CN104579577B - The apparatus and method for realizing 100GBase CR4 PCS Key ditherings - Google Patents
The apparatus and method for realizing 100GBase CR4 PCS Key ditherings Download PDFInfo
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- CN104579577B CN104579577B CN201510047312.2A CN201510047312A CN104579577B CN 104579577 B CN104579577 B CN 104579577B CN 201510047312 A CN201510047312 A CN 201510047312A CN 104579577 B CN104579577 B CN 104579577B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
- H04L1/0042—Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Abstract
Present invention is disclosed a kind of apparatus and method for realizing 100GBase CR4 PCS Key ditherings, wherein, the device is physically entered passage including 4, any passage that is physically entered is corresponding with 5 PCS passages, it is characterized in that, device also includes being physically entered the corresponding 4 groups of de-jitter buffers of passage with 4, and 4 groups of de-jitter buffers are used to carry out Key dithering to 5 PCS passages corresponding to respective physical input channel respectively.The present invention realizes that the apparatus and method of 100GBase CR4 PCS Key ditherings are by configuring a de-jitter buffer for each passage that is physically entered in 100GBase CR4, to corresponding multiple PCS passages Key ditherings, to reduce the power consumption and area of chip respectively.
Description
Technical field
The present invention relates to network communication field, more particularly to a kind of device for realizing 100GBase-CR4 PCS Key ditherings and
Method.
Background technology
100GBase-CR4 is the physical interface type defined by IEEE802.3.It is defeated that 100GBase-CR4 includes 4 physics
Enter passage and 20 PCS passages, every PCS passage has different alignment marks.Key dithering（deskew）It is to disappear
Except each bar passage caused shake in transmitting procedure in physical interface, and make the alignment of data of each passage.For 100GBase-
CR4, if every PCS passage all configures a de-jitter buffer and carries out Key dithering, that just needs 20 de-jitter buffers,
Cause the power consumption of chip too high, and add the area of chip.
The content of the invention
It is an object of the invention to provide a kind of apparatus and method for realizing 100GBase-CR4 PCS Key ditherings.
One of for achieving the above object, an embodiment of the present invention provides one kind and realizes 100GBase-CR4 PCS
The device of Key dithering, it includes 4 and is physically entered passage, it is any it is described be physically entered passage and be corresponding with 5 PCS passages, it is described
Device also includes being physically entered the corresponding 4 groups of de-jitter buffers of passage with described 4, and 4 groups of de-jitter buffers are used for
Key dithering is carried out to 5 PCS passages corresponding to respective physical input channel respectively.
As the further improvement of an embodiment of the present invention, described device also includes mark module and comparing module；Institute
De-jitter buffer is stated to be used for：
The valid data of corresponding physics input channel input are received, and the valid data are judged by the comparing module
Whether it is alignment mark；If so,
The type of the alignment mark and the position in the de-jitter buffer are recorded, and by each alignment mark in institute
State the write pointer that the position in de-jitter buffer is arranged to alignment mark；
The alignment mark signal of PCS passages corresponding with each alignment mark is put 1 by the mark module；
Judge in the de-jitter buffer whether be that corresponding PCS leads to by the comparing module at interval of predetermined amount of data
The alignment mark in road；If so,
Each alignment mark is locked.
As the further improvement of an embodiment of the present invention, the comparing module is additionally operable to：
At interval of predetermined amount of data judge in the de-jitter buffer whether be corresponding PCS passages alignment mark, if
It is determined as continuous 4 times no, then the de-jitter buffer unlocks each alignment mark.
As the further improvement of an embodiment of the present invention, described device also includes determining whether module, the determination module
For：
Whether the alignment mark signal for judging all PCS passages is all whether 1 and corresponding alignment mark are all locked；
If so,
The read pointer for the PCS passages that described 4 are physically entered corresponding to passage by 4 groups of de-jitter buffers is set
The write pointer of alignment mark in PCS passages corresponding to being set to.
As the further improvement of an embodiment of the present invention, the comparing module is additionally operable to：
Judge whether the write pointer of the alignment mark of the PCS passages is equal to read pointer；If so,
The mark module is additionally operable to the signal for reading the PCS passages alignment mark putting 1；Wherein,
If in synchronization, the alignment mark of the PCS passages is all locked, the alignment mark type of the PCS passages
It is different from, and it is all 1 that the PCS passages, which read the signal of alignment mark, then the determination module judges the Key dithering
Buffer Key dithering is completed.
As the further improvement of an embodiment of the present invention, described device also includes order module；The order module
For：
The data read from 4 groups of de-jitter buffers are ranked up according to the type of each alignment mark.
As the further improvement of an embodiment of the present invention, the mark module is additionally operable to：
If the write pointer of the de-jitter buffer is identical with the position where each alignment mark, the correspondence that will be recorded
The write pointer of alignment mark and the signal removal for reading alignment mark.
To realize above-mentioned another goal of the invention, the present invention provides a kind of side for realizing 100GBase-CR4 PCS Key ditherings
Method, the 100GBase-CR4 are physically entered passage including 4, it is any it is described be physically entered passage and be corresponding with 5 PCS passages,
Methods described is physically entered the corresponding 4 groups of de-jitter buffers of passage with defeated to respective physical respectively by configuring with described 4
Enter 5 PCS passages corresponding to passage and carry out Key dithering.
As the further improvement of an embodiment of the present invention, methods described also includes：
De-jitter buffer receives the valid data of corresponding physics input channel input, and whether judges the valid data
For alignment mark；If so,
The type of the alignment mark and the position in the de-jitter buffer are recorded, and by each alignment mark in institute
State the write pointer that the position in de-jitter buffer is arranged to alignment mark；
The alignment mark signal of PCS passages corresponding with each alignment mark is put 1；
Judge in the de-jitter buffer whether be that corresponding PCS leads to by the comparing module at interval of predetermined amount of data
The alignment mark in road；If so,
Each alignment mark is locked.
As the further improvement of an embodiment of the present invention, methods described also includes：
At interval of predetermined amount of data judge in the de-jitter buffer whether be corresponding PCS passages alignment mark,
If being determined as continuous 4 times no, each alignment mark is unlocked.
As the further improvement of an embodiment of the present invention, methods described also includes：
Whether the alignment mark signal for judging all PCS passages is all whether 1 and corresponding alignment mark are all locked；
If so,
The read pointer for the PCS passages that described 4 are physically entered corresponding to passage is arranged to align in corresponding PCS passages
The write pointer of mark.
As the further improvement of an embodiment of the present invention, methods described also includes：
Judge whether the write pointer of the alignment mark of the PCS passages is equal to read pointer；If so,
The signal for reading the PCS passages alignment mark is put 1；Wherein,
If in synchronization, the alignment mark of the PCS passages is all locked, the alignment mark type of the PCS passages
It is different from, and it is all 1 that the PCS passages, which read the signal of alignment mark, then judges the de-jitter buffer Key dithering
Complete.
As the further improvement of an embodiment of the present invention, methods described also includes：
The data read from 4 groups of de-jitter buffers are ranked up according to the type of each alignment mark.
As the further improvement of an embodiment of the present invention, methods described also includes：
If the write pointer of the de-jitter buffer is identical with the position where each alignment mark, the correspondence that will be recorded
The write pointer of alignment mark and the signal removal for reading alignment mark.
Relative to prior art, the technical effects of the invention are that：The present invention's realizes 100GBase-CR4 PCS debounces
Dynamic apparatus and method for each passage that is physically entered in 100GBase-CR4 by configuring a de-jitter buffer, to divide
It is other to corresponding multiple PCS passages Key ditherings, reduce the power consumption and area of chip.
Brief description of the drawings
Fig. 1 is the module diagram for the device that 100GBase-CR4 PCS Key ditherings are realized in an embodiment of the present invention；
Fig. 2 is the schematic device for the device that 100GBase-CR4 PCS Key ditherings are realized in an embodiment of the present invention；
Fig. 3 is the operating diagram for the device that 100GBase-CR4 PCS Key ditherings are realized in an embodiment of the present invention.
Embodiment
Below with reference to embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that one of ordinary skill in the art is made according to these embodiments, method or functionally
Conversion is all contained in protection scope of the present invention.
Join Fig. 1 to Fig. 3, introduce the specific implementation that the present invention realizes the device 100 of 100GBase-CR4 PCS Key ditherings
Mode.In the present embodiment, the device 100 includes 4 groups of de-jitter buffers 10.
100GBase-CR4 has 4 and is physically entered passage and 20 PCS passages, in present embodiment, for
Every of 100GBase-CR4 is physically entered passage and configures a de-jitter buffer 10, and each de-jitter buffer 10 is distinguished
Correspond to 5 PCS passages in 100GBase-CR4.Direction is received in 100GBase-CR4 PCS, this 4 are physically entered passage
Need to carry out Key dithering, and be physically entered at every on passage, all include 5 alignment marks, therefore need altogether to 4 physics
20 alignment marks of input channel are handled, and realize the Key dithering to 20 PCS passages.
In the present embodiment, de-jitter buffer 10 is used for respectively to 5 PCS corresponding to respective physical input channel
Passage carries out Key dithering.The present invention's realizes that the device 100 of 100GBase-CR4 PCS Key ditherings also includes the He of mark module 30
Comparing module 20；Wherein,
De-jitter buffer 10 is specifically used for：
The valid data of corresponding physics input channel input are received, and whether the valid data are judged by comparing module 20
For alignment mark；If so, recording the type of the alignment mark and the position in the de-jitter buffer 10, and each alignment is marked
Aim at the write pointer that the position in the de-jitter buffer 10 is arranged to alignment mark.
Due to every data for being physically entered passage and actually contains 5 PCS passages, so in a corresponding debounce
It is the data for writing into 5 PCS passages in sequence in dynamic buffer 10.Correspondingly, every PCS passage writes into Key dithering buffering
The pointer of device 10 have one plus 5 processing.For example, when the data of PCS passages 0 write into de-jitter buffer 10 for the first time, its
Write pointer is 0, and the write pointer that it writes into de-jitter buffer 10 for the second time just should be 5, and other PCS channel datas write finger
Pin is by that analogy.Therefore in the present embodiment, 10 complete write operations of de-jitter buffer are actual to contain 5 times continuously
Write operation.
Similarly, in the data in reading de-jitter buffer 10, the read pointer of corresponding PCS passages also can be each
Have during reading one plus 5 processing, 10 complete read operations of de-jitter buffer actually also contains 5 times and continuous read
Operation, the data of 5 different PCS passages could all be read.
Simultaneously as the alignment mark of 5 PCS passages can be continuously write into a de-jitter buffer 10, therefore work as
Comparing module 20 judges a valid data when being alignment mark, then can accordingly judge what is write into after the alignment mark
4 valid data（Valid data in i.e. specific data volume）Also it is alignment mark, and can correspondingly records 4 significant figures
According to alignment mark type and the position in de-jitter buffer 10.Certainly, in the implementation process of reality, connect for this
4 valid data, it is still desirable to which comparing module 20 carries out further comparing, to confirm 4 significant figures respectively
According to alignment mark type.
De-jitter buffer 10 is additionally operable to the alignment mark signal by PCS passages corresponding to each alignment mark by identifying mould
Block 30 puts 1, and judges whether formerly recorded in the de-jitter buffer 10 by comparing module 20 every predetermined amount of data
All types of alignment mark, if so, then locking each alignment mark.
Whether " being the alignment mark type formerly recorded " mentioned here substantially comprises two layers of definition, i.e.,：From detection
Start to first alignment mark, 1. whether needed to detect in the de-jitter buffer 10 comprising alignment at interval of predetermined amount of data
Mark；And 2. whether the type of the alignment mark is identical with the alignment mark having previously detected.In the present embodiment, due to going
Meeting 5 alignment marks of continued presence in wobble buffer 10, if the alignment mark 0 ~ 4 detected for the first time, and posterior detection
In, if any one in the alignment mark detected and the difference that has previously detected（Such as alignment mark 0,1,2,3,5）, then sentence
The type of alignment mark of the alignment mark type detected after being scheduled on from having previously detected is different.
If there is the alignment mark type that the alignment mark type and record detected is judged in rear detection of continuous 4 times
Difference, then the above-mentioned alignment mark that has been locked need to be relocked.
During above-mentioned, if the write pointer of de-jitter buffer 10 is identical with the position where each alignment mark,
The write pointer for the corresponding alignment mark for then needing to record and the signal removal for reading alignment mark.Such way, be in order to
Ensure the degree of jitter of each bar PCS passages in the maximum Key dithering limit of power of corresponding de-jitter buffer 10.
In the present embodiment, realize that the device 100 of 100GBase-CR4 PCS Key ditherings also includes determining whether module 40, should
Determination module 40 be used for judge all PCS passages alignment mark signal whether all for 1 and corresponding alignment mark whether all
It is locked；If so, the read pointer of 4 PCS being physically entered corresponding to passage passages is set by 4 groups of de-jitter buffers 10
For the write pointer of alignment mark in corresponding PCS passages.Now, that is, complete to remove 20 PCS passages in 100GBase-CR4
Dither operation, and due to the read pointer of PCS passages to be arranged to the write pointer of alignment mark in PCS passages, buffered from Key dithering
The data read out in device 10 are exactly to complete the later data of Key dithering.
After all PCS passages complete Key dithering, in the data in reading de-jitter buffer 10, comparing module 20
It is additionally operable to judge whether the write pointer of the alignment mark of PCS passages is equal to read pointer；If so, mark module 30 is additionally operable to read
The signal of PCS passage alignment marks puts 1；Wherein, it is if right corresponding to 20 PCS passages in synchronization, 100GBase-CR4
Neat mark is all locked, the alignment mark type of 20 PCS passages is different from（Different PCS passages are represented respectively）, with
And it is all 1 that 20 PCS passages, which read the signal of alignment mark, then determination module 40 judges that the Key dithering of de-jitter buffer 10 is complete
Into.Now, namely in 100GBase-CR4 the alignment of data of 20 PCS passages is debounce that is successful, being carried out to valid data
Dynamic is effective.And if any in above-mentioned condition can not be met, then it represents that Key dithering process mistake occurs, it is necessary to enter again
Row Key dithering.
In the present embodiment, realizing the device 100 of 100GBase-CR4 PCS Key ditherings also includes order module 50, should
Order module 50 is used to be ranked up the data read from 4 de-jitter buffers 10 according to each alignment mark type.Respectively
The alignment mark of type represents a PCS passage respectively, in reading process, in order to ensure the orderly of output data, it is necessary to according to
The data read from 4 de-jitter buffers 10 are ranked up according to the order of default PCS passages.
Join Fig. 1 to Fig. 3, introduce the specific embodiment party that the present invention realizes the method for 100GBase-CR4 PCS Key ditherings
Formula.In the present embodiment, this method is physically entered the corresponding 4 groups of debounces of passage by configuring with 4 in 100GBase-CR4
Dynamic buffer 10 is with respectively to 5 PCS passages progress Key dithering corresponding to respective physical input channel.
100GBase-CR4 has 4 and is physically entered passage and 20 PCS passages, in present embodiment, for
Every of 100GBase-CR4 is physically entered passage and configures a de-jitter buffer 10, and each de-jitter buffer 10 is distinguished
Correspond to 5 PCS passages in 100GBase-CR4.Direction is received in 100GBase-CR4 PCS, this 4 are physically entered passage
Need to carry out Key dithering, and be physically entered at every on passage, all include 5 alignment marks, therefore need altogether to 4 physics
20 alignment marks of input channel are handled, and realize the Key dithering to 20 PCS passages.
In the present embodiment, realize that the method for 100GBase-CR4 PCS Key ditherings specifically includes：
De-jitter buffer 10 receives the valid data of corresponding physics input channel input, and whether judges the valid data
For alignment mark；If so, recording the type of the alignment mark and the position in the de-jitter buffer 10, and each alignment is marked
Aim at the write pointer that the position in the de-jitter buffer 10 is arranged to alignment mark.
Due to every data for being physically entered passage and actually contains 5 PCS passages, so in a corresponding debounce
It is the data for writing into 5 PCS passages in sequence in dynamic buffer 10.Correspondingly, every PCS passage writes into Key dithering buffering
The pointer of device 10 have one plus 5 processing.For example, when the data of PCS passages 0 write into de-jitter buffer 10 for the first time, its
Write pointer is 0, and the write pointer that it writes into de-jitter buffer 10 for the second time just should be 5, and other PCS channel datas write finger
Pin is by that analogy.Therefore in the present embodiment, 10 complete write operations of de-jitter buffer are actual to contain 5 times continuously
Write operation.
Similarly, in the data in reading de-jitter buffer 10, the read pointer of corresponding PCS passages also can be each
Have during reading one plus 5 processing, 10 complete read operations of de-jitter buffer actually also contains 5 times and continuous read
Operation, the data of 5 different PCS passages could all be read.
Simultaneously as the alignment mark of 5 PCS passages can be continuously write into a de-jitter buffer 10, therefore examine
When to measure a valid data be alignment mark, then 4 valid data write into after the alignment mark can be accordingly judged
（Valid data in i.e. specific data volume）Also it is alignment mark, and can correspondingly records the alignment mark of 4 valid data
Will type and the position in de-jitter buffer 10.Certainly, in the implementation process of reality, have for 4 then
Imitate data, it is still desirable to which comparing module 20 carries out further comparing, to confirm the alignment mark of 4 valid data respectively
The type of will.
De-jitter buffer 10 is additionally operable to the alignment mark signal by PCS passages corresponding to each alignment mark by identifying mould
Block 30 puts 1, and judges whether formerly recorded in the de-jitter buffer 10 by comparing module 20 every predetermined amount of data
All types of alignment mark, if so, then locking each alignment mark.
Whether " being the alignment mark type formerly recorded " mentioned here substantially comprises two layers of definition, i.e.,：From detection
Start to first alignment mark, 1. need to detect in the de-jitter buffer 10 whether include alignment at interval of predetermined amount of data
Mark；And 2. whether the type of the alignment mark is identical with the alignment mark having previously detected.In the present embodiment, due to going
Meeting 5 alignment marks of continued presence in wobble buffer 10, if the alignment mark 0 ~ 4 detected for the first time, and posterior detection
In, if any one in the alignment mark detected and the difference that has previously detected（Such as alignment mark 0,1,2,3,5）, then sentence
The type of alignment mark of the alignment mark type detected after being scheduled on from having previously detected is different.
If there is the alignment mark type that the alignment mark type and record detected is judged in rear detection of continuous 4 times
Difference, then the above-mentioned alignment mark that has been locked need to be relocked.
During above-mentioned, if the write pointer of de-jitter buffer 10 is identical with the position where each alignment mark,
Then by the write pointer for the corresponding alignment mark recorded and the signal removal for reading alignment mark.Such way, it is to ensure
The degree of jitter of each bar PCS passages is in the maximum Key dithering limit of power of corresponding de-jitter buffer 10.
In the present embodiment, realize that the device 100 of 100GBase-CR4 PCS Key ditherings also includes determining whether module 40, should
Determination module 40 be used for judge all PCS passages alignment mark signal whether all for 1 and corresponding alignment mark whether all
It is locked；If so, the read pointer of 4 PCS being physically entered corresponding to passage passages is set by 4 groups of de-jitter buffers 10
For the write pointer of alignment mark in corresponding PCS passages.Now, that is, complete to remove 20 PCS passages in 100GBase-CR4
Dither operation, and due to the read pointer of PCS passages to be arranged to the write pointer of alignment mark in PCS passages, buffered from Key dithering
The data read out in device 10 are exactly to complete the later data of Key dithering.
After all PCS passages complete Key dithering, in the data in reading de-jitter buffer 10, it is also necessary to judge
Whether the write pointer of the alignment mark of PCS passages is equal to read pointer；If so, then the signal for reading PCS passage alignment marks is put
1；Wherein, if alignment mark corresponding to 20 PCS passages is all locked in synchronization, 100GBase-CR4,20 PCS lead to
The alignment mark type in road is different from（Different PCS passages are represented respectively）And 20 PCS passages read alignment mark
Signal be all 1, then judge that de-jitter buffer 10 Key dithering is completed.Now, 20 PCS passages namely in 100GBase-CR4
Alignment of data be it is successful, to valid data carry out Key dithering be effective.And if can not meet in above-mentioned condition
It is any, then it represents that Key dithering process mistake occurs, it is necessary to re-start Key dithering.
In the present embodiment, realizing the method for 100GBase-CR4 PCS Key ditherings also includes according to each alignment mark class
Type is ranked up to the data read from 4 de-jitter buffers 10.All types of alignment marks represents a PCS and led to respectively
Road, in reading process, in order to ensure the orderly, it is necessary to which the order according to default PCS passages will be from 4 debounces of the data of output
The data read in dynamic buffer 10 are ranked up.
A specific embodiment introduced below.
In the device of concrete implementation 100GBase-CR4 PCS Key ditherings, it is physically entered passage for 4 and is respectively configured one
Individual depth 96, width 66bit de-jitter buffer.The actual number for containing 5 PCS passages of passage is physically entered due to every
According to so in a de-jitter buffer, the depth for the de-jitter buffer that each PCS channel allocations are arrived is 19, and debounce
The depth of the actual use of dynamic buffer is 95, when read/write pointer is 94, can be clearly 0 by read/write pointer, realize significant figure
According to recurrent wrIting and reading.
In the write operation of de-jitter buffer, 66bit valid data can be write successively corresponding to each PCS passages
In de-jitter buffer.While de-jitter buffer is write, it can judge whether the valid data are alignment mark, if
Be then record be corresponding any bar PCS passage alignment mark and the alignment mark be written to position in de-jitter buffer
Put；In the process, a de-jitter buffer can be continuously written into the alignment mark of 5 PCS passages, and be remembered respectively
Record.Meanwhile it will represent that those PCS Air conduct measurements put 1 to alignment mark signal.
If the write pointer of alignment mark of the write pointer of de-jitter buffer with recording is equal, the alignment can be marked
The write pointer of will and put 1 signal and all remove.
Since being detected first alignment mark, at interval of 16383 groups of 66bit data（That is predetermined amount of data）Afterwards, then
It is secondary detect the de-jitter buffer in whether be the alignment mark having previously detected type；Lead to if it is, representing corresponding PCS
Alignment mark is correct in road, has been locked out.After alignment mark is locked, at interval of 16383 groups of 66bit data
（That is predetermined amount of data）, will detect in the de-jitter buffer whether be the alignment mark having previously detected type, if
The type of alignment mark of the type of continuous 4 alignment marks detected all from having previously detected is different, then it is right to need again
Those alignment marks are locked.
When the alignment mark signal of 20 PCS passages corresponding to 4 de-jitter buffers is all 1, and every PCS passage
Alignment mark it is all locked when, then it represents that 20 PCS passages have been detected simultaneously by alignment mark in a window period, this
When, the read pointer for 5 PCS passages that every is physically entered in passage is all set to writing for the alignment mark each recorded
Pointer, complete to operate the Key dithering of 20 PCS passages.
When all PCS passages complete Key dithering operation after, read de-jitter buffer data when, if read pointer with
The write pointer of alignment mark is equal, then the signal for representing to read alignment mark is put into 1.If buffered in a complete Key dithering
After the read operation of device, the signal that alignment mark is read in the expressions of all PCS passages is all 1, and the alignment mark of 20 PCS passages
All locked, the type of 20 alignment marks is all different（Represent different PCS passages）, then the data of 20 PCS passages
Alignment is successful, and the Key dithering operation carried out to data is effective.If above-mentioned condition can not all meet, illustrate
Shake mistake occurs, it is necessary to Key dithering again.
After the data in reading de-jitter buffer, it is necessary to according to the PCS passages of each alignment mark representative, to 20 groups of numbers
According to being resequenced.
In summary, the apparatus and method for realizing 100GBase-CR4 PCS Key ditherings of the invention by for
Each passage that is physically entered in 100GBase-CR4 configures a de-jitter buffer, to lead to respectively to corresponding multiple PCS
Road Key dithering, reduce the power consumption and area of chip.
It is apparent to those skilled in the art that for convenience and simplicity of description, the device of foregoing description,
The specific work process of device and module, the corresponding process in method embodiment is may be referred to, will not be repeated here.
In several embodiments provided by the present invention, it should be understood that disclosed device, apparatus and method can
To realize by another way.For example, device embodiments described above are only schematical, for example, the mould
The division of block, only a kind of division of logic function can have an other dividing mode when actually realizing, for example, multiple modules or
Component can combine or be desirably integrated into another device, or some features can be ignored, or not perform.It is another, show
Show or the mutual coupling discussed or direct-coupling or communication connection can be by some interfaces, between device or module
Coupling or communication connection are connect, can be electrical, mechanical or other forms.
The module illustrated as separating component can be or may not be physically separate, show as module
The part shown can be or may not be physical module, you can with positioned at a place, or can also be distributed to multiple
On mixed-media network modules mixed-media.Some or all of module therein can be selected to realize present embodiment scheme according to the actual needs
Purpose.
In addition, each functional module in each embodiment of the present invention can be integrated in a processing module, also may be used
To be that modules are individually physically present, can also 2 or 2 be integrated in upper module in a module.Above-mentioned integrated mould
Block can both be realized in the form of hardware, can also be realized in the form of hardware adds software function module.
The above-mentioned integrated module realized in the form of software function module, can be stored in one and computer-readable deposit
In storage media.Above-mentioned software function module is stored in a storage medium, including some instructions are causing a computer
Device（Can be personal computer, server, or network equipment etc.）Or processor（processor）It is each to perform the present invention
The part steps of embodiment methods described.And foregoing storage medium includes：USB flash disk, mobile hard disk, read-only storage（Read-
Only Memory, ROM）, random access memory（Random Access Memory, RAM）, magnetic disc or CD etc. it is various
Can be with the medium of store program codes.
Finally it should be noted that：Embodiment of above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to aforementioned embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing each embodiment can so be modified, or which part technical characteristic is equal
Replace；And these modifications or replacement, the essence of appropriate technical solution is departed from each embodiment technical scheme of the present invention
Spirit and scope.
Claims (14)
1. a kind of device for realizing 100GBase-CR4 PCS Key ditherings, it includes 4 and is physically entered passage, any physics
Input channel is corresponding with 5 PCS passages, it is characterised in that described device is also corresponding including being physically entered passage with described 4
4 groups of de-jitter buffers, 4 groups of de-jitter buffers are used to respectively lead to 5 PCS corresponding to respective physical input channel
Road carries out Key dithering.
2. the device according to claim 1 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that described device
Also include mark module and comparing module；The de-jitter buffer is used for：
The valid data of corresponding physics input channel input are received, and whether the valid data are judged by the comparing module
For alignment mark；If so,
The type of the alignment mark and the position in the de-jitter buffer are recorded, and each alignment mark is gone described
Position in wobble buffer is arranged to the write pointer of alignment mark；
The alignment mark signal of PCS passages corresponding with each alignment mark is put 1 by the mark module；
Judge in the de-jitter buffer whether be corresponding PCS passages by the comparing module at interval of predetermined amount of data
Alignment mark；If so,
Each alignment mark is locked.
3. the device according to claim 2 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that the comparison
Module is additionally operable to：
At interval of predetermined amount of data judge in the de-jitter buffer whether be corresponding PCS passages alignment mark, if continuous 4
Secondary to be determined as no, then the de-jitter buffer unlocks each alignment mark.
4. the device according to claim 2 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that described device
Module is also included determining whether, the determination module is used for：
Whether the alignment mark signal for judging all PCS passages is all whether 1 and corresponding alignment mark are all locked；If
It is,
The read pointer for the PCS passages that described 4 are physically entered corresponding to passage by 4 groups of de-jitter buffers is arranged to
The write pointer of alignment mark in corresponding PCS passages.
5. the device according to claim 4 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that the comparison
Module is additionally operable to：
Judge whether the write pointer of the alignment mark of the PCS passages is equal to read pointer；If so,
The mark module is additionally operable to the signal for reading the PCS passages alignment mark putting 1；Wherein,
If in synchronization, the alignment mark of the PCS passages is all locked, and the alignment mark type of the PCS passages is not
It is identical, and it is all 1 that the PCS passages, which read the signal of alignment mark, then the determination module judges the Key dithering buffering
Device Key dithering is completed.
6. the device according to claim 5 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that described device
Also include order module；The order module is used for：
The data read from 4 groups of de-jitter buffers are ranked up according to the type of each alignment mark.
7. the device according to claim 2 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that the mark
Module is additionally operable to：
If the write pointer of the de-jitter buffer is identical with the position where each alignment mark, corresponding to for recording is alignd
The write pointer of mark and the signal removal for reading alignment mark.
8. a kind of method for realizing 100GBase-CR4 PCS Key ditherings, the 100GBase-CR4 is physically entered logical including 4
Road, it is any described to be physically entered passage and be corresponding with 5 PCS passages, it is characterised in that methods described is by configuring and described 4
4 groups of de-jitter buffers corresponding to passage are physically entered to enter respectively to 5 PCS passages corresponding to respective physical input channel
Row Key dithering.
9. the method according to claim 8 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that methods described
Also include：
De-jitter buffer receives the valid data of corresponding physics input channel input, and judges whether the valid data are pair
Neat mark；If so,
The type of the alignment mark and the position in the de-jitter buffer are recorded, and each alignment mark is gone described
Position in wobble buffer is arranged to the write pointer of alignment mark；
The alignment mark signal of PCS passages corresponding with each alignment mark is put 1；
At interval of predetermined amount of data, judge in the de-jitter buffer whether be the alignment mark for corresponding to PCS passages；If
It is,
Each alignment mark is locked.
10. the method according to claim 8 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that the side
Method also includes：
At interval of predetermined amount of data judge in the de-jitter buffer whether be corresponding PCS passages alignment mark, if continuous 4
It is secondary to be determined as no, then each alignment mark is unlocked.
11. the method according to claim 8 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that the side
Method also includes：
Whether the alignment mark signal for judging all PCS passages is all whether 1 and corresponding alignment mark are all locked；If
It is,
The read pointer for the PCS passages that described 4 are physically entered corresponding to passage is arranged to alignment mark in corresponding PCS passages
Write pointer.
12. the method according to claim 11 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that the side
Method also includes：
Judge whether the write pointer of the alignment mark of the PCS passages is equal to read pointer；If so,
The signal for reading the PCS passages alignment mark is put 1；Wherein,
If in synchronization, the alignment mark of the PCS passages is all locked, and the alignment mark type of the PCS passages is not
It is identical, and it is all 1 that the PCS passages, which read the signal of alignment mark, then judges that the de-jitter buffer Key dithering is completed.
13. the method according to claim 12 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that the side
Method also includes：
The data read from 4 groups of de-jitter buffers are ranked up according to the type of each alignment mark.
14. the method according to claim 8 for realizing 100GBase-CR4 PCS Key ditherings, it is characterised in that the side
Method also includes：
If the write pointer of the de-jitter buffer is identical with the position where each alignment mark, corresponding to for recording is alignd
The write pointer of mark and the signal removal for reading alignment mark.
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| CN101841744A (en) * | 2009-03-17 | 2010-09-22 | 华为技术有限公司 | Transmitting method and device of hundred gigabit Ethernet in optical transmission network |
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