CN104576326A - Method and system for preparing silicon-based III-V gallium arsenide semiconductor material - Google Patents
Method and system for preparing silicon-based III-V gallium arsenide semiconductor material Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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Abstract
The invention provides a method and a system for preparing a silicon-based III-V gallium arsenide semiconductor material. The method comprises the following steps: preparing a silicon dioxide film on a clean single crystal silicon substrate surface; obtaining a silicon dioxide nanometer pattern layer on the silicon dioxide film by adopting the nanometer imprinting technology, wherein the silicon dioxide nanometer pattern layer comprises a growth window area exposed on the single crystal silicon substrate surface and a silicon dioxide pattern area, and the growth window area and the silicon dioxide pattern area are arranged in a staggered manner; depositing a galium arsenide buffer layer on the growth window area, wherein the height of the galium arsenide buffer layer is close to or equal to that of a table surface of the silicon dioxide pattern area; growing the III-V semiconductor material on the galium arsenide buffer layer and the silicon dioxide pattern area in an extension manner. According to the method, the silicon dioxide nanometer pattern layer is prepared by adopting the nanometer imprinting technology to be used as a pattern substrate for growth of the semiconductor material, and the problem of limitation of material sizes is solved, so that the growth and the preparation of industrial materials are facilitated, the material production cost is effectively lowered, and the method has a broad application prospect.
Description
Technical field
The present invention relates to field of semiconductor materials, particularly relate to a kind of silica-based iii-v gallium arsenide semiconductor material preparation method and system.
Background technology
Lattice that is unstressed, low-dislocation-density large mismatched heterostructures material epitaxy growing technology is one of main development direction of opto-electronic device of future generation and multifunctional photoelectric integrated chip.Particularly, the iii-v direct gap semiconductor materials such as silicon materials full-fledged in microelectronic technique and GaAs are combined in high quality become the preferred plan of optoelectronic integrated technology.But on a silicon substrate, the III-V group semi-conductor material such as epitaxial growth device level GaAs (GaAs) are difficult problems for silica-base material research field in the world always.
In order to solve this difficult problem, scheme prepared by the main material adopted both at home and abroad has: hypo-hyperthermia two-step method, graph substrate method, thermal annealing method, strained super lattice barrier layer method etc.At present, in order to reduce dislocation density better, generally based on two-step method, use simultaneously comprehensive to graph substrate method, thermal annealing method and strained super lattice barrier layer method.Owing to being subject to the restriction of lattice mismatch stress and III-V group semi-conductor material horizontal extension characteristic, research shows, employing nano-scale is that the silicon graphics substrate of 100 ~ 200nm is more suitable for silica-based upper III-V group semi-conductor material growth preparation, can more effectively discharge epitaxial loayer stress, fall low threading dislocation density.In recent years, in order to prepare silicon graphics substrate, external and more domestic seminar mainly adopt the methods such as laser hologram, electron beam exposure and self-assembly for nanosphere.
But the above-mentioned method preparing silicon graphics substrate is not ideal, the maximum substrate dimension that can prepare can only be mm magnitude, more large-area graph substrate cannot be obtained, the cost of manufacture that result in material is too high, the technical problem that the Material growth preparation that can not meet industrialization requires, limits the application prospect of material.
Summary of the invention
(1) technical problem that will solve
The invention provides a kind of silica-based iii-v gallium arsenide semiconductor material preparation method and system, to solve in prior art the technical problem that cannot manufacture the silica-based extension III-V group semi-conductor material of large-sized high-quality.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of silica-based iii-v gallium arsenide semiconductor material preparation method, comprising:
Silicon dioxide film is prepared on clean monocrystalline substrate surface;
On described silicon dioxide film, nanometer embossing is adopted to obtain silica nanometer graph layer, described silica nanometer graph layer comprises the growth window district on exposed monocrystalline substrate surface, and silicon dioxide graph area, and growth window district and silicon dioxide graph area are interspersed;
In described growth window district, deposition close to or equal the GaAs buffer layer of table surface height of described silicon dioxide graph area;
In described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material.
Further,
Described before silicon dioxide film is prepared on clean monocrystalline substrate surface, also comprise: utilize Wet chemical cleaning method to process monocrystalline substrate;
And/or described silicon dioxide film of preparing comprises: utilize plasma enhanced chemical vapor deposition method or thermal oxidation process, deposit thickness is the uniform silicon dioxide film of thickness of 400nm;
And/or, described monocrystalline substrate is the highly doped low-drag type of intrinsic-OR, aufwuchsplate is <100>, crystal face deflection <110> or <111> crystal face 4 ° ~ 6 °, thickness is 330 ~ 370 μm.
Further,
Described employing nanometer embossing obtains silica nanometer graph layer and comprises: utilize electron beam lithography to make the nano-imprint stamp with nano-scale cycle graph, nano-imprint lithography glue is spun on silicon oxide film surface, thickness is 200nm, toasts 2 minutes at 140 DEG C of temperature; Again template is placed in the silicon oxide film surface scribbling photoresist, temperature be 130 DEG C, pressure keeps 2 minutes under being 3MPa, then reduces pressure be cooled to 50 DEG C of demouldings; Then, adopt reactive ion etching method to remove the primer of dented part, complete the transfer of nano graph to photoresist; Afterwards, take photoresist as mask, adopt dry etching technology removal without the silicon dioxide film of masked areas, form growth window district, complete the transfer of nano graph to silicon dioxide film;
Described nano-scale cycle graph is: the cycle graph of one-dimensional barcode structure or two-dimentional hole shape structure, and periodic dimensions is 100 ~ 200nm;
Described growth window district is of a size of: 50 ~ 100nm.
Further,
Describedly in described growth window district, deposit GaAs buffer layer comprise:
Utilize the GaAs material of the involuntary doping of MOCVD technology growth: first substrate is warmed up to 220 DEG C, toast 30 minutes in atmosphere of hydrogen; Then be warmed up to 750 DEG C, toast 15 minutes at hydrogen and arsine mist atmosphere; Cool to 400 ~ 420 DEG C again, growth a layer thickness is the GaAs nucleating layer of 18nm, and source flux is: trimethyl gallium 2.7 × 10
-5mol/min, arsine 6.5 × 10
-3mol/min, input V/III are than 240; Be warmed up to 650 ~ 680 DEG C after 10 minutes, the GaAs buffer layer that growth 300 ~ 400nm is thick, source flux is: trimethyl gallium 4.0 × 10
-5mol/min, arsine 4.0 × 10
-3mol/min, input V/III are than 100; Finally, the in-situ heat cycle annealing between hydrogen and arsine mist atmosphere carry out 350 to 750 DEG C, cycle annealing number of times is three times.
Further,
Describedly to comprise at described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material: utilize MOCVD technology, in 420 ~ 750 DEG C of temperature ranges, in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material, growth thickness is 1000-2000nm, and chamber pressure is 50 ~ 100Torr;
When described III-V group semi-conductor material is the GaAs of involuntary doping, epitaxially grown carrier gas is high-purity hydrogen, and the organic source of III is trimethyl gallium, and group V source is 99.999% high-purity arsine, and source flux is respectively: TMGa flow rate 4.0 × 10
-5mol/min, arsine flow 4.0 × 10
-3mol/min, input V/III ratio are 100.
On the other hand, the present invention also provides a kind of silica-based iii-v gallium arsenide semiconductor material preparation system, it is characterized in that, comprising: silicon dioxide prepares unit, nano graph prepares unit, buffer layer deposition unit and epitaxial growth unit, each sequence of unit is connected, wherein:
Silicon dioxide prepares unit, for preparing silicon dioxide film on clean monocrystalline substrate surface;
Nano graph prepares unit, for at described silicon dioxide film, nanometer embossing is adopted to obtain silica nanometer graph layer, described silica nanometer graph layer comprises the growth window district on exposed monocrystalline substrate surface, and silicon dioxide graph area, growth window district and silicon dioxide graph area are interspersed;
Buffer layer deposition unit, in described growth window district, deposition close to or equal the GaAs buffer layer of table surface height of described silicon dioxide graph area;
Epitaxial growth unit, in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material.
Further,
Described system also comprises: silicon chip processing unit, prepares unit be connected with described silicon dioxide, processes monocrystalline substrate for utilizing Wet chemical cleaning method;
And/or,
Described silicon dioxide is prepared unit and is comprised:
Chemical vapour deposition (CVD) subelement, for utilizing plasma enhanced chemical vapor deposition method, deposit thickness is the uniform silicon dioxide film of thickness of 400nm;
Or thermal oxidation subelement, for utilizing thermal oxidation process, forms the uniform silicon dioxide film of thickness that thickness is 400nm.
Further,
Described nano graph is prepared unit and is comprised:
Template preparation subelement, for utilizing electron beam lithography to make the nano-imprint stamp with nano-scale cycle graph, nano-imprint lithography glue is spun on silicon oxide film surface, and thickness is 200nm, toasts 2 minutes at 140 DEG C of temperature;
Demoulding subelement, for described template being placed in the silicon oxide film surface scribbling photoresist, temperature be 130 DEG C, pressure keeps 2 minutes under being 3MPa, then reduces pressure be cooled to 50 DEG C of demouldings;
Etching subelement, for the primer adopting reactive ion etching method to remove dented part, completes the transfer of nano graph to photoresist; Afterwards, take photoresist as mask, adopt dry etching technology removal without the silicon dioxide film of masked areas, form growth window district, complete the transfer of nano graph to silicon dioxide film;
Nano-scale cycle graph prepared by described Template preparation subelement is: the cycle graph of one-dimensional barcode structure or two-dimentional hole shape structure, and periodic dimensions is 100 ~ 200nm; Prepared growth window district is of a size of: 50 ~ 100nm.
Further, described buffer layer deposition unit comprises:
Deposition anneal subelement, for utilizing the GaAs material of the involuntary doping of MOCVD technology growth: first substrate is warmed up to 220 DEG C, toasts 30 minutes in atmosphere of hydrogen; Then be warmed up to 750 DEG C, toast 15 minutes at hydrogen and arsine mist atmosphere; Cool to 400 ~ 420 DEG C again, growth a layer thickness is the GaAs nucleating layer of 18nm, and source flux is: trimethyl gallium 2.7 × 10
-5mol/min, arsine 6.5 × 10
-3mol/min, input V/III are than 240; Be warmed up to 650 ~ 680 DEG C after 10 minutes, the GaAs buffer layer that growth 300 ~ 400nm is thick, source flux is: trimethyl gallium 4.0 × 10
-5mol/min, arsine 4.0 × 10
-3mol/min, input V/III are than 100; Finally, the in-situ heat cycle annealing between hydrogen and arsine mist atmosphere carry out 350 to 750 DEG C, cycle annealing number of times is three times.
Further,
Described epitaxial growth unit comprises: vapour phase epitaxy deposition subelement, for utilizing MOCVD technology, in 420 ~ 750 DEG C of temperature ranges, in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material, growth thickness is 1000-2000nm, and chamber pressure is 50 ~ 100Torr;
And/or GaAs deposition subelement, for controlling the gallium arsenide epitaxial growth of involuntary doping, wherein epitaxially grown carrier gas is high-purity hydrogen, the organic source of III is trimethyl gallium, and group V source is 99.999% high-purity arsine, and source flux is respectively: TMGa flow rate 4.0 × 10
-5mol/min, arsine flow 4.0 × 10
-3mol/min, input V/III ratio are 100.
(3) beneficial effect
In the silica-based iii-v gallium arsenide semiconductor material preparation method and system of the present invention's proposition, adopt the fabrication techniques silica nanometer graph layer of nano impression, be used as the graph substrate of semiconductor material growing, and continue epitaxial growth GaAs buffer layer and III-V group semi-conductor material on this basis.The graph substrate technology of preparing of this nano impression broken before scantling restricted problem, advantageously prepare in industrialized Material growth, significantly reduce material cost of manufacture, be with a wide range of applications.
In addition, for the situation that dimension of picture is less, several preparation method of the prior art not easily prepares high-quality graph substrate, and the nanometer embossing adopted in the present invention is easy to realize the high-quality graph substrate preparation of small size, depth-width ratio and the sidewall steepness of coining pattern can be changed as required, thus control the degree of depth and the sidewall profile of figure.The present invention can utilize the graph substrate of nano-scale to reduce the strain energy of material in fact, thus greatly improve the critical thickness that material produces dislocation, simultaneously by the side direction dislocation barrier effect of silicon dioxide figure table top, stop that the threading dislocation of the overwhelming majority continues to propagate to upper layer of material at the early growth period of semi-conducting material, reduce upper strata dislocation density.
Meanwhile, the present invention utilizes MOCVD technology the selective epitaxy at initial stage and the epitaxial lateral overgrowth in later stage to be merged, and finally realizes complete smooth outer layer growth.Because the growth district selectivity of MOCVD technology is good, the adjustable extent of growth rate is large, is applicable to very much preparing high-quality low stress, the silica-based III-V group semi-conductor material of low-dislocation-density.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the basic procedure schematic diagram of the embodiment of the present invention silica-based iii-v gallium arsenide semiconductor material preparation method;
Fig. 2 is the nano-scale cycle graph template schematic diagram of the embodiment of the present invention silica-based iii-v gallium arsenide semiconductor material preparation method, and wherein: left figure is the template schematic diagram of one-dimensional barcode structure, right figure is the template schematic diagram of two-dimentional hole shape structure;
Fig. 3 is a preferred embodiment schematic flow sheet of the present invention's silica-based iii-v gallium arsenide semiconductor material preparation method;
Fig. 4 is the generalized section of embodiment of the present invention III-V group semi-conductor material structure,
In figure: 10: monocrystalline silicon <100>4 ° of drift angle substrate, 20: growth window district GaAs resilient coating, 21: silicon dioxide graph area; 30:III-V race semiconductor epitaxial layers;
Fig. 5 is the growth window district size of the nano-scale cycle graph of the embodiment of the present invention silica-based iii-v gallium arsenide semiconductor material preparation method and the functional relation schematic diagram of GaAs epitaxial loayer critical thickness;
Fig. 6 is in the embodiment of the present invention silica-based iii-v gallium arsenide semiconductor material preparation method, and the silicon dioxide figure of nano-scale stops the schematic diagram that the threading dislocation at GaAs/Si interface is upwards propagated;
Fig. 7 is the basic structure schematic diagram of the embodiment of the present invention silica-based iii-v gallium arsenide semiconductor material preparation system;
Fig. 8 is a preferred embodiment structural representation of the embodiment of the present invention silica-based iii-v gallium arsenide semiconductor material preparation system.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provide firstly a kind of silica-based iii-v gallium arsenide semiconductor material preparation method, and see Fig. 1, the method comprises:
Step 101: prepare silicon dioxide film on clean monocrystalline substrate surface.
Step 102: on described silicon dioxide film, nanometer embossing is adopted to obtain silica nanometer graph layer, described silica nanometer graph layer comprises the growth window district on exposed monocrystalline substrate surface, and silicon dioxide graph area, and growth window district and silicon dioxide graph area are interspersed.
Step 103: in described growth window district, deposition close to or equal the GaAs buffer layer of table surface height of described silicon dioxide graph area.
Step 104: in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material.
Visible, in the silica-based iii-v gallium arsenide semiconductor material preparation method that the embodiment of the present invention proposes, adopt the fabrication techniques silica nanometer graph layer of nano impression, be used as the graph substrate of semiconductor material growing, and continue epitaxial growth GaAs buffer layer and III-V group semi-conductor material on this basis.The graph substrate technology of preparing of this nano impression broken before scantling restricted problem, advantageously prepare in industrialized Material growth, significantly reduce material cost of manufacture, be with a wide range of applications.
In addition, for the situation that dimension of picture is less, several preparation method of the prior art not easily prepares high-quality graph substrate, and the nanometer embossing adopted in the embodiment of the present invention is easy to realize the high-quality graph substrate preparation of small size, depth-width ratio and the sidewall steepness of coining pattern can be changed as required, thus control the degree of depth and the sidewall profile of figure.The embodiment of the present invention can utilize the graph substrate of nano-scale to reduce the strain energy of material, thus greatly improve the critical thickness that material produces dislocation, simultaneously by the side direction dislocation barrier effect of silicon dioxide figure table top, stop that the threading dislocation of the overwhelming majority continues to propagate to upper layer of material at the early growth period of semi-conducting material, reduce upper strata dislocation density.
In the said method of the embodiment of the present invention, be attached with the pollutants such as grease, organic substance, metal impurities due to silicon chip surface, preferably, the conventional silicon chip Wet chemical cleaning method of industry can be utilized to process its surface to silicon chip; In addition, in order to prepare high-quality graph substrate in subsequent step, in an embodiment of the invention, preferably, can utilize plasma enhanced chemical vapor deposition method (PECVD) or thermal oxidation process, deposit thickness is the uniform silicon dioxide film of thickness of 400nm, and required thickness is even, surface-brightening is clean, and the quality of prepared silicon dioxide film can utilize atomic force microscope (AFM) to carry out surface topography to scan confirmation.In the selection of substrate, in order to eliminate the formation on reverse farmland on silica-based GaAs interface, <100> crystal face can be selected, the monocrystalline substrate of deflection <110> or <111> crystal face 4 ° ~ 6 °, in order to form diatomic step, suppress the generation on reverse farmland.Selected monocrystalline silicon buffing sheet can be Intrinsical or highly doped low-drag type, and thickness can be 330 ~ 370 μm.
In one embodiment of the invention, preferably, the method utilizing hot nano-imprinting method to obtain silica nanometer graph layer can be: utilize electron beam lithography to make the nano-imprint stamp with nano-scale cycle graph, nano-imprint lithography glue is spun on silicon oxide film surface, thickness is 200nm, toasts 2 minutes at 140 DEG C of temperature; Again template is placed in the silicon oxide film surface scribbling photoresist, temperature be 130 DEG C, pressure keeps 2 minutes under being 3MPa, then reduces pressure be cooled to 50 DEG C of demouldings; Then, adopt reactive ion etching method to remove the primer of dented part, complete the transfer of nano graph to photoresist; Afterwards, take photoresist as mask, adopt dry etching technology removal without the silicon dioxide film of masked areas, form growth window district, complete the transfer of nano graph to silicon dioxide film.The cycle graph of made nano-scale can be the one-dimensional barcode structure in cycle or two-dimentional hole shape structure, and periodic dimensions is 100 ~ 200nm, as shown in Figure 2; Wherein growth window district, also the area size that namely silicon dioxide film exposes monocrystalline substrate surface after being etched can be 50 ~ 100nm, dimension of picture and growth window district are interspersed, and size can carry out suitable adjustment and optimization according to the Material growth characteristic of the critical thickness of material and upper strata GaAs resilient coating.
For the growth course of GaAs resilient coating, in one embodiment of the invention, preferably, can in growth window district, MOCVD technology (MOCVD) is utilized to grow the GaAs material of involuntary doping: first substrate to be warmed up to 220 DEG C, to toast 30 minutes in atmosphere of hydrogen; Then be warmed up to 750 DEG C, toast 15 minutes at hydrogen and arsine mist atmosphere; Cool to 400 ~ 420 DEG C again, growth a layer thickness is the GaAs nucleating layer of 18nm, and source flux is: trimethyl gallium 2.7 × 10
-5mol/min, arsine 6.5 × 10
-3mol/min, input V/III are than 240; Be warmed up to 650 ~ 680 DEG C after 10 minutes, the GaAs buffer layer that growth 300 ~ 400nm is thick, source flux is: trimethyl gallium 4.0 × 10
-5mol/min, arsine 4.0 × 10
-3mol/min, input V/III are than 100; Finally, the in-situ heat cycle annealing between hydrogen and arsine mist atmosphere carry out 350 to 750 DEG C, cycle annealing number of times is three times.The height of the GaAs buffer layer grown should close to or equal the table surface height of silicon dioxide graph area.
In another embodiment of the present invention, in order to further reduce dislocation density gradually, improve the crystal mass of epitaxial loayer, complete material preparation, preferably, MOCVD technology can be utilized, in 420 ~ 750 DEG C of temperature ranges, GaAs buffer layer and silicon dioxide graph area continue epitaxial growth III-V group semi-conductor material, and growth thickness is 1000-2000nm, and chamber pressure is 50 ~ 100Torr.Wherein, when grown III-V group semi-conductor material is the GaAs of involuntary doping, epitaxially grown carrier gas can be high-purity hydrogen, and the organic source of III is trimethyl gallium, group V source is 99.999% high-purity arsine, and source flux is respectively: TMGa flow rate 4.0 × 10
-5mol/min, arsine flow 4.0 × 10
-3mol/min, input V/III ratio are 100.
Below with on the silica nanometer graph layer of strip structure cycle graph, continuing epitaxial growth GaAs material is example, describes the specific implementation process of a preferred embodiment of the invention in detail, as shown in Figure 3:
Step 301: utilize Wet chemical cleaning method to clean silicon chip.
Be attached with the pollutants such as grease, organic substance, metal impurities due to silicon chip surface, the silicon chip Wet chemical cleaning method that industry can be adopted conventional removes the various impurity of silicon chip surface.
Wherein, selected monocrystalline substrate is the Intrinsical silicon substrate in <100> crystal face deflection 4 °, <110> direction, and thickness is 370 μm.
Step 302: prepare silicon dioxide film.
In this step, have employed PECVD method and deposit the silicon dioxide film that a layer thickness is 400nm on a silicon surface, required thickness is even, and surface-brightening is clean, and utilizes AFM to carry out surface scan to the pattern of prepared silicon dioxide film.
Step 303: adopt hot nano-imprinting method to obtain silica nanometer graph layer.
In this step, have employed the method for hot nano impression to prepare the cycle graph of nano-scale: utilize electron beam lithography to make the nano-imprint stamp with nano-scale cycle graph, nano-imprint lithography glue is spun on silicon oxide film surface, thickness is 200nm, toasts 2 minutes at 140 DEG C of temperature; Again template is placed in the silicon oxide film surface scribbling photoresist, temperature be 130 DEG C, pressure keeps 2 minutes under being 3MPa, then reduces pressure be cooled to 50 DEG C of demouldings; Then, adopt reactive ion etching method to remove the primer of dented part, complete the transfer of nano graph to photoresist; Afterwards, take photoresist as mask, adopt dry etching technology removal without the silicon dioxide film of masked areas, form growth window district, complete the transfer of nano graph to silicon dioxide film.
The cycle graph of wherein made nano-scale is the one-dimensional barcode structure in cycle, and periodic dimensions is 200nm, wherein growth window district, and the area size that also namely silicon dioxide film exposes monocrystalline substrate surface after being etched is 50nm, as shown in Figure 4.Wherein the size in cycle graph and growth window district determines according to the Material growth characteristic of critical thickness and upper strata GaAs resilient coating, the functional relation of critical thickness and growth window district size is as Fig. 5, and this function curve is calculate notional result according to the strain energy of epitaxial film materials and the equilibrium condition model of misfit dislocation energy.Can be seen by critical thickness curve, when the size in growth window district is less than 100nm, the thickness of dislocation-free epitaxial loayer can reach about 100 μm, at this moment, graph substrate does not almost limit the thickness of epitaxial loayer, and we realize the theoretical foundation of low stress, the silica-based GaAs/Si Material growth of low-dislocation-density just.When the size in growth window district meets or exceeds 100 μm, the thickness of dislocation-free epitaxial loayer is reduced to rapidly and is thinner than 10nm, namely tradition is without the naked silicon chip growth GaAs material context of nanometer-scale pattern, obviously cannot realize significant silica-based GaAs/Si Material growth in this case.
Step 304: utilize MOCVD method growing low temperature GaAs nucleating layer in growth window district.
In this step, have employed MOCVD technology to prepare low temperature GaAs nucleating layer: first substrate is warmed up to 220 DEG C, toasts 30 minutes in atmosphere of hydrogen; Then be warmed up to 750 DEG C, toast 15 minutes at hydrogen and arsine mist atmosphere; Cool to 400 ~ 420 DEG C again, growth a layer thickness is the involuntary Doped GaAs material of 18nm, is GaAs nucleating layer.Wherein source flux is: trimethyl gallium 2.7 × 10
-5mol/min, arsine 6.5 × 10
-3mol/min, input V/III ratio are 240.
Step 305: utilize MOCVD method to grow high temperature GaAs resilient coating in growth window district.
To obtain after the nucleating layer of GaAs 10 minutes in step 304, substrate is warmed up to 650 ~ 680 DEG C, then grows the thick high temperature GaAs resilient coating of 300 ~ 400nm with MOCVD, wherein source flux is: trimethyl gallium 4.0 × 10
-5mol/min, arsine 4.0 × 10
-3mol/min, input V/III ratio are 100, and the material used is involuntary Doped GaAs.And require the height of GaAs buffer layer that grows close to or equal the table surface height of silicon dioxide graph area, be also namely less than 400nm.
Step 306: in-situ heat cycle annealing is carried out to resilient coating.
In this step, for the GaAs resilient coating of preparation in step 305, the in-situ heat cycle annealing between hydrogen and arsine mist atmosphere carry out 350 to 750 DEG C, cycle annealing number of times is three times.
Step 307: on resilient coating and silicon dioxide graph area, utilizes MOCVD method epitaxial growth GaAs material.
In this step, utilize MOCVD technology, at the GaAs material that 720 DEG C of growth 1500nm are thick, wherein epitaxially grown carrier gas is high-purity hydrogen, the organic source of III is trimethyl gallium, and group V source is 99.999% high-purity arsine, and source flux is respectively: TMGa flow rate 4.0 × 10
-5mol/min, arsine flow 4.0 × 10
-3mol/min, input V/III ratio are 100, and chamber pressure is 50 ~ 100Torr.The material profile graph structure finally obtained as shown in Figure 4.
The schematic diagram that the embodiment of the present invention utilizes the threading dislocation at the silicon dioxide figure of nano-scale stop GaAs/Si interface upwards to propagate is as Fig. 6, generally, the dislocation upwards propagated from GaAs/Si interface is mainly 60 ° of type dislocations along (111) crystal-plane slip, thus, these threading dislocations of bottom GaAs material can be stopped by silicon dioxide figure mesa structure, prevent dislocation continuation to the propagation of upper strata GaAs material, thus reduce dislocation density further.
So far, then complete in the embodiment of the present invention on the silica nanometer graph layer of strip structure cycle graph, continue the overall process of epitaxial growth GaAs material.
In addition, it should be noted that, above-mentioned all flow processs descriptions based on Fig. 3 are preferred implementation procedures of one of epitaxial growth GaAs MATERIALS METHODS of the present invention, in the actual realization of epitaxial growth GaAs MATERIALS METHODS of the present invention, random variation can be carried out as required on the basis of flow process shown in Fig. 1, can be select the arbitrary steps in Fig. 3 to realize, the sequencing of each step also can adjust as required.Such as, in a kind of actual realization, when step 303 pair silicon dioxide film etches, the hole shape structure of two-dimensional and periodic can be adopted as template.
Also proposed a kind of silica-based iii-v gallium arsenide semiconductor material preparation system in one embodiment of the present of invention, see Fig. 7, this system comprises:
Silicon dioxide prepares unit 701, for preparing silicon dioxide film on clean monocrystalline substrate surface;
Nano graph prepares unit 702, for at described silicon dioxide film, nanometer embossing is adopted to obtain silica nanometer graph layer, described silica nanometer graph layer comprises the growth window district on exposed monocrystalline substrate surface, and silicon dioxide graph area, growth window district and silicon dioxide graph area are interspersed;
Buffer layer deposition unit 703, in described growth window district, deposition close to or equal the GaAs buffer layer of table surface height of described silicon dioxide graph area;
Epitaxial growth unit 704, in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material.
In the said method of the embodiment of the present invention, the pollutants such as grease, organic substance, metal impurities are attached with due to silicon chip surface, preferably, system can also comprise: silicon chip processing unit 801, as shown in Figure 8, preparing unit 701 with silicon dioxide to be connected, for utilizing Wet chemical cleaning method, monocrystalline substrate being processed; In addition, in order to prepare high-quality graph substrate in subsequent step, in an embodiment of the invention, preferably, silicon dioxide is prepared unit 701 and can be comprised: chemical vapour deposition (CVD) subelement 802, for utilizing plasma enhanced chemical vapor deposition method, deposit thickness is the uniform silicon dioxide film of thickness of 400nm; Thermal oxidation subelement 803, for utilizing thermal oxidation process, forms the uniform silicon dioxide film of thickness that thickness is 400nm.
In one embodiment of the invention, preferably, nano graph is prepared unit 702 and can be comprised:
Template preparation subelement 804, for utilizing electron beam lithography to make the nano-imprint stamp with nano-scale cycle graph, nano-imprint lithography glue is spun on silicon oxide film surface, and thickness is 200nm, toasts 2 minutes at 140 DEG C of temperature.Prepared nano-scale cycle graph can be: the cycle graph of one-dimensional barcode structure or two-dimentional hole shape structure, and periodic dimensions is 100 ~ 200nm; Prepared growth window district size can be: 50 ~ 100nm.；
Demoulding subelement 805, for described template being placed in the silicon oxide film surface scribbling photoresist, temperature be 130 DEG C, pressure keeps 2 minutes under being 3MPa, then reduces pressure be cooled to 50 DEG C of demouldings;
Etching subelement 806, for the primer adopting reactive ion etching method to remove dented part, completes the transfer of nano graph to photoresist; Afterwards, take photoresist as mask, adopt dry etching technology removal without the silicon dioxide film of masked areas, form growth window district, complete the transfer of nano graph to silicon dioxide film.
In one embodiment of the invention, preferably, buffer layer deposition unit 703 can comprise:
Deposition anneal subelement 807, for utilizing the GaAs material of the involuntary doping of MOCVD technology growth: first substrate is warmed up to 220 DEG C, toasts 30 minutes in atmosphere of hydrogen; Then be warmed up to 750 DEG C, toast 15 minutes at hydrogen and arsine mist atmosphere; Cool to 400 ~ 420 DEG C again, growth a layer thickness is the GaAs nucleating layer of 18nm, and source flux is: trimethyl gallium 2.7 × 10
-5mol/min, arsine 6.5 × 10
-3mol/min, input V/III are than 240; Be warmed up to 650 ~ 680 DEG C after 10 minutes, the GaAs buffer layer that growth 300 ~ 400nm is thick, source flux is: trimethyl gallium 4.0 × 10
-5mol/min, arsine 4.0 × 10
-3mol/min, input V/III are than 100; Finally, the in-situ heat cycle annealing between hydrogen and arsine mist atmosphere carry out 350 to 750 DEG C, cycle annealing number of times is three times.
In another embodiment of the present invention, in order to further reduce dislocation density gradually, improve the crystal mass of epitaxial loayer, complete material preparation, preferably, epitaxial growth unit 704 can comprise: vapour phase epitaxy deposition subelement 808, for utilizing MOCVD technology, in 420 ~ 750 DEG C of temperature ranges, in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material, growth thickness is 1000-2000nm, and chamber pressure is 50 ~ 100Torr;
GaAs deposition subelement 809, for controlling the gallium arsenide epitaxial growth of involuntary doping, wherein epitaxially grown carrier gas is high-purity hydrogen, and the organic source of III is trimethyl gallium, group V source is 99.999% high-purity arsine, and source flux is respectively: TMGa flow rate 4.0 × 10
-5mol/min, arsine flow 4.0 × 10
-3mol/min, input V/III ratio are 100.
It should be noted that, the structure of each embodiment of the silica-based iii-v gallium arsenide semiconductor material preparation system shown in above-mentioned Fig. 8 can carry out combination in any use.Such as, do not comprise thermal oxidation subelement 803 in silica-based iii-v gallium arsenide semiconductor material preparation system, and comprise other all structures shown in Fig. 8.
Visible, the embodiment of the present invention has following beneficial effect:
In the silica-based iii-v gallium arsenide semiconductor material preparation method and system of embodiment of the present invention proposition, adopt the fabrication techniques silica nanometer graph layer of nano impression, be used as the graph substrate of semiconductor material growing, and continue epitaxial growth GaAs buffer layer and III-V group semi-conductor material on this basis.The graph substrate technology of preparing of this nano impression broken before scantling restricted problem, prepared substrate can reach 2 inches, compared to mm magnitude of the prior art, advantageously prepare in industrialized Material growth, significantly reduce material cost of manufacture, be with a wide range of applications.
In addition, for the situation that dimension of picture is less, several preparation method of the prior art not easily prepares high-quality graph substrate, and the nanometer embossing adopted in the embodiment of the present invention is easy to realize the high-quality graph substrate preparation of small size, depth-width ratio and the sidewall steepness of coining pattern can be changed as required, thus control the degree of depth and the sidewall profile of figure.The embodiment of the present invention can utilize the graph substrate of nano-scale to reduce the strain energy of material, thus greatly improve the critical thickness that material produces dislocation, simultaneously by the side direction dislocation barrier effect of silicon dioxide figure table top, stop that the threading dislocation of the overwhelming majority continues to propagate to upper layer of material at the early growth period of semi-conducting material, reduce upper strata dislocation density.
Meanwhile, the embodiment of the present invention utilizes MOCVD technology the selective epitaxy at initial stage and the epitaxial lateral overgrowth in later stage to be merged, and finally realizes complete smooth outer layer growth.Because the growth district selectivity of MOCVD technology is good, the adjustable extent of growth rate is large, is applicable to very much preparing high-quality low stress, the silica-based III-V group semi-conductor material of low-dislocation-density.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a silica-based iii-v gallium arsenide semiconductor material preparation method, is characterized in that, comprising:
Silicon dioxide film is prepared on clean monocrystalline substrate surface;
On described silicon dioxide film, nanometer embossing is adopted to obtain silica nanometer graph layer, described silica nanometer graph layer comprises the growth window district on exposed monocrystalline substrate surface, and silicon dioxide graph area, and growth window district and silicon dioxide graph area are interspersed;
In described growth window district, deposition close to or equal the GaAs buffer layer of table surface height of described silicon dioxide graph area;
In described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material.
2. silica-based iii-v gallium arsenide semiconductor material preparation method according to claim 1, is characterized in that:
Described before silicon dioxide film is prepared on clean monocrystalline substrate surface, also comprise: utilize Wet chemical cleaning method to process monocrystalline substrate;
And/or described silicon dioxide film of preparing comprises: utilize plasma enhanced chemical vapor deposition method or thermal oxidation process, deposit thickness is the uniform silicon dioxide film of thickness of 400nm;
And/or, described monocrystalline substrate is the highly doped low-drag type of intrinsic-OR, aufwuchsplate is <100>, crystal face deflection <110> or <111> crystal face 4 ° ~ 6 °, thickness is 330 ~ 370 μm.
3. silica-based iii-v gallium arsenide semiconductor material preparation method according to claim 1, is characterized in that:
Described employing nanometer embossing obtains silica nanometer graph layer and comprises: utilize electron beam lithography to make the nano-imprint stamp with nano-scale cycle graph, nano-imprint lithography glue is spun on silicon oxide film surface, thickness is 200nm, toasts 2 minutes at 140 DEG C of temperature; Again template is placed in the silicon oxide film surface scribbling photoresist, temperature be 130 DEG C, pressure keeps 2 minutes under being 3MPa, then reduces pressure be cooled to 50 DEG C of demouldings; Then, adopt reactive ion etching method to remove the primer of dented part, complete the transfer of nano graph to photoresist; Afterwards, take photoresist as mask, adopt dry etching technology removal without the silicon dioxide film of masked areas, form growth window district, complete the transfer of nano graph to silicon dioxide film;
Described nano-scale cycle graph is: the cycle graph of one-dimensional barcode structure or two-dimentional hole shape structure, and periodic dimensions is 100 ~ 200nm;
Described growth window district is of a size of: 50 ~ 100nm.
4. silica-based iii-v gallium arsenide semiconductor material preparation method according to claim 1, is characterized in that:
Describedly in described growth window district, deposit GaAs buffer layer comprise:
Utilize the GaAs material of the involuntary doping of MOCVD technology growth: first substrate is warmed up to 220 DEG C, toast 30 minutes in atmosphere of hydrogen; Then be warmed up to 750 DEG C, toast 15 minutes at hydrogen and arsine mist atmosphere; Cool to 400 ~ 420 DEG C again, growth a layer thickness is the GaAs nucleating layer of 18nm, and source flux is: trimethyl gallium 2.7 × 10
-5mol/min, arsine 6.5 × 10
-3mol/min, input V/III are than 240; Be warmed up to 650 ~ 680 DEG C after 10 minutes, the GaAs buffer layer that growth 300 ~ 400nm is thick, source flux is: trimethyl gallium 4.0 × 10
-5mol/min, arsine 4.0 × 10
-3mol/min, input V/III are than 100; Finally, the in-situ heat cycle annealing between hydrogen and arsine mist atmosphere carry out 350 to 750 DEG C, cycle annealing number of times is three times.
5. silica-based iii-v gallium arsenide semiconductor material preparation method according to any one of claim 1 to 4, is characterized in that:
Describedly to comprise at described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material: utilize MOCVD technology, in 420 ~ 750 DEG C of temperature ranges, in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material, growth thickness is 1000-2000nm, and chamber pressure is 50 ~ 100Torr;
When described III-V group semi-conductor material is the GaAs of involuntary doping, epitaxially grown carrier gas is high-purity hydrogen, and the organic source of III is trimethyl gallium, and group V source is 99.999% high-purity arsine, and source flux is respectively: TMGa flow rate 4.0 × 10
-5mol/min, arsine flow 4.0 × 10
-3mol/min, input V/III ratio are 100.
6. a silica-based iii-v gallium arsenide semiconductor material preparation system, is characterized in that, comprising: silicon dioxide prepares unit, nano graph prepares unit, buffer layer deposition unit and epitaxial growth unit, and each sequence of unit is connected, wherein:
Silicon dioxide prepares unit, for preparing silicon dioxide film on clean monocrystalline substrate surface;
Nano graph prepares unit, for at described silicon dioxide film, nanometer embossing is adopted to obtain silica nanometer graph layer, described silica nanometer graph layer comprises the growth window district on exposed monocrystalline substrate surface, and silicon dioxide graph area, growth window district and silicon dioxide graph area are interspersed;
Buffer layer deposition unit, in described growth window district, deposition close to or equal the GaAs buffer layer of table surface height of described silicon dioxide graph area;
Epitaxial growth unit, in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material.
7. silica-based iii-v gallium arsenide semiconductor material preparation system according to claim 6, is characterized in that:
Described system also comprises: silicon chip processing unit, prepares unit be connected with described silicon dioxide, processes monocrystalline substrate for utilizing Wet chemical cleaning method;
And/or,
Described silicon dioxide is prepared unit and is comprised:
Chemical vapour deposition (CVD) subelement, for utilizing plasma enhanced chemical vapor deposition method, deposit thickness is the uniform silicon dioxide film of thickness of 400nm;
Or thermal oxidation subelement, for utilizing thermal oxidation process, forms the uniform silicon dioxide film of thickness that thickness is 400nm.
8. silica-based iii-v gallium arsenide semiconductor material preparation system according to claim 6, is characterized in that:
Described nano graph is prepared unit and is comprised:
Template preparation subelement, for utilizing electron beam lithography to make the nano-imprint stamp with nano-scale cycle graph, nano-imprint lithography glue is spun on silicon oxide film surface, and thickness is 200nm, toasts 2 minutes at 140 DEG C of temperature;
Demoulding subelement, for described template being placed in the silicon oxide film surface scribbling photoresist, temperature be 130 DEG C, pressure keeps 2 minutes under being 3MPa, then reduces pressure be cooled to 50 DEG C of demouldings;
Etching subelement, for the primer adopting reactive ion etching method to remove dented part, completes the transfer of nano graph to photoresist; Afterwards, take photoresist as mask, adopt dry etching technology removal without the silicon dioxide film of masked areas, form growth window district, complete the transfer of nano graph to silicon dioxide film;
Nano-scale cycle graph prepared by described Template preparation subelement is: the cycle graph of one-dimensional barcode structure or two-dimentional hole shape structure, and periodic dimensions is 100 ~ 200nm; Prepared growth window district is of a size of: 50 ~ 100nm.
9. silica-based iii-v gallium arsenide semiconductor material preparation system according to claim 6, it is characterized in that, described buffer layer deposition unit comprises:
Deposition anneal subelement, for utilizing the GaAs material of the involuntary doping of MOCVD technology growth: first substrate is warmed up to 220 DEG C, toasts 30 minutes in atmosphere of hydrogen; Then be warmed up to 750 DEG C, toast 15 minutes at hydrogen and arsine mist atmosphere; Cool to 400 ~ 420 DEG C again, growth a layer thickness is the GaAs nucleating layer of 18nm, and source flux is: trimethyl gallium 2.7 × 10
-5mol/min, arsine 6.5 × 10
-3mol/min, input V/III are than 240; Be warmed up to 650 ~ 680 DEG C after 10 minutes, the GaAs buffer layer that growth 300 ~ 400nm is thick, source flux is: trimethyl gallium 4.0 × 10
-5mol/min, arsine 4.0 × 10
-3mol/min, input V/III are than 100; Finally, the in-situ heat cycle annealing between hydrogen and arsine mist atmosphere carry out 350 to 750 DEG C, cycle annealing number of times is three times.
10. the silica-based iii-v gallium arsenide semiconductor material preparation system according to any one of claim 6 to 9, is characterized in that:
Described epitaxial growth unit comprises: vapour phase epitaxy deposition subelement, for utilizing MOCVD technology, in 420 ~ 750 DEG C of temperature ranges, in described GaAs buffer layer and described silicon dioxide graph area Epitaxial growth III-V group semi-conductor material, growth thickness is 1000-2000nm, and chamber pressure is 50 ~ 100Torr;
And/or GaAs deposition subelement, for controlling the gallium arsenide epitaxial growth of involuntary doping, wherein epitaxially grown carrier gas is high-purity hydrogen, the organic source of III is trimethyl gallium, and group V source is 99.999% high-purity arsine, and source flux is respectively: TMGa flow rate 4.0 × 10
-5mol/min, arsine flow 4.0 × 10
-3mol/min, input V/III ratio are 100.
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