CN104572506B - A kind of method and device concurrently accessing memory - Google Patents

A kind of method and device concurrently accessing memory Download PDF

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Publication number
CN104572506B
CN104572506B CN201310492402.3A CN201310492402A CN104572506B CN 104572506 B CN104572506 B CN 104572506B CN 201310492402 A CN201310492402 A CN 201310492402A CN 104572506 B CN104572506 B CN 104572506B
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affairs
read
conflict
processor
write
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CN104572506A (en
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马凌
姚四海
张磊
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Alibaba Group Holding Ltd
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Alibaba Group Holding Ltd
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Priority to CN201310492402.3A priority Critical patent/CN104572506B/en
Priority to TW103118605A priority patent/TW201516688A/en
Priority to EP14793944.1A priority patent/EP3058461A1/en
Priority to PCT/US2014/060901 priority patent/WO2015057962A1/en
Priority to SG11201602639TA priority patent/SG11201602639TA/en
Priority to JP2016520133A priority patent/JP2016537708A/en
Priority to US14/515,952 priority patent/US20150113244A1/en
Priority to KR1020167009643A priority patent/KR20160086820A/en
Publication of CN104572506A publication Critical patent/CN104572506A/en
Priority to HK15106256.9A priority patent/HK1205806A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G06F9/528—Mutual exclusion algorithms by using speculative mechanisms

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  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

This application discloses a kind of method and devices for concurrently accessing memory；The described method includes: when the first affairs need to carry out write operation to the first data, if there is reading first data or the second affairs of first data will be read, then the record of the read operation conflict of the write operation and second affairs that indicate first affairs is generated；The processing of second affairs is executed, second affairs are submitted after the completion of executing and first affairs are notified according to the record；The processing of first affairs is executed, submits first affairs after executing the notice for completing and receiving second affairs.The application can be improved the concurrency that transaction internal memory accesses in multiple nucleus system, while reduce the rollback that conflict causes, and improve systematic entirety energy.

Description

A kind of method and device concurrently accessing memory
Technical field
The present invention relates to computer fields, more particularly to a kind of method and device for concurrently accessing memory.
Background technique
Recent years, processor manufacturer are limited by power consumption and temperature, while in order to keep high performance computation to continue Increase, computer develops towards multi-core computer architectural framework direction.In order to make full use of multicore architecture, application program quilt Split into it is multiple can thread of the independent operating on single cpu, in this way design program can execute raising overall operation parallel Efficiency.It based on such procedure system, needs to guarantee the synchronism and data integrity of data processing, therefore is needed between thread With certain synchronization mechanism come serial access shared region.
Transaction memory(transaction internal memory) proposition precisely in order to improve thread degree of parallelism； Transaction memory assumes seldom to generate write-read for the access of shared data between multicore thread, read-write, and - write conflict, therefore the parallel execution for allowing multiple threads exploratory are write, rollback is carried out when discovery generates conflict, makes journey The state of sequence returns to the state before conflict, utilizes the property of this characteristic architecture under the premise of not influencing data integrity It can be improved with scalability.
Transaction memory is widely used in the scalability that architectural framework is improved in parallel system.Currently Transaction memory technology has come among CPU architectural framework, the Blue Gene/Q including IBM, Intel's Haswell。
Although Transaction memory improves the degree of parallelism of thread, as the raising conflict of degree of parallelism generates Probability be consequently increased, once generate conflict carry out rolling back action will it is serious injury program performance.
Summary of the invention
The application technical problems to be solved are how to improve the concurrency that transaction internal memory accesses in multiple nucleus system, are subtracted simultaneously The prominent rollback caused of Shaochong, improves systematic entirety energy.
To solve the above-mentioned problems, this application provides a kind of methods for concurrently accessing memory, comprising:
When the first affairs need to carry out write operation to the first data, if there is reading first data or will read Second affairs of first data then generate the read operation punching of the write operation and second affairs that indicate first affairs Prominent record；
The processing of second affairs is executed, second affairs are submitted after the completion of executing and institute is notified according to the record State the first affairs；
The processing of first affairs is executed, submits described first after executing the notice for completing and receiving second affairs Affairs.
Optionally, the note of the read operation conflict for generating the write operation and second affairs that indicate first affairs The step of record includes:
In the first read/write conflict detected register of first processor for running first affairs, described the will be run Operation conflict mark position is to indicate to generate write operation punching by the corresponding processor flag set of the second processor of two affairs Prominent value；
In the second read/write conflict detected register of the second processor, by the corresponding processing of the first processor Device marker set, will operate conflict mark position is the value for indicating to generate read operation conflict.
Optionally, according to it is described record notify first affairs the step of include:
In the second read/write conflict detected register, the processor flag of set is searched；
Determine that the processor flag of set corresponds to the first processor；
Notify first affairs run on the first processor.
Optionally, the processing of first affairs is executed, is submitted after executing the notice for completing and receiving second affairs The step of first affairs includes:
Step 41, the processing for executing first affairs carry out step 42 after the completion of executing；
Step 42 judges whether the operation conflict mark position in the first read/write conflict detected register is to indicate to generate The value of write operation conflict if it is carries out step 43, then carries out step 45 if it is the value for indicating read operation conflict；
Step 43 judges the whether complete non-set of each processor flag in the first read/write conflict detected register；Such as Fruit at least one set then waits；Step 45 is carried out if complete non-set；
Step 44, after receiving the notice of second affairs, in the first read/write conflict detected register, by institute The corresponding processor flag of second processor is stated to reset；Return step 43；
Step 45 submits first affairs.
Optionally, it judges whether there is and read first data or the step of the second affairs that first data will be read After rapid further include:
It, will be described before the processing for executing first affairs if second affairs read first data First data corresponding cache lines in second affairs copy in the corresponding privately owned invisible caching of first affairs；
If second affairs will read first data, before the processing for executing second affairs, from institute It states in the corresponding cache lines of the first affairs, it is corresponding that first data for not carrying out write operation are copied to second affairs In caching.
Present invention also provides a kind of devices for concurrently accessing memory, comprising:
Memory management unit, for when the first affairs need to the first data carry out write operation when, if there is reading It states the first data or the second affairs of first data will be read, then generate the write operation for indicating first affairs and described The record of the read operation conflict of second affairs；
First processing units execute for executing the processing of first affairs and complete and receive second affairs First affairs are submitted after notice；
The second processing unit submits second affairs simultaneously after the completion of executing for executing the processing of second affairs First affairs are notified according to the record.
Optionally, the device further include:
The first read/write conflict detected register corresponding with the first processing units；
The second read/write conflict detected register corresponding with described the second processing unit；
The memory management unit generates the read operation punching of the write operation and second affairs that indicate first affairs Prominent record refers to:
The memory management unit is corresponding by described the second processing unit in the first read/write conflict detected register Processor flag set, by operate conflict mark position be indicate generation write operation conflict value；In second read-write In collision detection register, by the corresponding processor flag set of the first processing units, conflict mark position will be operated To indicate to generate the value of read operation conflict.
Optionally, described the second processing unit notifies first affairs to refer to according to the record:
Described the second processing unit searches the processor flag of set in the second read/write conflict detected register Position；Determine that the processor flag of set corresponds to the first processing units；It notifies to run in the first processing units First affairs.
Optionally, the first processing units include:
First judgment module, the second judgment module；
Execution module, for executing the processing of first affairs, indicated after the completion of executing the first judgment module into Row judgement；
Module is removed, for after receiving the notice of second affairs, in the first read/write conflict detected register In, the corresponding processor flag of described the second processing unit is resetted；Indicate that second judgment module is judged；
The first judgment module is used to judge the operation conflict mark position in the first read/write conflict detected register It whether is the value for indicating to generate write conflict；If it is indicate that the first judgment module is judged；Behaviour is read if it is expression The value for making to conflict then indicates that the submission module submits first affairs；
Second judgment module is for judging that each processor flag is in the first read/write conflict detected register No complete non-set；Indicate that the submission module submits first affairs if complete non-set.
Optionally, the memory management unit is also used to when judging that second affairs read first data, It is before the first processing units execute the processing of first affairs, first data are corresponding in second affairs Cache lines copy in the corresponding privately owned invisible caching of first affairs；When judging that second affairs will read described When one data, before the processing that described the second processing unit executes second affairs, from the corresponding caching of first affairs In row, first data for not carrying out write operation are copied in the corresponding caching of second affairs.
The application can permit under the premise of a thread writes data, other multicores still can read identical parallel Data, under the premise of maintaining data integrity, improve the concurrency of multicore read operation and avoid memory due to read-write conflict and The rollback time that write-read conflict generates, the final concurrency and handling capacity for improving system, so that overall operation performance is improved, and The scalability of multiple nucleus system can be improved.Transactional conflict register is increased in another embodiment of the application, it can be effective Object, the type of conflict are recorded, and can guarantee the submission sequence of each affairs by the transactional conflict register.Certainly, implement this Any product of application must be not necessarily required to reach all the above advantage simultaneously.
Detailed description of the invention
Fig. 1 is the flow diagram of the method for concurrently accessing memory of embodiment one；
Fig. 2 is the schematic diagram of read/write conflict detected register in embodiment one；
Fig. 3 is the flow diagram of step S103 in embodiment one；
Fig. 4 is the flow diagram of first example of embodiment one；
Fig. 5 is the flow diagram of second example of embodiment one.
Specific embodiment
It is described in detail below in conjunction with technical solution of the accompanying drawings and embodiments to the application.
It should be noted that each feature in the embodiment of the present application and embodiment can be tied mutually if do not conflicted It closes, within the scope of protection of this application.In addition, though logical order is shown in flow charts, but in certain situations Under, it can be with the steps shown or described are performed in an order that is different from the one herein.
In a typical configuration, multiple nucleus system may include multiple processors (CPU), one or more input/output Interface, network interface and memory.
Memory may include the non-volatile memory in computer-readable medium, random access memory (RAM) and/or The forms such as Nonvolatile memory, such as read-only memory (ROM) or flash memory (flash RAM).Memory is computer-readable medium Example.
Computer-readable medium includes permanent and non-permanent, removable and non-removable media can be by any method Or technology come realize information store.Information can be computer readable instructions, data structure, the module of program or other data. The example of the storage medium of computer includes, but are not limited to phase change memory (PRAM), static random access memory (SRAM), moves State random access memory (DRAM), other kinds of random access memory (RAM), read-only memory (ROM), electric erasable Programmable read only memory (EEPROM), flash memory or other memory techniques, read-only disc read only memory (CD-ROM) (CD-ROM), Digital versatile disc (DVD) or other optical storage, magnetic cassettes, tape magnetic disk storage or other magnetic storage devices Or any other non-transmission medium, can be used for storage can be accessed by a computing device information.As defined in this article, it calculates Machine readable medium does not include non-temporary computer readable media (transitory media), such as the data-signal and carrier wave of modulation.
By development in nearly more than 20 years, Transaction memory can be soft respectively by software or hardware realization The Transaction memory execution efficiency that part is realized is very low, and hard-wired Transaction memory is mentioned significantly High the practicality, therefore the Transaction memory being discussed herein primarily on hardware foundation.
The working principle of hardware Transaction memory is introduced first.
Transaction memory tells the CPU beginning and end of Transaction region of memory with code, such as Transaction_start and Transaction_end.Middle section is the execution region Transaction, once executing terminates The data that Transaction_end instruction requires CPU to cross all modifications are submitted in an atomic manner (namely submits process can not It is interrupted and accesses).
Any region of memory read or write can be all monitored in order to avoid producing during executing Transaction Raw write-read, read-write, and write-write conflict.For example, every cache line(cache lines) all mark is write there are two bit( Position write-bit and reading marker read-bit) it respectively indicates and write and read；Such as the first affairs Transaction0It reads Data A is set as " 1 " then by the read-bit set of the corresponding cache lines of data A to indicate to read (to read to refer to Transaction is read0In corresponding caching but not yet submit Transaction0, by the read-bit if having submitted It resets, that is, is set as " 0 ")；If Transaction later0Write data A again, then it can be first by the number of the corresponding cache lines of data A It is updated operation according to privately owned sightless buffer zone (such as first layer caching) is copied to, while former data A is corresponding The write-bit of cache lines is set as " 1 ", and read-bit is set as " 0 ".
If first thread P0Pass through first processor CPU0Into the first affairs Transaction0Region write (or Read) data of a cache lines (64 bytes), then the label for writing (or reading) corresponding in this cache lines will be arranged bit；And the second other thread P1 passes through first processor CPU1Enter the first affairs Transaction0Or other affairs Region, prepare to read (either writing) to be written (or reading) identical cache lines just now, then such action event will be by First processor CPU0The result for being captured, therefore being generated is first thread P0Or the second thread P1Rollback is carried out, in addition write- The rollback phenomenon that write conflict will also generate hinders cpu performance, especially in read-write shared drive (one or more cache lines) operation frequency In the case where numerous, i.e., cannot reach parallel work-flow will also generate redundancy rollback therefore will seriously hinder performance
The state originated into the region Transaction is rolled back to when in order to enable data collision, currently Transaction memory operation is a to must all replicate original data before all memory write operations；Such as it can be with Duplication needs to carry out a cache lines of write operation into privately owned sightless caching (such as in first layer caching), in write operation It is that write-in update is carried out to cache lines corresponding in privately owned sightless caching；In this way once generate conflict if will abandon it is privately owned not Updated data (as unit of cache lines) among visible caching (such as first layer caching), program is from Transaction Entrance is reruned, if successfully completed Transaction, then in privately owned sightless caching (such as first layer caching) The data being newly written replace original data.
Embodiment one, a kind of method for concurrently accessing memory, comprising:
S101, when the first affairs need to the first data carry out write operation when, if there is read first data or The second affairs that will read first data then generate the reading of the write operation and second affairs that indicate first affairs Operate the record of conflict；
S102, the processing for executing second affairs submit second affairs and according to the record after the completion of executing Notify first affairs；
S103, the processing for executing first affairs submit institute after executing the notice for completing and receiving second affairs State the first affairs.
Wherein, the step of executing the processing of first, second affairs can in no particular order and can be parallel.Here " reading Cross " refer to and read to refer to and read in the corresponding caching of the second affairs but not yet submitted.
The submission process in conflict is devised in the present embodiment and guarantees the measure that the submission process is realized, can guarantee thing Business is submitted according to the sequence that reading and writing operate, and avoids rushing in read-write conflict (data of Yao Jinhang write operation were read) and write-read Prominent (data of Yao Jinhang write operation will be read) carries out rollback when occurring, therefore improves read operation concurrency and reduce back The generation of rolling can improve the overall performance of multiple systems.
In an embodiment of the present embodiment, a read/write conflict can be increased for each processor in multiple nucleus system Detected register (is hereinafter T-CCR), format is as shown in Fig. 2, including the corresponding processor of processor each in multiple nucleus system Marker C0, C1 ... Cn, and being used to indicate currently running Transaction on present processor is to generate read operation conflict also It is the operation conflict mark position Reader/Writer of write operation conflict, does not allow reading and writing to operate in a Transaction Conflict while occurring, if occurring to need to carry out rollback simultaneously.
In present embodiment, the read operation punching for generating the write operation and second affairs that indicate first affairs The step of prominent record, can specifically include:
In the first read/write conflict detected register of first processor for running first affairs, described the will be run Operation conflict mark position is to indicate to generate write operation punching by the corresponding processor flag set of the second processor of two affairs Prominent value；
In the second read/write conflict detected register of the second processor, by the corresponding processing of the first processor Device marker set, will operate conflict mark position is the value for indicating to generate read operation conflict.
Correspondingly, according to it is described record notify first affairs the step of include:
In the second read/write conflict detected register, the processor flag of set is searched；
Determine that the processor flag of set corresponds to the first processor；
Notify first affairs run on the first processor.
For example, (assuming that first processor CPU when for example generating read-write conflict0The Transaction of upper operation0It wants The cache lines and second processor CPU write1The Transaction of upper operation1The cache lines conflict read), then first processor CPU0T-CCR0In, second processor CPU1Corresponding processor flag C1 will set, while Reader/Writer quilt It is set to " 1 ", indicates first processor CPU0Upper currently running Transaction0It is to generate write operation conflict；And second processing Device CPU1Corresponding T-CCR1In, first processor CPU0Corresponding processor flag C0 will set, while Reader/ Writer is set to " 0 ", indicates second processor CPU1Upper currently running Transaction1It is to generate read operation conflict.Table Show that the value of read/write operation conflict also can be interchanged.
(T-CCR of the second processor of second affairs is run as the second affairs for carrying out read operation1Middle Reader/ Writer is " 0 ", and the corresponding processor flag of other processors is not all set in C0~Cn), even if due to certain A little situations generate rollback, also will be according to the T-CCR of the second processor1In corresponding conflict position (be i.e. set in C0~Cn The processor flag corresponding to other processors, be exactly C0 in this example), accordingly remove processor corresponding to the conflict position T-CCR in, the corresponding processor flag of second processor (in this example be T-CCR0In processor flag C1).
In present embodiment, as shown in figure 3, step S103 can specifically include:
S301, the processing for executing first affairs carry out step S302 after the completion of executing；
S302, judge whether the operation conflict mark position in the first read/write conflict detected register is to indicate to generate to write The value of conflict is operated, step S303 is if it is carried out, then carries out step S305 if it is the value for indicating read operation conflict；
S303, judge the whether complete non-set of each processor flag in the first read/write conflict detected register；If Set then waits at least one；Step S305 is carried out if complete non-set；
S304, after receiving the notice of second affairs, will be described in the first read/write conflict detected register The corresponding processor flag of second processor resets；Return step S303；
S305, first affairs are submitted.
Second affairs can have an one or more, for example to read first data/to read described there are two affairs First data；Or an affairs read first data, another affairs will read first data；It at this moment only need to be by first Corresponding processor flag set in read/write conflict detected register, Reader/Writer are still set to indicate to write Operate the value of conflict.(the first read/write conflict detected register after all being submitted Deng these affairs for reading/reading first data In processor flag all reset after), submit first affairs.
In an embodiment of the present embodiment, judges whether there is and read first data or will read described first Can also include: after the step of second affairs of data
It, will be described before the processing for executing first affairs if second affairs read first data First data corresponding cache lines in second affairs copy in the corresponding privately owned invisible caching of first affairs；
If second affairs will read first data, before the processing for executing second affairs, from institute It states in the corresponding cache lines of the first affairs, it is corresponding that first data for not carrying out write operation are copied to second affairs In caching.
Transaction is replicated before writing to be utilized in the present embodiment this to carry out data recovery when rollback The characteristics of duplication, reads copied content parallel before writing, and improves whole degree of parallelism while reducing conflict and improves performance.
The present embodiment is illustrated with two examples below:
First example is to postpone submitting reducing read-write conflict (data to be write were read by other affairs), such as Fig. 4 institute Show, including step S401~407.
S401, the first affairs Transaction0Pass through first processor CPU0It brings into operation, by first processor CPU0's T-CCR0It empties, data A is write in preparation.
S402, whether (that is: the corresponding cache lines of data A by other Transaction were read by inquiry detection data A Read bit whether set), step S404 is jumped to if not reading；Step S403 is carried out if reading.
S403, assume data A by the second affairs Transaction1Read (the read bit of the corresponding cache lines of data A It is set), then to T-CCR0、T-CCR1It is configured, comprising: the second affairs Transaction will be run1Second processing Device CPU1T-CCR1In, correspond to the first processor CPU0Processor flag C0 be set to " 1 ", by operation mark position Reader/Writer is set to the value " 0 " for indicating read operation conflict.It replicates this cache lines and is put into the first affairs Transaction0 It is updated in corresponding privately owned invisible caching, by the first affairs Transaction0T-CCR0In correspond to described second Processor CPU1Processor flag C1 be set to 1, operation mark position Reader/Writer, which is set to, indicates write operation conflict It is worth " 1 ".
S404, the first affairs Transaction0Executive Office's reason is until terminating.
S405, judge whether to need to wait other affairs to submit, comprising:
Judge the first affairs Transaction0T-CCR0In the whether non-set of processor flag (C1~Cn), Illustrate to without waiting for if non-set, can normally submit, carries out step S407.
If there is at least one set (not for " 0) and T-CCR0Middle Reder/Writer is that " 1 " then illustrates the second affairs Transaction1Just use data A, it is therefore desirable to wait the second affairs Transaction1It submits；Carry out step S406.
S406, the second affairs Transaction1T-CCR is notified when submission1Middle numerical value is that the processor flag of " 1 " is corresponding Processor on run affairs (in this example i.e.: processor flag C0 be " 1 " then notify the first affairs Transaction0)；According to the second affairs Transaction1Notice when submission removes T-CCR0In correspond to second processing The processor flag C1 of device, jumps to step S405.
Step S406 is it can also happen that in the first affairs Transaction0Before executing processing completion, such first affairs Transaction0Just can directly it submit without waiting.
S407, the first affairs Transaction is submitted0。
Second example is to postpone submitting reducing write-read conflict (data to be write will be read by other affairs), such as Fig. 5 institute Show, including step S501~507.
S501, the first affairs Transaction0Pass through first processor CPU0It brings into operation, by first processor CPU0's T-CCR0It empties, data A is write in preparation.
S502, it other Transaction is judged whether there is needs to read data A, step S504 is jumped to if not, if There is the second affairs Transaction1It needs to read data A and then carries out step S503.
S503, by T-CCR0In correspond to the second processor CPU1Processor flag C1 be set to " 1 ", simultaneously will Reader/Writer is set to " 1 ", and duplication original data A(does not carry out the data A of write operation) in the first affairs Transaction0 In corresponding cache lines to the second affairs Transaction1Caching in (be also possible in privately owned caching), by T-CCR1In it is right Second processor CPU described in Ying Yu1Processor flag C0 be set to " 1 ", Reader/Writer is set to " 0 ".
S504, the first affairs Transaction0Executive Office's reason is until terminating.
S405, judge whether to need to wait other affairs to submit, comprising:
Judge the first affairs Transaction0T-CCR0In the whether non-set of processor flag (C1~Cn), Illustrate to without waiting for if non-set, can normally submit, carries out step S407.
If there is at least one set (not for " 0) and T-CCR0Middle Reder/Writer is that " 1 " then illustrates the second affairs Transaction1Just use data A, it is therefore desirable to wait the second affairs Transaction1It submits；Carry out step S506.
S506, the second affairs Transaction1T-CCR is notified when submission1Middle numerical value is that the processor flag of " 1 " is corresponding Processor on run affairs (in this example i.e.: processor flag C0 be " 1 " then notify the first affairs Transaction0)；According to the second affairs Transaction1Notice when submission removes T-CCR0In correspond to second processing The processor flag C1 of device, jumps to step S505.
Step S506 is it can also happen that in the first affairs Transaction0Before executing processing completion, such first affairs Transaction0Just can directly it submit without waiting.
S507, the first affairs Transaction is submitted0。
In the present embodiment, if the first affairs Transaction0Need to read the data that other Transaction write, Due to T-CCR0Middle Reder/Writer is " 1 ", indicates the first affairs Transaction0Write operation with other affairs Read operation conflict, then Transaction0Or the necessary rollback of the other Transaction, in order to avoid generation deadlock (such as Other Transaction is the second affairs Transaction1When, the affairs due to writing data will wait the thing for reading data Business is first submitted, then the first affairs, the second affairs will require that other side is waited to submit, and causes all submit).It will when rollback Processor flag bit clear in corresponding T-CCR.
Embodiment two, a kind of device for concurrently accessing memory, comprising:
Memory management unit, for when the first affairs need to the first data carry out write operation when, if there is reading It states the first data or the second affairs of first data will be read, then generate the write operation for indicating first affairs and described The record of the read operation conflict of second affairs；
First processing units execute for executing the processing of first affairs and complete and receive second affairs The submission of first affairs is carried out after notice；
The second processing unit carries out second affairs for executing the processing of second affairs after the completion of executing It submits and first affairs is notified according to the record.
In an embodiment of the present embodiment, described device can also include:
The first read/write conflict detected register corresponding with the first processing units；
The second read/write conflict detected register corresponding with described the second processing unit；
The memory management unit generates the read operation punching of the write operation and second affairs that indicate first affairs Prominent record can specifically refer to:
The memory management unit is corresponding by described the second processing unit in the first read/write conflict detected register Processor flag set, by operate conflict mark position be indicate generation write operation conflict value；In second read-write In collision detection register, by the corresponding processor flag set of the first processing units, conflict mark position will be operated To indicate to generate the value of read operation conflict.
In present embodiment, described the second processing unit notifies first affairs specifically to can be according to the record Refer to:
Described the second processing unit searches the processor flag of set in the second read/write conflict detected register Position；Determine that the processor flag of set corresponds to the first processing units；It notifies to run in the first processing units First affairs.
In present embodiment, the first processing units be can specifically include:
First judgment module, the second judgment module；
Execution module, for executing the processing of first affairs, indicated after the completion of executing the first judgment module into Row judgement；
Module is removed, for after receiving the notice of second affairs, in the first read/write conflict detected register In, the corresponding processor flag of described the second processing unit is resetted；Indicate that second judgment module is judged；
The first judgment module is used to judge the operation conflict mark position in the first read/write conflict detected register It whether is the value for indicating to generate write conflict；If it is indicate that the first judgment module is judged；Behaviour is read if it is expression The value for making to conflict then indicates that the submission module carries out the submission of first affairs；
Second judgment module is for judging that each processor flag is in the first read/write conflict detected register No complete non-set；Indicate that the submission module carries out the submission of first affairs if complete non-set.
In an embodiment of the present embodiment, the memory management unit, which can be also used for working as, judges second affairs When reading first data, before the processing that the first processing units execute first affairs, by first data Corresponding cache lines copy in the corresponding privately owned invisible caching of first affairs in second affairs；When judging When first data will be read by stating the second affairs, before the processing that described the second processing unit executes second affairs, from In the corresponding cache lines of first affairs, it is corresponding that first data for not carrying out write operation are copied into second affairs Caching in.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program Related hardware is completed, and described program can store in computer readable storage medium, such as read-only memory, disk or CD Deng.Optionally, one or more integrated circuits can be used also to realize in all or part of the steps of above-described embodiment.Accordingly Ground, each module/unit in above-described embodiment can take the form of hardware realization, can also use the shape of software function module Formula is realized.The application is not limited to the combination of the hardware and software of any particular form.
Certainly, the application can also have other various embodiments, ripe without departing substantially from the application spirit and its essence Various corresponding changes and modifications, but these corresponding changes and change ought can be made according to the application by knowing those skilled in the art Shape all should belong to the protection scope of claims hereof.

Claims (10)

1. a kind of method for concurrently accessing transaction internal memory, comprising:
Memory management unit is when the first affairs need to carry out write operation to the first data, if there is reading first data Or the second affairs of first data will be read, then generate the write operation and second affairs for indicating first affairs The record of read operation conflict；
Second processor executes the processing of second affairs, submits second affairs and according to the record after the completion of executing Notify first affairs；
First processor executes the processing of first affairs, after executing the notice completed and received when second affairs are submitted Submit first affairs.
2. the method as described in claim 1, which is characterized in that the write operation for indicating first affairs and described of generating The step of record of the read operation conflict of second affairs includes:
Memory management unit will be transported in the first read/write conflict detected register of first processor for running first affairs Operation conflict mark position is to indicate to generate by the corresponding processor flag set of second processor of row second affairs The value of write operation conflict；
Memory management unit is in the second read/write conflict detected register of the second processor, by the first processor pair The processor flag set answered, will operate conflict mark position is the value for indicating to generate read operation conflict.
3. method according to claim 2, which is characterized in that the step of notifying first affairs according to record packet It includes:
Second processor searches the processor flag of set in the second read/write conflict detected register；
Determine that the processor flag of set corresponds to the first processor；
Notify first affairs run on the first processor.
4. method according to claim 2, which is characterized in that first processor executes the processing of first affairs, executes Complete and receive the step of submitting first affairs after the notices of second affairs include:
Step 41, first processor execute the processing of first affairs, carry out step 42 after the completion of executing；
Whether step 42, the first processor judge the operation conflict mark position in the first read/write conflict detected register To indicate to generate the value of write operation conflict, step 43 is if it is carried out, is then walked if it is the value for indicating read operation conflict Rapid 45；
Step 43, the first processor judge whether each processor flag is complete in the first read/write conflict detected register Non- set；It is waited if at least one set；Step 45 is carried out if complete non-set；
Step 44, the first processor are posted after receiving the notice of second affairs in first read/write conflict detection In storage, the corresponding processor flag of the second processor is resetted；Return step 43；
Step 45, the first processor submit first affairs.
5. the method as described in claim 1, which is characterized in that judge whether there is and read first data or will read institute After the step of stating the second affairs of the first data further include:
If second affairs read first data, the memory management unit is at the place for executing first affairs Before reason, by first data in second affairs corresponding cache lines copy to first affairs it is corresponding it is privately owned not In visible buffer；
If second affairs will read first data, the memory management unit is executing second affairs Before processing, from the corresponding cache lines of first affairs, first data for not carrying out write operation are copied to described In the corresponding caching of two affairs.
6. a kind of device for concurrently accessing transaction internal memory characterized by comprising
Memory management unit, for when the first affairs need to carry out write operation to the first data, if there is reading described the One data or the second affairs that will read first data then generate the write operation and described second for indicating first affairs The record of the read operation conflict of affairs；
First processing units, for executing the processing of first affairs, when executing completion and receiving second affairs submission Notice after submit first affairs；
The second processing unit submits second affairs and basis for executing the processing of second affairs after the completion of executing The record notifies first affairs.
7. device as claimed in claim 6, which is characterized in that further include:
The first read/write conflict detected register corresponding with the first processing units；
The second read/write conflict detected register corresponding with described the second processing unit；
The memory management unit generates the read operation conflict of the write operation and second affairs that indicate first affairs Record refers to:
The memory management unit is in the first read/write conflict detected register, by the corresponding place of described the second processing unit The set of device marker is managed, will operate conflict mark position is the value for indicating to generate write operation conflict；In second read/write conflict It is table by operation conflict mark position by the corresponding processor flag set of the first processing units in detected register Show the value for generating read operation conflict.
8. device as claimed in claim 7, which is characterized in that described the second processing unit notifies described the according to the record One affairs refer to:
Described the second processing unit searches the processor flag of set in the second read/write conflict detected register；Really The processor flag of fixation position corresponds to the first processing units；Notify described run in the first processing units One affairs.
9. device as claimed in claim 7, which is characterized in that the first processing units include:
First judgment module, the second judgment module；
Execution module indicates that the first judgment module is sentenced after the completion of executing for executing the processing of first affairs It is disconnected；
Module is removed, in the first read/write conflict detected register, inciting somebody to action after receiving the notice of second affairs The corresponding processor flag of described the second processing unit resets；Indicate that second judgment module is judged；
Whether the first judgment module is used to judge the operation conflict mark position in the first read/write conflict detected register To indicate to generate the value of write conflict；If it is indicate that the first judgment module is judged；If it is expression read operation punching Prominent value then indicates that the submission module submits first affairs；
Second judgment module is for judging whether each processor flag is complete in the first read/write conflict detected register Non- set；Indicate that the submission module submits first affairs if complete non-set.
10. device as claimed in claim 6, it is characterised in that:
The memory management unit is also used to when judging that second affairs read first data, in first processing Before unit executes the processing of first affairs, by first data, corresponding cache lines are copied in second affairs In the corresponding privately owned invisible caching of first affairs；When judging that second affairs will read first data, Before described the second processing unit executes the processing of second affairs, from the corresponding cache lines of first affairs, will not into First data of row write operation copy in the corresponding caching of second affairs.
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CN201310492402.3A CN104572506B (en) 2013-10-18 2013-10-18 A kind of method and device concurrently accessing memory
TW103118605A TW201516688A (en) 2013-10-18 2014-05-28 Concurrently accessing memory
PCT/US2014/060901 WO2015057962A1 (en) 2013-10-18 2014-10-16 Concurrently accessing memory
SG11201602639TA SG11201602639TA (en) 2013-10-18 2014-10-16 Concurrently accessing memory
EP14793944.1A EP3058461A1 (en) 2013-10-18 2014-10-16 Concurrently accessing memory
JP2016520133A JP2016537708A (en) 2013-10-18 2014-10-16 Simultaneous access to memory
US14/515,952 US20150113244A1 (en) 2013-10-18 2014-10-16 Concurrently accessing memory
KR1020167009643A KR20160086820A (en) 2013-10-18 2014-10-16 Concurrently accessing memory
HK15106256.9A HK1205806A1 (en) 2013-10-18 2015-07-01 Method for accessing memory concurrently and device thereof

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