CN104572499B - A kind of access mechanism of data high-speed caching - Google Patents
A kind of access mechanism of data high-speed caching Download PDFInfo
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- CN104572499B CN104572499B CN201410843407.0A CN201410843407A CN104572499B CN 104572499 B CN104572499 B CN 104572499B CN 201410843407 A CN201410843407 A CN 201410843407A CN 104572499 B CN104572499 B CN 104572499B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A kind of access mechanism of data high-speed caching, including：Record sheet is accessed, comprising n list item, the positional information for data memory address and its in data high-speed caching；Address comparing unit, for the data address of input to be respectively compared with accessing the address of all list items in record sheet, produces the hit information of n list item；Access control unit, for accessing record sheet according to hit message reference and obtaining corresponding positional information, produces the access control signal to data cache；Stack pointer detection unit, the inspection of stack pointer is carried out for the data address to input, the indication signal of heap stack addressing is produced；Control unit is created, for controlling the list item for accessing record sheet to create；Access record sheet and its positional information in data high-speed caching is recorded in units of cache lines, each list item for accessing record sheet remembers the positional information of M neighbor cache row, and M is integer.Effectively reduction power consumption of the invention, lifting processor performance.
Description
Technical field
The invention belongs to field of microprocessors, it is related to a kind of access mechanism of data high-speed caching, especially one kind can drop
Low data high-speed caches the access mechanism of power consumption.
Background technology
In processor system, cache is set up generally between processor and main storage, to reduce to primary storage
The access of device, improves the storage speed of data, so as to lift the overall performance of memory.
Shown in reference picture 1, the consideration in terms of combination property and power consumption, processor is generally high using k roads-group connected data
Speed caching：For reading data manipulation, processor accesses the k circuit-switched datas array and tag array of data high-speed caching, then root simultaneously
Judge whether that a circuit-switched data can be chosen from k circuit-switched data arrays to be returned according to the comparative result with k road sign label；Behaviour for writing data
Make, then obtain its positional information in the caches by accessing tag array, determine whether to write data according to this information
Enter in k circuit-switched data arrays all the way.But this traditional access mode, the hit rate regardless of cache, are accessed every time
Operation all inevitably needs to conduct interviews to remaining unwanted data in (k-1) road or label.Due to cache
Data array and tag array be all using SRAM as physical store carrier, it is conducted interviews every time be required for voltage driving make
Energy SRAM, this k select 1 access mode to considerably increase the power consumption for accessing cache.
The content of the invention
In order to which the power consumption for the access mechanism for overcoming the shortcomings of data with existing cache is larger, limiting processor performance, this
Invention provides a kind of effective reduction power consumption, lifts the access mechanism that the data high-speed of processor performance is cached.
The technical solution adopted for the present invention to solve the technical problems is：
A kind of access mechanism of data high-speed caching, the access mechanism includes：
Record sheet is accessed, comprising n list item, the position letter for data memory address and its in data high-speed caching
Breath, n is integer；
Address comparing unit, is made up of n comparator, by the data address of input with accessing all list items in record sheet
Address is respectively compared, and produces the hit information of n list item；
Access control unit, is connected to the output end of address comparing unit, according to the hit information of address comparing unit, visits
Ask access record sheet and obtain corresponding positional information, produce the access control signal to data cache；
Stack pointer detection unit, the inspection of stack pointer is carried out for the data address to input, heap stack addressing is produced
Indication signal；
Control unit is created, the output end of address comparing unit and stack pointer detection unit is connected to, for controlling to visit
Ask that the list item of record sheet is created；
Access record sheet and its positional information in data high-speed caching is recorded in units of cache lines, it is each to access record
The list item of table remembers the positional information of M neighbor cache row, and M is integer.
Further, the access mechanism also includes：Feedback unit, for being controlled according to the output result of address comparing unit
Whether the data address of this input is accessed to the positional information write-access record sheet obtained by cache.
Further, the access mechanism also includes：Control unit is emptied, for controlling to access the clear of record sheet content
Sky, i.e., it is invalid all list items to be set to, and access record sheet can be emptied in the following two cases by emptying unit, including：(1) data
Cache there occurs backfill behavior；(2) virtual address changes to the mapping relations of physical address.
Write permission highest of the control unit to access record sheet is emptied, needs to empty the letter for accessing record sheet when emptying unit
During breath, create control unit and feedback unit and the write operation for accessing record sheet is failed.
The list item for accessing record sheet is by effective bit field, address field, location information field and lock field four
Part is constituted：Whether the significance bit field to deposit information effective if characterizing this list item；The address field is used to characterize slow at a high speed
Capable address information is deposited, and is compared with the data address of input；The location information field includes M sub-information, respectively
Store the positional information of corresponding M cache line in the caches；Whether the lock field characterizes this list item and can
It is replaced.
When the output result of the address comparing unit shows the address of the data address of input not with any effective list item
When equal, the establishment control unit is then chosen a list item in record sheet is accessed and created, i.e., the data of input
Location writes the address field of the list item, while effective bit field of the list item has been put, location information field is removed.
If the data address that storehouse detection unit detects input is stack pointer, lock field is put, representing should
List item will retain always, and the establishment control unit will no longer choose the list item and be created.
The address that the input address of the address comparing unit and deposit access record sheet is virtual address.
What the positional information in the data high-speed caching being connected for k roads-group, the list item of access record sheet was recorded is the table
Positional information of the corresponding physical address in address of item in k roads-group associated data cache, this information is completed in the address
To being obtained after the k roads tag access and label of data cache, the position of the list item is written into by feedback unit
In the corresponding sub-information of information field.
Input data address access data high-speed caching before, access control unit can detect its whether and meanwhile meet with
Lower two conditions：A, the data address and the address phase of a certain effective list item of the output result display input of address comparing unit
Deng；B, the positional information of the list item show the corresponding physical address of the table entry address be located at data high-speed cache certain all the way in；
If two conditions are met simultaneously, the read request cached for data high-speed, access control unit is only opened slow at a high speed
The corresponding data array all the way accessed pointed by record list item middle position confidence breath of middle input address is deposited, remaining (K-1) road is closed
Data array and k roads tag array；The write request cached for data high-speed, access control unit can then close total data battle array
Row and tag array, directly obtain the positional information of the input address；
If two conditions are met when different, the read request cached for data high-speed, access control unit can then be opened entirely
Portion's data array and tag array, the write request cached for data high-speed, access control unit can then open k road signs label battle array
Row.
Beneficial effects of the present invention are mainly manifested in：Effectively reduce power consumption, lifting processor performance.
Brief description of the drawings
Fig. 1 charts for the addressing machine of traditional reading k roads-set associative cache data.
Fig. 2 is the access mechanism structure block schematic diagram that a kind of data high-speed is cached.
Fig. 3 is the structure composition instance graph for accessing record sheet.
Fig. 4 is address comparing unit structure example figure.
Fig. 5 is the instance graph that access control unit controls cache access enable signal.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.
2~Fig. 4 of reference picture, a kind of access mechanism of data high-speed caching, including：Access record sheet, address comparing unit,
Access control unit, stack pointer detection unit creates control unit, feedback unit and empties control unit.Wherein：
It is a form for including n list item to access record sheet, address and its cached in data high-speed that log history is accessed
In positional information, by establishment control unit, stack pointer detection unit and empties unit and safeguarded jointly feedback unit.
Address comparing unit includes limited comparator, by the data address of input with accessing the address recorded in record sheet
It is compared, comparative result is exported to access control unit, creating unit and feedback unit.
Output result of the access control unit according to address comparing unit and corresponding positional information control in access record sheet
The access of cache processed enables signal.
Whether the data address of stack pointer detection unit detection input is the access of stack pointer, and by testing result
Export and give establishment control unit.
Create control unit and include an establishment pointer, a certain list item for accessing record sheet is pointed to all the time, control is created single
The output control that member is returned according to address comparing unit and stack pointer detection unit accesses the establishment of record sheet.
Feedback unit controls whether the data address of this input accessing high according to the output result of address comparing unit
Positional information write-access record sheet obtained by speed caching.
Empty control unit control and access emptying for record sheet content, i.e., it is invalid all list items to be set to.Unit is emptied to exist
Access record sheet can be emptied in the case of following two, including：(1) data high-speed caching there occurs backfill behavior；(2) virtual address
Mapping relations to physical address change.
Write permission highest of the control unit to access record sheet is emptied, needs to empty the letter for accessing record sheet when emptying unit
During breath, create control unit and feedback unit and the write operation for accessing record sheet is failed.
Shown in reference picture 3, to access the composition implementation illustration of record sheet.Access record sheet and have n list item, each list item
Information include four：Significance bit, address, positional information and locking bit.Significance bit characterizes this list item and deposits whether information has
Effect；Address is used to be compared with the data address of input；Positional information includes M sub-information, and corresponding M phase is stored respectively
The positional information of adjacent cache lines；Locking bit characterizes whether this list item can be replaced.
In the present embodiment, the bit wide of effective bit field is 1, is represented with vld, and vld=1 represents list item effectively, vld=0 tables
Show invalid.The active position 0 that unit will access all list items of record sheet when emptying is emptied, control unit is created when creating
The active position 1 for the list item that pointer is pointed to will be created.
Access record sheet and record its positional information in data high-speed caching in units of cache lines, list item can be with
The positional information of M adjacent cache lines is recorded, this M adjacent cache lines constitute a cache blocks, and creating unit is cut when creating
Take and represent that one section of cache blocks is deposited into the address field for creating the list item that pointer is pointed in the data address of input.The present embodiment
In, the address field of list item is represented with addr.
The bit wide of each sub-information is k in location information field, is cleared when list item is created, then will by feedback unit
The positional information result that corresponding reference address accesses cache is updated into some sub-information in this region, passes through the number of input
According to allocation index.In the present embodiment, positional information P [M-1:0][k-1:0] represent, wherein [M-1:0] M son letter is represented
Breath, [k-1:0] positional information that a sub-information is recorded is represented, when a certain position is 1 in this k, then this list item record is represented
Corresponding cache lines be located at k roads-group associated data cache in correspondence all the way.
In the present embodiment, the bit wide of locking bit field is 1, is represented with lock, and lock=1 represents that this list item is locked, and needs
To retain always, the list item can not be write by new address by creating control unit；Lock=0 represents that this list item is not locked out, wound
The list item can be write by new address by building control unit.
It is the implementation illustration of the composition of address comparing unit shown in reference picture 4.The data address of input is accessing slow at a high speed
Before depositing, address comparing unit is introduced into, is compared with the address of all list items in access record sheet, is determined and if visit
Ask that a certain effective list item of record sheet is equal, this comparative result will return to access control unit, create control unit and anti-
Present unit.In the present embodiment, the result of return is with the one-hot encoding match [n-1 of n:0] represent, when the reference address of input
With some table entry address for accessing record sheet during equal and this effective list item, then by match [n-1:0] this position is 1,
Otherwise it is set to 0.
When the comparative result that creating unit detects address comparing unit output shows that input address is not visited with any history
When asking that the effective address of record sheet list item is equal, i.e. match [n-1 in the present embodiment:0] 0 is all, control unit is created and then will
Input address write-in creates in the address area of the access record sheet list item pointed by pointer, and the active position of list item is risen,
Positional information is reset.The list item write is needed when creating pointer simultaneously by sensing establishment next time list item.List item is replaced in the present embodiment
The maintenance mechanism changed is fifo algorithm.
When the comparative result that feedback unit detects address comparing unit output shows that input address is not visited with any history
When asking that the effective address of record sheet list item is equal, obtained by feedback unit then conducts interviews this visit address to cache
Hit information updating into corresponding list item.
It is one embodiment figure of access control unit shown in reference picture 5.Compare when access control unit detects address
As a result show that reference address matches the address for a certain effective list item for accessing record sheet, and in the positional information of this list item
Corresponding sub-information shows certain of this address in data high-speed caching all the way, and access control unit then can only enable that all the way
Data array, without enabling k road tag arrays and remaining k-1 circuit-switched data array.And when conditions above is not exclusively met, then also
It is according to traditional access mode, according to access type (read/write) while opening the enable signal of k circuit-switched datas or label, specifically
It is that when reading, while opening the enable signal of k circuit-switched datas and tag array, access type is when writing, to open k road signs for access type
Sign the enable signal of array.
In the present embodiment as match [n-1:0] when xth position is 1, then the son of the positional information of x-th of list item is chosen
Information Px [y] [k-1:0], wherein y represents that the positional information of the data address of input is stored in y-th of sub-information.Define tag_
en[k-1:0] it is the enable signal of tag array, data_en [k-1:0] it is the enable signal of data array, when enable signal
When certain position is 1, characterizes and open corresponding array, otherwise close array.If Px [y] [k-1:0] when a certain position is 1, for reading
Access request, then by tag_en [k-1:0] full 0 is set to, by data_en [k-1:0] it is set to Px [the y] [k-1 selected:0] value,
For write access request, then by tag_en [k-1:0] with data_en [k-1:0] full 0 is set to, and preserves Px [y] [k-1:0]
Value is write data into subsequent operation in the data array specified.If comparative result match [n-1:0] it is all 0 or selects
Positional information Px [y] [k-1:When 0] being all 0, for read access request, then by tag_en [k-1:0] with data_en [k-1:
0] complete 1 is set to, for write access request, then by tag_en [k-1:0] complete 1 is set to, by data_en [k-1:0] full 0 is set to,
Label is compared to obtain the Target Aerial Array positional information that data write back in subsequent operation.
Claims (10)
1. a kind of access mechanism of data high-speed caching, it is characterised in that：The access mechanism includes：
Record sheet is accessed, comprising n list item, the positional information for data memory address and its in data high-speed is cached, n is
Integer；
Address comparing unit, is made up of n comparator, by the data address of input and the address for accessing all list items in record sheet
It is respectively compared, produces the hit information of n list item；
Access control unit, is connected to the output end of address comparing unit, according to the hit information of address comparing unit, accesses and visits
Ask record sheet and obtain corresponding positional information, produce the access control signal to data cache；
Stack pointer detection unit, the inspection of stack pointer is carried out for the data address to input, the finger of heap stack addressing is produced
Show signal；
Control unit is created, the output end of address comparing unit and stack pointer detection unit is connected to, for controlling to access note
The list item for recording table is created；
Access record sheet and its positional information in data high-speed caching is recorded in units of cache lines, each access record sheet
List item remembers the positional information of M neighbor cache row, and M is integer.
2. the access mechanism of data high-speed caching as claimed in claim 1, it is characterised in that：The access mechanism also includes：
Feedback unit, for being controlled whether the data address of this input accessing slow at a high speed according to the output result of address comparing unit
Deposit resulting positional information write-access record sheet.
3. the access mechanism of data high-speed caching as claimed in claim 1 or 2, it is characterised in that：The access mechanism is also wrapped
Include：Control unit is emptied, for controlling to access emptying for record sheet content, i.e., it is invalid all list items to be set to, and empties unit and exists
Access record sheet can be emptied in the case of following two, including：(1) data high-speed caching there occurs backfill behavior；(2) virtual address
Mapping relations to physical address change.
4. the access mechanism of data high-speed caching as claimed in claim 3, it is characterised in that：Control unit is emptied to accessing to remember
The write permission highest of table is recorded, when emptying unit and needing to empty the information for accessing record sheet, control unit and feedback unit is created
The write operation for accessing record sheet is failed.
5. the access mechanism of data high-speed caching as claimed in claim 1 or 2, it is characterised in that：The access record sheet
List item is made up of effective bit field, address field, location information field and the part of lock field four：The significance bit field list
Whether levying this list item, to deposit information effective；The address field is used to characterizing the address information of cache line, and with input
Data address is compared；The location information field includes M sub-information, and corresponding M cache line is stored respectively and is existed
Positional information in cache；The lock field characterizes whether this list item can be replaced.
6. the access mechanism of data high-speed caching as claimed in claim 5, it is characterised in that：When the address comparing unit
When the data address of output result display input is equal not with the address of any effective list item, the establishment control unit is then being visited
Ask and chosen in record sheet that a list item is created, i.e., write the data address of input the address field of the list item, while handle
Effective bit field of the list item has been put, and location information field is removed.
7. the access mechanism of data high-speed caching as claimed in claim 6, it is characterised in that：If storehouse detection unit is detected
When the data address of input is stack pointer, lock field has been put, has represented that the list item will retain always, it is described to create control list
Member will no longer choose the list item and be created.
8. the access mechanism of data high-speed caching as claimed in claim 1 or 2, it is characterised in that：The address comparing unit
Input address and deposit access record sheet address be virtual address.
9. the access mechanism of data high-speed caching as claimed in claim 2, it is characterised in that：The data being connected for k roads-group
Cache, access record sheet list item in positional information record be the list item the corresponding physical address in address k roads-
Positional information in group associated data cache, k road tag access of this information in the complete paired data cache in the address
And obtained after label, it is written into by feedback unit in the corresponding sub-information of the location information field of the list item.
10. the access mechanism of data high-speed caching as claimed in claim 9, it is characterised in that：Visited in the data address of input
Ask before data high-speed caching, whether access control unit can detect it while meeting following two conditions：A, address comparing unit
Output result display input data address it is equal with the address of a certain effective list item；B, the positional information of the list item show this
The corresponding physical address of table entry address be located at data high-speed cache certain all the way in；
If two conditions are met simultaneously, the read request cached for data high-speed, access control unit is only opened in cache
Input address is corresponding to access the pointed data array all the way of record list item middle position confidence breath, closes remaining (k-1) circuit-switched data
Array and k roads tag array；For data high-speed cache write request, access control unit can then close total data array and
Tag array, directly obtains the positional information of the input address；
If two conditions are met when different, the read request cached for data high-speed, access control unit can then open whole numbers
According to array and tag array, the write request cached for data high-speed, access control unit can then open k roads tag array.
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| CN108519858B (en) * | 2018-03-22 | 2021-06-08 | 雷科防务（西安）控制技术研究院有限公司 | Memory chip hardware hit method |
| US20200301840A1 (en) * | 2019-03-20 | 2020-09-24 | Shanghai Zhaoxin Semiconductor Co., Ltd. | Prefetch apparatus and method using confidence metric for processor cache |
| CN114528229A (en) * | 2022-04-21 | 2022-05-24 | 飞腾信息技术有限公司 | Cache data access method and device and electronic equipment |
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| DE10102202A1 (en) * | 2001-01-18 | 2002-08-08 | Infineon Technologies Ag | Microprocessor circuit for portable data carriers |
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| CN101178690A (en) * | 2007-12-03 | 2008-05-14 | 浙江大学 | Design method of low-power consumption high performance high speed scratch memory |
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