CN104539642A - Device and method for hardware acceleration of Internet of things module equipment based on infection control protocol package - Google Patents
Device and method for hardware acceleration of Internet of things module equipment based on infection control protocol package Download PDFInfo
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- CN104539642A CN104539642A CN201410593007.9A CN201410593007A CN104539642A CN 104539642 A CN104539642 A CN 104539642A CN 201410593007 A CN201410593007 A CN 201410593007A CN 104539642 A CN104539642 A CN 104539642A
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Abstract
The invention discloses a device and a method for hardware acceleration of Internet of things module equipment based on an infection control protocol package. By adopting a concurrent optimal line speed data acquisition structure, the locking expenditure for multithread shared data of software is unloaded, data distribution is implemented in hardware by utilizing a load balancing unit, and then data packages are respectively transmitted to different memory buffer zones of a host at high speed through DMA (Direct Memory Access) channels. Therefore, when the data packages enter a back-end server, data-level parallel decomposition is implemented, data of each processing thread of the back end is completely independent, lock-free programming can be implemented and the mutual exclusion expenditure for the threads is avoided. Meanwhile, a back-end host can work in combination with an annular buffer zone technology and a zero copy technology, so that the expenditure for data copy is avoided.
Description
Technical field
The present invention relates to informatization, particularly a kind of thing gang mould group device hardware accelerator based on sense control protocol package and method.
Background technology
Along with the propelling of medical information, the informatization of hospital will gradually by systems such as HIS system, EMR to each special outpatient clinic deeply.Hospital's sense control control is an important step on Hospital medical administration of health, obtains to preventing institute-level infection, patient in hospital the function and significance that the aspects such as antibacterial drug therapy all have positive important in time.Being limited to the institute-level server system of existing hospital and software running platform, there is many destabilizing factors in institute-level sense Ore-controlling Role, and such as system cloud gray model is unstable, outpatient service not to catch up with patient peak period and to see and treat patients the demand etc. that quantity rises.
These are all the performance bottleneck problems outstanding because hospital information system is realized by pure software mode.In traditional data acquisition structure of simultaneously hospital information system, DMA (direct memory access) engine only devises a transmission channel.The expense that locks when software multithread shares data is very large, causes Load Balance Unit cannot realize data and distributes in real time, makes packet cannot by the different core buffers of DMA (direct memory access) passage high-speed transfer to main frame.Therefore, packet cannot enter back-end server, and data processing is delayed, even causes data system instability and systemic breakdown.
Summary of the invention
The object of the present invention is to provide a kind of thing gang mould group device hardware accelerator based on sense control protocol package and method, existing hospital information system can be solved and realized by pure software mode and cause instability, the problem of easy systemic breakdown.
For this reason, the invention provides a kind of thing gang mould group device hardware accelerator based on sense control protocol package, comprising: datum plane construction unit, pretreatment unit, arbitration unit, pipelining-stage backend unit,
Described datum plane construction unit, in order to when each packet enters receiving queue, stamps a hardware timestamping.
Described pretreatment unit, in order to resolve and preliminary treatment layer data packet agreement, according to different application demands, is configured by programmable interface, makes packet enter processing unit selectively and carries out subsequent treatment;
Described arbitration unit, in order to arbitrate the result of each processing unit for parallel execution;
Described pipelining-stage backend unit, is copied into two-way by packet, gathers according to arbitration result and forwards two paths of data bag.
Optionally, described pretreatment unit has the processing unit of several bag taxons, stream table query unit composition, according to different application demands, configured by programmable interface, make packet enter one or more processing units in bag taxon, stream table query unit selectively, carry out subsequent treatment.
Optionally, the algorithm that described arbitration is followed is: according to the class categories of packet, the interpretation of result of stream table inquiry that enter processing unit, draw the priority of a result, this priority is according to Rm, the priority of Wm infers the sequence drawing priority, as arbitration process bus An (n=1,2,3 ...) obtain the foundation identified:
Rm represents and reads programmable interface,
Wm represents and writes programmable interface,
Rn (n=0,1,2) and Wn (n=0,1,2,3 ...) represent that N number of processing unit is to the read-write operation of port respectively, || (or) (representing logic OR), & & (and) (representing logical AND)
1) algorithm is read:
Rm＝R0&&(R1||/W0)&&(R2||/W1||/W0)&&……
2) algorithm is write:
Wm＝W0&&(W1||/R0)&&(W2||/R0||/R1)&&(W3||/R0||/R1||/R2)&&……
3) bus obtains mark:
A1＝(R1||W1)&&/(R0||W0)
A2＝(R2||W2)&&/(R1||W1)&&/(R0||W0)
A3＝W3&&/(R2||W2)&&/(R1||W1)&&/(R0||W0)……。
Optionally, described pipelining-stage backend unit, comprise packet capture unit, packet retransmission unit, in order to packet is copied into two-way: packet capture unit says that packet sends into collecting part, transfers to back-end server process further by load balancing and multi-channel high-speed DMA engine; Packet is sent into forwarding engine by packet retransmission unit, provides packet forward-path fast, according to concrete application demand, selects to clean flow and control.
Optionally, described arbitration modules is also responsible for encapsulating packet, is contained in the record of user-defined format, for subsequent treatment by the result of front-end processing unit and whole data envelope.
Present invention also offers a kind of thing gang mould group device hardware accelerated method based on sense control protocol package, comprising:
When each packet enters receiving queue, stamp a hardware timestamping.
Layer data packet agreement is resolved and preliminary treatment, according to different application demands, is configured by programmable interface, make packet enter processing unit selectively and carry out subsequent treatment;
The result of each processing unit for parallel execution is arbitrated;
Packet is copied into two-way, according to arbitration result, two paths of data bag is gathered and forwarded.
Optionally, back-end server uses buffer circle technology and zero duplication technology.
Optionally, according to arbitration result, packet is copied into two-way: packet is sent into collecting part by a road, transfers to back-end server by load balancing and multi-channel high-speed DMA engine and process further; Packet is sent into forwarding engine by another road, provides packet forward-path fast, according to concrete application demand, selects to clean flow and control.
Optionally, arbitrated procedure also comprises and encapsulating packet, is contained in the record of user-defined format, for subsequent treatment by the result of front-end processing unit and whole data envelope.
Optionally, the algorithm that described arbitration is followed is: according to the class categories of packet, the interpretation of result of stream table inquiry that enter processing unit, draw the priority of a result, this priority is according to Rm, the priority of Wm infers the sequence drawing priority, as arbitration process bus An (n=1,2,3 ...) obtain the foundation identified:
Rm represents and reads programmable interface
Wm represents and writes programmable interface
Rn (n=0,1,2) and Wn (n=0,1,2,3 ...) represent that N number of processing unit is to the read-write operation of port respectively, || (or) (representing logic OR), & & (and) (representing logical AND).
1) algorithm is read:
Rm＝R0&&(R1||/W0)&&(R2||/W1||/W0)&&……
2) algorithm is write:
Wm＝W0&&(W1||/R0)&&(W2||/R0||/R1)&&(W3||/R0||/R1||/R2)&&……
3) bus obtains mark:
A1＝(R1||W1)&&/(R0||W0)
A2＝(R2||W2)&&/(R1||W1)&&/(R0||W0)
A3＝W3&&/(R2||W2)&&/(R1||W1)&&/(R0||W0)……。
The invention has the beneficial effects as follows:
The present invention adopts the linear speed data acquisition structure of a parallel optimization, uninstall multithreading shares the expense that locks of data, working load balanced unit realizes Data dissemination within hardware, then packet is passed through the different core buffers of DMA (direct memory access) passage difference high-speed transfer to main frame.Therefore, when packet enters back-end server, achieved the parallel decomposition of data level, it is completely independent that rear end respectively processes thread-data, can realize, without lock programming, avoiding Line Procedure Mutually-exclusive expense.Meanwhile, back-end host with the use of buffer circle technology and zero duplication technology, can avoid the expense of data copy.
Accompanying drawing explanation
Fig. 1 is the acceleration design theory schematic diagram of the embodiment of the present invention;
Fig. 2 is the structural representation of the hardware accelerator of the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment, clear, complete description is carried out to technical scheme of the present invention.
Please refer to Fig. 1 and Fig. 2, for the acceleration design theory schematic diagram of the embodiment of the present invention and the structural representation of hardware accelerator, the described thing gang mould group device hardware accelerated method based on sense control protocol package comprises: datum plane construction unit 10, pretreatment unit 20, arbitration unit 30, pipelining-stage backend unit 40
Described datum plane construction unit 10, in order to when each packet enters receiving queue, stamps a hardware timestamping.
Described pretreatment unit 20, in order to resolve and preliminary treatment layer data packet agreement, according to different application demands, is configured by programmable interface, makes packet enter processing unit selectively and carries out subsequent treatment;
Described arbitration unit 30, in order to arbitrate the result of each processing unit for parallel execution;
Described pipelining-stage backend unit 40, is copied into two-way by packet, gathers according to arbitration result and forwards two paths of data bag.
Described datum plane structure 10, uses flowing water and concurrent technique, in order to when each packet enters receiving queue, stamps a hardware timestamping immediately.
The embodiment of the present invention adopts the hardware timestamping marking circuit of GAL, when each packet enters receiving queue, stamps a hardware timestamping.This GAL hardware timestamping marking circuit can be real-time the transmitting-receiving timestamp of mark time synchronized message.
Described pretreatment unit 20 has the processing unit of several bag taxons, stream table query unit composition, according to different application demands, configured by programmable interface, make packet enter one or more processing units in bag taxon, stream table query unit selectively, carry out subsequent treatment.
In the present embodiment, arbitrating to the result of each processing unit the algorithm followed is: according to the class categories of packet, the interpretation of result of stream table inquiry that enter processing unit, draw the priority of a result, this priority is according to Rm, the priority of Wm infers the sequence drawing priority, as arbitration process bus An (n=1,2,3 ...) obtain the foundation identified:
Rm represents and reads programmable interface,
Wm represents and writes programmable interface,
Rn (n=0,1,2) and Wn (n=0,1,2,3 ...) represent that N number of processing unit is to the read-write operation of port respectively, || (or) (representing logic OR), & & (and) (representing logical AND)
1) algorithm is read:
Rm＝R0&&(R1||/W0)&&(R2||/W1||/W0)&&……
2) algorithm is write:
Wm＝W0&&(W1||/R0)&&(W2||/R0||/R1)&&(W3||/R0||/R1||/R2)&&……
3) bus obtains mark:
A1＝(R1||W1)&&/(R0||W0)
A2＝(R2||W2)&&/(R1||W1)&&/(R0||W0)
A3＝W3&&/(R2||W2)&&/(R1||W1)&&/(R0||W0)……。
In other embodiments, described arbitration modules is also responsible for encapsulating packet, is contained in the record of user-defined format, for subsequent treatment by the result of front-end processing unit and whole data envelope.
According to the arbitration result of above-mentioned arbitration algorithm, Data dissemination can be realized within hardware, therefore described pipelining-stage backend unit 40, comprise packet capture unit, packet retransmission unit, in order to packet is copied into two-way: packet capture unit says that packet sends into collecting part, transfer to back-end server by load balancing and multi-channel high-speed DMA engine, process further in the core that namely in Fig. 2, each internal memory of main frame is namely corresponding; Packet is sent into forwarding engine by packet retransmission unit, provides packet forward-path fast, according to concrete application demand, selects to clean flow and control.
According to above-mentioned hardware accelerator, present invention also offers a kind of thing gang mould group device hardware accelerated method based on sense control protocol package, comprising:
Use flowing water and concurrent technique, in order to when each packet enters receiving queue, stamp a hardware timestamping.
Layer data packet agreement is resolved and preliminary treatment, according to different application demands, is configured by programmable interface, make packet enter processing unit selectively and carry out subsequent treatment;
The result of each processing unit for parallel execution is arbitrated;
Packet is copied into two-way, according to arbitration result, two paths of data bag is gathered and forwarded.
Optionally, according to arbitration result, packet is copied into two-way: packet is sent into collecting part by a road, transfers to back-end server by load balancing and multi-channel high-speed DMA engine and process further; Packet is sent into forwarding engine by another road, provides packet forward-path fast, according to concrete application demand, selects to clean flow and control.
Optionally, arbitrated procedure also comprises and encapsulating packet, is contained in the record of user-defined format, for subsequent treatment by the result of front-end processing unit and whole data envelope.
The present invention adopts the linear speed data acquisition structure of a parallel optimization, uninstall multithreading shares the expense that locks of data, working load balanced unit realizes Data dissemination within hardware, then packet is passed through the different core buffers of DMA (direct memory access) passage difference high-speed transfer to main frame.Therefore, when packet enters back-end server, achieved the parallel decomposition of data level, it is completely independent that rear end respectively processes thread-data, can realize, without lock programming, avoiding Line Procedure Mutually-exclusive expense.Meanwhile, back-end host with the use of buffer circle technology and zero duplication technology, can avoid the expense of data copy.
Although last it is noted that the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (10)
1., based on a thing gang mould group device hardware accelerator for sense control protocol package, it is characterized in that, comprising: datum plane construction unit, pretreatment unit, arbitration unit, pipelining-stage backend unit,
Described datum plane construction unit, in order to when each packet enters receiving queue, stamps a hardware timestamping.
Described pretreatment unit, in order to resolve and preliminary treatment layer data packet agreement, according to different application demands, is configured by programmable interface, makes packet enter processing unit selectively and carries out subsequent treatment;
Described arbitration unit, in order to arbitrate the result of each processing unit for parallel execution;
Described pipelining-stage backend unit, is copied into two-way by packet, gathers according to arbitration result and forwards two paths of data bag.
2. as claimed in claim 1 based on the thing gang mould group device hardware accelerator of sense control protocol package, it is characterized in that, described pretreatment unit has the processing unit of several bag taxons, stream table query unit composition, according to different application demands, configured by programmable interface, make packet enter one or more processing units in bag taxon, stream table query unit selectively, carry out subsequent treatment.
3. as claimed in claim 1 based on the thing gang mould group device hardware accelerator of sense control protocol package, it is characterized in that, the algorithm that described arbitration is followed is: according to the class categories of packet, the interpretation of result of stream table inquiry that enter processing unit, draw the priority of a result, this priority infers the sequence drawing priority, as arbitration process bus An (n=1 according to the priority of Rm, Wm, 2,3 ...) obtain the foundation identified:
Rm represents and reads programmable interface,
Wm represents and writes programmable interface,
Rn (n=0,1,2) and Wn (n=0,1,2,3 ...) represent that N number of processing unit is to the read-write operation of port respectively, || (or) (representing logic OR), & & (and) (representing logical AND)
1) algorithm is read:
Rm＝R0&&(R1||/W0)&&(R2||/W1||/W0)&&……
2) algorithm is write:
Wm＝W0&&(W1||/R0)&&(W2||/R0||/R1)&&(W3||/R0||/R1||/R2)&&……
3) bus obtains mark:
A1＝(R1||W1)&&/(R0||W0)
A2＝(R2||W2)&&/(R1||W1)&&/(R0||W0)
A3＝W3&&/(R2||W2)&&/(R1||W1)&&/(R0||W0)……。
4. as claimed in claim 1 based on the thing gang mould group device hardware accelerator of sense control protocol package, it is characterized in that, described pipelining-stage backend unit, comprise packet capture unit, packet retransmission unit, in order to packet is copied into two-way: packet capture unit says that packet sends into collecting part, transfers to back-end server process further by load balancing and multi-channel high-speed DMA engine; Packet is sent into forwarding engine by packet retransmission unit, provides packet forward-path fast, according to concrete application demand, selects to clean flow and control.
5. as claimed in claim 1 based on the thing gang mould group device hardware accelerator of sense control protocol package, it is characterized in that, described arbitration modules is also responsible for encapsulating packet, the result of front-end processing unit and whole data envelope are contained in the record of user-defined format, for subsequent treatment.
6., based on a thing gang mould group device hardware accelerated method for sense control protocol package, it is characterized in that, comprising:
When each packet enters receiving queue, stamp a hardware timestamping.
Layer data packet agreement is resolved and preliminary treatment, according to different application demands, is configured by programmable interface, make packet enter processing unit selectively and carry out subsequent treatment;
The result of each processing unit for parallel execution is arbitrated;
Packet is copied into two-way, according to arbitration result, two paths of data bag is gathered and forwarded.
7., as claimed in claim 6 based on the thing gang mould group device hardware accelerated method of sense control protocol package, it is characterized in that, back-end server uses buffer circle technology and zero duplication technology.
8. as claimed in claim 6 based on the thing gang mould group device hardware accelerated method of sense control protocol package, it is characterized in that, according to arbitration result, packet is copied into two-way: packet is sent into collecting part by a road, transfers to back-end server by load balancing and multi-channel high-speed DMA engine and process further; Packet is sent into forwarding engine by another road, provides packet forward-path fast, according to concrete application demand, selects to clean flow and control.
9. as claimed in claim 6 based on the thing gang mould group device hardware accelerated method of sense control protocol package, it is characterized in that, arbitrated procedure also comprises and encapsulating packet, is contained in the record of user-defined format, for subsequent treatment by the result of front-end processing unit and whole data envelope.
10. as claimed in claim 6 based on the thing gang mould group device hardware accelerated method of sense control protocol package, it is characterized in that, the algorithm that described arbitration is followed is: according to the class categories of packet, the interpretation of result of stream table inquiry that enter processing unit, draw the priority of a result, this priority infers the sequence drawing priority, as arbitration process bus An (n=1 according to the priority of Rm, Wm, 2,3 ...) obtain the foundation identified:
Rm represents and reads programmable interface
Wm represents and writes programmable interface
Rn (n=0,1,2) and Wn (n=0,1,2,3 ...) represent that N number of processing unit is to the read-write operation of port respectively, || (or) (representing logic OR), & & (and) (representing logical AND).
1) algorithm is read:
Rm＝R0&&(R1||/W0)&&(R2||/W1||/W0)&&……
2) algorithm is write:
Wm＝W0&&(W1||/R0)&&(W2||/R0||/R1)&&(W3||/R0||/R1||/R2)&&……
3) bus obtains mark:
A1＝(R1||W1)&&/(R0||W0)
A2＝(R2||W2)&&/(R1||W1)&&/(R0||W0)
A3＝W3&&/(R2||W2)&&/(R1||W1)&&/(R0||W0)……。
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106339257A (en) * | 2015-07-10 | 2017-01-18 | 中标软件有限公司 | Method and system for lightweighting client computer operating system and virtualized operating system |
| CN110178118A (en) * | 2017-01-17 | 2019-08-27 | 微软技术许可有限责任公司 | Hard-wired load balance |
| CN116483013A (en) * | 2023-06-19 | 2023-07-25 | 成都实时技术股份有限公司 | High-speed signal acquisition system and method based on multichannel collector |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070201458A1 (en) * | 2006-02-28 | 2007-08-30 | Thron Chris P | System and method for implementing ACLs using multiple hash-trie-key tables |
| CN101286936A (en) * | 2008-05-16 | 2008-10-15 | 华为技术有限公司 | Method and apparatus for data message processing |
| CN101540727A (en) * | 2009-05-05 | 2009-09-23 | 曙光信息产业(北京)有限公司 | Hardware shunt method of IP report |
| CN102497322A (en) * | 2011-12-19 | 2012-06-13 | 曙光信息产业(北京)有限公司 | High-speed packet filtering device and method realized based on shunting network card and multi-core CPU (Central Processing Unit) |
| CN102769575A (en) * | 2012-08-08 | 2012-11-07 | 南京中兴特种软件有限责任公司 | Flow load balancing method for intelligent network card |
| CN102916905A (en) * | 2012-10-18 | 2013-02-06 | 曙光信息产业(北京)有限公司 | Gigabit network card multi-path shunting method and system based on hash algorithm |
-
2014
- 2014-10-29 CN CN201410593007.9A patent/CN104539642A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070201458A1 (en) * | 2006-02-28 | 2007-08-30 | Thron Chris P | System and method for implementing ACLs using multiple hash-trie-key tables |
| CN101286936A (en) * | 2008-05-16 | 2008-10-15 | 华为技术有限公司 | Method and apparatus for data message processing |
| CN101540727A (en) * | 2009-05-05 | 2009-09-23 | 曙光信息产业(北京)有限公司 | Hardware shunt method of IP report |
| CN102497322A (en) * | 2011-12-19 | 2012-06-13 | 曙光信息产业(北京)有限公司 | High-speed packet filtering device and method realized based on shunting network card and multi-core CPU (Central Processing Unit) |
| CN102769575A (en) * | 2012-08-08 | 2012-11-07 | 南京中兴特种软件有限责任公司 | Flow load balancing method for intelligent network card |
| CN102916905A (en) * | 2012-10-18 | 2013-02-06 | 曙光信息产业(北京)有限公司 | Gigabit network card multi-path shunting method and system based on hash algorithm |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106339257A (en) * | 2015-07-10 | 2017-01-18 | 中标软件有限公司 | Method and system for lightweighting client computer operating system and virtualized operating system |
| CN110178118A (en) * | 2017-01-17 | 2019-08-27 | 微软技术许可有限责任公司 | Hard-wired load balance |
| CN110178118B (en) * | 2017-01-17 | 2023-06-23 | 微软技术许可有限责任公司 | Hardware implemented load balancing |
| CN116483013A (en) * | 2023-06-19 | 2023-07-25 | 成都实时技术股份有限公司 | High-speed signal acquisition system and method based on multichannel collector |
| CN116483013B (en) * | 2023-06-19 | 2023-09-05 | 成都实时技术股份有限公司 | High-speed signal acquisition system and method based on multichannel collector |
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