CN104537984A - Pixel circuit and driving method thereof - Google Patents

Abstract

The invention relates to the technical field of display, in particular to a pixel circuit and a driving method of the pixel circuit. The pixel circuit comprises a driving sub-circuit, a reset sub-circuit and a charging sub-circuit, wherein the driving sub-circuit comprises a driving transistor, a first transistor, a third transistor, a first storage capacitor and a second storage capacitor; the reset sub-circuit is used for discharging the first storage capacitor and the second storage capacitor under the control of a first scanning signal output from a first scanning signal line; the charging sub-circuit comprises a fifth transistor and a sixth transistor. According to the pixel circuit, heterogeneity caused by the threshold voltage of the driving transistor and the ghost shadow phenomenon caused by threshold voltage drifting can be effectively eliminated through compensation; the problem that the brightness of an active matrix light-emitting organic electrical display tube is not uniform because light-emitting devices of different pixel units in the active matrix light-emitting organic electrical display tube are different in threshold voltage of the driving transistor is avoided.

Description

A kind of image element circuit and driving method thereof

Technical field

The present invention relates to display technique field, particularly relate to a kind of image element circuit and driving method thereof.

Background technology

Organic electroluminescent LED (OLED, Organic Light-Emitting Diode) is applied in high-performance active matrix light-emitting organic electroluminescence display tube more and more as a kind of current mode luminescent device.Traditional passive matrix ORGANIC ELECTROLUMINESCENCE DISPLAYS pipe (Passive MatrixOLED), along with the increase of display size, needs the driving time of shorter single pixel, thus needs to increase transient current, increases power consumption.The application of big current simultaneously can cause pressure drop on nano indium tin metal oxide line excessive, and makes OLED operating voltage too high, and then reduces its efficiency.And active matrix OLED pipe (AMOLED, Active Matrix OLED) to be lined by line scan input OLED electric current by switching transistor, can address these problems well.

In the back plate design of AMOLED, the problem that main needs solve is the luminance non-uniformity between the compensating circuit of each AMOLED pixel cell.

First, AMOLED adopts thin film transistor (TFT) (TFT, Thin-Film Transistor) to build image element circuit for luminescent device and provides corresponding drive current.In prior art, mostly adopt low-temperature polysilicon film transistor or oxide thin film transistor.Compared with general amorphous silicon film transistor, low-temperature polysilicon film transistor and oxide thin film transistor have higher mobility and more stable characteristic, are more suitable for being applied in AMOLED display.But due to the limitation of crystallization process, the low-temperature polysilicon film transistor that large-area glass substrate makes, usually on the such as electrical parameter such as threshold voltage, mobility, there is heterogeneity, this heterogeneity can be converted into drive current difference and the luminance difference of OLED, and by the perception of human eye institute, i.e. look uneven phenomenon.Although the homogeneity of oxide thin film transistor technique is better, but it is similar with amorphous silicon film transistor, under long-time pressurization and high temperature, its threshold voltage there will be drift, because display frame is different, the threshold drift amount of panel each several part thin film transistor (TFT) is different, can cause display brightness difference, due to this species diversity with to show before image-related, be therefore often rendered as ghost phenomena.

Second, in large scale display application, because backboard power lead exists certain resistance, and the drive current of all pixels is all provided by supply voltage (ARVDD), therefore compare from for electric position near the supply voltage of the ARVDD Power supply band of position in backboard and want high compared with the supply voltage of far region, this phenomenon is called as power voltage-drop.Because the voltage of ARVDD is relevant to electric current, power voltage-drop also can cause the drive current difference of zones of different, and then produces look uneven phenomenon when showing.Adopt the low temperature polysilicon process of P type TFT structure pixel cell especially responsive to this problem, because its memory capacitance is connected between ARVDD and TFT grid, the voltage of ARVDD changes, and directly can affect the grid voltage V of drive TFT pipe _gs.

3rd, the heterogeneity that luminescent device also can cause electric property when evaporation because thickness is uneven.For the amorphous silicon or the oxide thin film transistor technique that adopt N-type TFT to build pixel cell, its memory capacitance is connected between drive TFT grid and luminescent device anode, when data voltage is transferred to grid, if each pixel light emission device first voltage end is different, then the grid voltage V of actual loaded on TFT _gsdifference, thus drive current difference causes display brightness difference.

Therefore, for solving the problem, the present invention is badly in need of providing a kind of image element circuit and driving method thereof.

Summary of the invention

Technical matters solved by the invention is to provide a kind of image element circuit and driving method thereof, the heteropical object of drive transistor threshold voltage that the image element circuit for solving prior art occurs when compensating.

The object of the invention is to be achieved through the following technical solutions: a kind of image element circuit, comprises reset subcircuit, charging electronic circuit, drive sub-circuits and luminescent device, wherein,

The first end of described luminescent device connects the second voltage end;

Described drive sub-circuits comprises driving transistors, the first transistor, third transistor and the first memory capacitance, the second memory capacitance, the source electrode of described driving transistors connects the drain electrode of described the first transistor and the drain electrode of described third transistor, the drain electrode of described driving transistors connects the second end of described luminescent device, and the grid of described driving transistors connects the first end of described first memory capacitance; The source electrode of described the first transistor connects the first voltage end, and the grid of described the first transistor connects the first end of described second memory capacitance;

Second end of described second memory capacitance connects reference voltage end; The source electrode of described third transistor connects the grid of described driving transistors, and the drain electrode of described third transistor connects the source electrode of described driving transistors, and the grid of described third transistor connects the first scan signal line;

Described reset subcircuit is discharged to described first memory capacitance and described second memory capacitance under being used for the control of the first sweep signal exported at the first scan signal line;

Described charging electronic circuit comprises the 5th transistor and the 6th transistor, the source electrode connection data voltage input end of described 5th transistor, the drain electrode of described 5th transistor connects the source electrode of described 4th transistor, and the grid of described 5th transistor connects the second scan signal line; The grid of described 6th transistor is connected the 3rd scan signal line with the source electrode of described 6th transistor, and the drain electrode of described 6th transistor connects the source electrode of described transistor seconds.

Further, described reset subcircuit comprises transistor seconds and the 4th transistor, the source electrode of described transistor seconds connects the grid of described the first transistor, and the drain electrode of described transistor seconds connects described reference voltage end, and the grid of described transistor seconds connects the first scan signal line; The source electrode of described 4th transistor connects the second end of described first memory capacitance, and the drain electrode of described 4th transistor connects described reference voltage end, and the grid of described 4th transistor connects the first scan signal line.

Further, described reset subcircuit comprises transistor seconds and the 4th transistor, the source electrode of described transistor seconds connects the grid of described the first transistor, the drain electrode of described transistor seconds connects the source electrode of described 4th transistor, and the grid of described transistor seconds connects the first scan signal line; The source electrode of described 4th transistor connects the second end of described first memory capacitance, and the drain electrode of described 4th transistor connects described reference voltage end, and the grid of described 4th transistor connects the first scan signal line.

Further, the grid of described 5th transistor, the grid of described 6th transistor are connected the second scan signal line with the source electrode of described 6th transistor simultaneously.

Further, described luminescent device is organic electroluminescent LED.

Further, described driving transistors, the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor are n type field effect transistor.

According to a driving method for image element circuit described in above-mentioned, it is characterized in that, described method comprises:

Reseting stage, described first scan signal line opens described transistor seconds, third transistor and the 4th transistor, described second memory capacitance stored charge is discharged by transistor seconds, the first end stored charge of described first memory capacitance is via the release of described third transistor, driving transistors and luminescent device, and the second end stored charge of described first memory capacitance is by the 4th transistor release;

Compensated stage, described first scan signal line closes described transistor seconds, third transistor and the 4th transistor, described second scan signal line opens described 5th transistor, described 3rd scan signal line opens described 6th transistor, and described 3rd scan signal line is charged to described second memory capacitance by described 6th transistor; Described data voltage input end is charged to described first memory capacitance by described 5th transistor;

Glow phase, described first scan signal line closes described transistor seconds, third transistor and the 4th transistor, described second scan signal line closes described 5th transistor and the 6th transistor, described second memory capacitance opens described the first transistor, the electric charge that described first memory capacitance stores opens described driving transistors, drives described luminescent device luminous.

Further, described second scan signal line controls described 5th transistor and described 6th transistor unlatching simultaneously or closes.

Further, also comprise:

Reseting stage, described first scan signal line opens described transistor seconds, third transistor and the 4th transistor; Described third transistor opens described driving transistors; The first end stored charge of described second memory capacitance is discharged via described 4th transistor by described transistor seconds, thus closes described the first transistor; The first end stored charge of described first memory capacitance is via the release of described third transistor, driving transistors and luminescent device, and the second end stored charge of described first memory capacitance is by the 4th transistor release.

The present invention compared with prior art has following advantage:

1, image element circuit of the present invention, can in the process that luminescent device is compensated, effectively eliminate heterogeneity that N-shaped depletion type or enhancement mode TFT driving transistors cause by self threshold voltage by compensating and to drift about the ghost phenomena caused because of threshold voltage; Avoid the problem of the active matrix light-emitting organic electroluminescence display tube brightness disproportionation caused because of the threshold voltage difference of its driving transistors between the luminescent device of different pixels unit in active matrix light-emitting organic electroluminescence display tube; In addition, the heterogeneity of the electric property that luminescent device causes due to thickness inequality when evaporation effectively can be eliminated by image element circuit of the present invention, and the difference of the drive current of each luminescent device in the active matrix light-emitting organic electroluminescence display tube caused by luminescent device heterogeneity; Improve the compensation effect of image element circuit to luminescent device, further increase the quality of active matrix light-emitting organic electroluminescence display tube.

2, the present invention adopts the design comprising the 3rd scan signal line, described 6th transistor AND gate being used for controlling described second memory capacitance charging can be used for the described 5th transistor separately scanning of controlled loading data voltage and the charging of the first memory capacitance; Namely the charging process of the first memory capacitance originally completed at the same time and the charging process of the second memory capacitance are divided into two steps to carry out; Realize the precharge first the first memory capacitance being carried out to certain hour thus, then by charging in order to open the first transistor to the second memory capacitance, make the object that luminous working power is opened; Because the charging of memory capacitance and release need certain hour, therefore adopt such design can solve because of not enough to the first memory capacitance duration of charging, the uneven insufficient problem of the compensation brought.

Accompanying drawing explanation

Below in conjunction with drawings and Examples, the invention will be further described.

Fig. 1 is the circuit connection diagram of image element circuit described in the embodiment of the present invention one;

Fig. 2 is the step block diagram of driving method described in the embodiment of the present invention one;

Fig. 3 is the sequential control schematic diagram of driving method described in the embodiment of the present invention one;

Fig. 4 is the circuit connection diagram of image element circuit described in the embodiment of the present invention two;

Fig. 5 is the step block diagram of the driving method of image element circuit described in the embodiment of the present invention two;

Fig. 6 is the sequential control schematic diagram of driving method described in the embodiment of the present invention two;

Fig. 7 is the circuit connection diagram of image element circuit described in the embodiment of the present invention three;

Fig. 8 is the step block diagram of the driving method of image element circuit described in the embodiment of the present invention three;

Fig. 9 is the sequential control schematic diagram of driving method described in the embodiment of the present invention three.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

Embodiment one:

Shown in Figure 1, the driving that image element circuit described in the embodiment of the present invention is mainly used in each luminescent device in active matrix light-emitting organic electroluminescence display tube compensates, each luminescent device is driven by an image element circuit and compensates, each image element circuit comprises: reset subcircuit, charging electronic circuit, drive sub-circuits and luminescent device; Wherein,

The first end of described luminescent device OLED connects the second voltage end ELVSS;

Described drive sub-circuits comprises driving transistors DTFT, the first transistor T1, third transistor T3 and the first memory capacitance Cs, the second memory capacitance Cb, the source electrode of described driving transistors DTFT connects the drain electrode of described the first transistor T1 and the drain electrode of described third transistor T3, the drain electrode of described driving transistors DTFT connects second end of described luminescent device OLED, and the grid of described driving transistors DTFT connects the first end of described first memory capacitance Cs; The source electrode of described the first transistor T1 connects the first voltage end ELVDD, and the grid of described the first transistor T1 connects the first end of described second memory capacitance Cb;

Second end of described second memory capacitance Cb connects the incoming end VSS in reference voltage end; The source electrode of described third transistor T3 connects the grid of described driving transistors DTFT, and the drain electrode of described third transistor T3 connects the source electrode of described driving transistors DTFT, and the grid of described third transistor T3 connects the first scan signal line Scan1.

Reset subcircuit described in the present embodiment is discharged to described first memory capacitance Cs and described second memory capacitance Cb under being used for the control of the first sweep signal exported at the first scan signal line Scan1.

Reset subcircuit described in the present embodiment comprises transistor seconds T2 and the 4th transistor T4, the source electrode of described transistor seconds T2 connects the grid of described the first transistor T1, the drain electrode of described transistor seconds T2 connects the incoming end VSS in described reference voltage end, and the grid of described transistor seconds T2 connects the first scan signal line Scan1; The source electrode of described 4th transistor T4 connects second end of described first memory capacitance Cs, and the drain electrode of described 4th transistor T4 connects the incoming end VSS in described reference voltage end, and the grid of described 4th transistor T4 connects the first scan signal line Scan1.

Described charging electronic circuit comprises the 5th transistor T5 and the 6th transistor T6, the source electrode connection data voltage input end DATA of described 5th transistor T5, the drain electrode of described 5th transistor T5 connects the source electrode of described 4th transistor T4, and the grid of described 5th transistor T5 connects the second scan signal line Scan2; The grid of described 6th transistor T6 is connected the second scan signal line Scan2 with the source electrode of described 6th transistor T6 simultaneously, and the drain electrode of described 6th transistor T6 connects the source electrode of described transistor seconds T2.

Compare traditional dot structure, said structure can solve the threshold voltage shift of enhancement mode or depletion type TFT driving transistors, heterogeneity and luminescent device voltage non-uniformity and aging problem effectively.

Described image element circuit of the present invention is connected in luminous working power (belonging to prior art), and this luminous working power provides the first voltage end ELVDD and the second voltage end ELVSS for image element circuit.Described in the present embodiment, the second voltage end ELVSS generally chooses within the scope of-5V to 0V, obtains according to reality debugging.Luminescent device described in the present embodiment is organic electroluminescent LED (OLED).

Image element circuit of the present invention, can in the process that luminescent device is compensated, effectively eliminate heterogeneity that N-shaped depletion type or enhancement mode TFT driving transistors cause by self threshold voltage by compensating and to drift about the ghost phenomena caused because of threshold voltage; Avoid the problem of the active matrix light-emitting organic electroluminescence display tube brightness disproportionation caused because of the threshold voltage difference of its driving transistors between the luminescent device of different pixels unit in active matrix light-emitting organic electroluminescence display tube; In addition, the heterogeneity of the electric property that luminescent device causes due to thickness inequality when evaporation effectively can be eliminated by image element circuit of the present invention, and the difference of the drive current of each luminescent device in the active matrix light-emitting organic electroluminescence display tube caused by luminescent device heterogeneity; Improve the compensation effect of image element circuit to luminescent device, further increase the quality of active matrix light-emitting organic electroluminescence display tube.

Reference voltage end described in the present embodiment comprises multiple incoming end VSS, for connecting second end of described second memory capacitance Cb, the drain electrode of described transistor seconds T2, the drain electrode of described 4th transistor T4 and/or described second voltage end ELVSS.Described reference voltage end with thinking that above-mentioned each element provides reference potential, such as, for connecting zero line, ground wire to provide zero potential or to provide negative voltage etc.

Driving transistors described in the present embodiment is N-type TFT driving transistors; The TFT form of this N-type TFT driving transistors is enhancement mode (threshold voltage is just) or depletion type (threshold voltage is negative); Described driving transistors, the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor are field effect transistor.

Shown in Fig. 2, Fig. 3, the present invention also provides a kind of driving method realized according to the image element circuit described in above-mentioned, and described method comprises reseting stage, compensated stage and glow phase.Below in conjunction with Fig. 3 (V in figure _scan1it is the potential waveform that the first scan signal line Scan1 exports; V _scan2it is the potential waveform that the second scan signal line Scan2 exports; V _datafor the potential waveform that data voltage input end DATA exports; T1 is reseting stage; T2 is compensated stage; T3 is glow phase; ) three phases is described in detail:

1, reseting stage, described first scan signal line Scan1 exports noble potential, and described second scan signal line Scan2 exports electronegative potential; Described first scan signal line Scan1 opens described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described third transistor T3 opens described driving transistors DTFT; Described second memory capacitance Cb stored charge is discharged into the incoming end VSS in described reference voltage end by transistor seconds T2, thus closes described the first transistor T1; The first end stored charge of described first memory capacitance CS is discharged into described second voltage end ELVSS via described third transistor T3, driving transistors DTFT and luminescent device OLED; Meanwhile, the second end stored charge of described first memory capacitance Cs is discharged into the incoming end VSS in described reference voltage end by the 4th transistor T4;

When described first memory capacitance Cs and described second memory capacitance Cb electric charge discharge complete, the grid voltage of described driving transistors DTFT is V _oLED+ V _th; Wherein, V _oLEDfor the voltage of the first voltage end ELVDD of described luminescent device OLED, V _thfor the threshold voltage of described driving transistors DTFT.V described in the present invention _oLEDand V _thfor steady state value.

2, compensated stage, described second scan signal line Scan2 exports noble potential, and described first scan signal line Scan1 exports electronegative potential; Described first scan signal line Scan1 closes described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described second scan signal line Scan2 opens described 5th transistor T5 and the 6th transistor T6; Described second sweep signal Scan2 line is charged to described second memory capacitance Cb by described 6th transistor T6; Meanwhile, described data voltage input end DATA is charged to described first memory capacitance Cs by described 5th transistor T5; The first end of described first memory capacitance Cs is made to be promoted to V _data+ V _oLED+ V _th; Again because the voltage of the first end of described first memory capacitance Cs is equal to (visible see Fig. 1) with the grid voltage of described driving transistors DTFT; Therefore, the grid voltage of described driving transistors DTFT is made to be promoted to V _data+ V _oLED+ V _th; Wherein, V _datafor described data voltage, V _thfor the threshold voltage of described driving transistors DTFT.

3, glow phase, described second scan signal line Scan2 and described first scan signal line Scan1 all exports electronegative potential; Described first scan signal line Scan2 closes described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described second scan signal line Scan2 closes described 5th transistor T5 and the 6th transistor T6; Described second memory capacitance Cb is in noble potential, opens described the first transistor T1, makes described first voltage end ELVDD and described second voltage end ELVSS keep conducting; Meanwhile, the electric charge conducting driving transistors ETFT that described first memory capacitance Cs stores, drives described luminescent device OLED luminous with this.

Now, the grid voltage of described driving transistors DTFT remains V _data+ V _oLED+ V _th; In this area about the drive current formula inputing to described luminescent device OLED through described driving transistors DTFT be

$I_{\mathrm{OLED}}=\frac{1}{2}\·{\mathrm{\μ}}_n{C}_{\mathrm{OX}}\·\frac{W}{L}\·{[V_{\mathrm{DATA}},-V_{\mathrm{OLED}}-V_{\mathrm{th}}-\mathrm{ELVSS}]}^2$

Wherein, μ _nfor carrier mobility, C _oXfor the gate oxide capacitance of described first memory capacitance Cs, for the breadth length ratio of described driving transistors DTFT, V _dATA, be the grid voltage of described driving transistors DTFT, V _oLEDfor the operating voltage of described luminescent device OLED, ELVSS is described second voltage end.That is V _dATA,=V _data+ V _oLED+ V _th;

Substituted into drive current I _oLEDformula is known, makes the drive current I inputing to described luminescent device OLED through described driving transistors DTFT _oLEDfor:

$\begin{array}{c}{I}_{\mathrm{OLED}}=\frac{1}{2}\·{\mathrm{\μ}}_n{C}_{\mathrm{OX}}\·\frac{W}{L}\·{[V_{\mathrm{data}}+V_{\mathrm{OLED}}+V_{\mathrm{th}}-V_{\mathrm{OLED}}-V_{\mathrm{th}}-\mathrm{ELVSS}]}^2\\ =\frac{1}{2}\·{\mathrm{\μ}}_n{C}_{\mathrm{OX}}\·\frac{W}{L}\·{[V_{\mathrm{data}}-\mathrm{ELVSS}]}^2\end{array}.$

Known by calculating above, through the drive current I of described driving transistors DTFT _oLEDonly and V _datarelevant with ELVSS, and with the threshold voltage vt h of driving transistors DTFT and the luminous operating voltage V of luminescent device OLED _oLEDirrelevant; Therefore, also well can compensate even if Vth is less than 0, essentially eliminate the impact of threshold voltage non-uniformity, drift.Adopt the image element circuit described in the embodiment of the present invention, no matter for enhancement mode or the TFT driving transistors of depletion type, can heteropical impact of compensating threshold voltage, thus the irregularity in brightness of luminescent device can well be compensated, therefore applicability is wider.

Embodiment two:

Image element circuit in the present embodiment and driving method are the improvement on embodiment one basis, and technology contents not repeated description disclosed in embodiment one, disclosed in embodiment one, content also belongs to content disclosed in the present embodiment.

Shown in Figure 4, as a deformation technology scheme of technical scheme in embodiment one; Described image element circuit also comprises the 3rd scan signal line Scan3; Specifically: described charging electronic circuit comprises the 5th transistor T5 and the 6th transistor T6, the source electrode connection data voltage input end DATA of described 5th transistor T5, the drain electrode of described 5th transistor T5 connects the source electrode of described 4th transistor T4, and the grid of described 5th transistor T5 connects the second scan signal line Scan2; The grid of described 6th transistor T6 is connected the 3rd scan signal line Scan3 with the source electrode of described 6th transistor T6, and the drain electrode of described 6th transistor T6 connects the source electrode of described transistor seconds T2.

Adopt such design can by the described 6th transistor T6 being used for controlling described second memory capacitance Cb charging be used for described 5th transistor T5 that controlled loading data voltage and the first memory capacitance Cs charge and separate and scan; Namely the charging process of the first memory capacitance Cs originally completed at the same time and the charging process of the second memory capacitance Cb are divided into two steps to carry out; Realize the precharge first the first memory capacitance Cs being carried out to certain hour thus, then by charging in order to open the first transistor T1 to the second memory capacitance Cb, make the object that luminous working power is opened; Because the charging of memory capacitance and release need certain hour, therefore adopt such design can solve because of not enough to the first memory capacitance Cs duration of charging, the uneven insufficient problem of the compensation brought.

Shown in Fig. 5, Fig. 6, the driving method of image element circuit described in the present embodiment comprises reseting stage, compensated stage and glow phase; Wherein said compensated stage comprises again the first memory capacitance compensated stage and the second memory capacitance compensated stage.Below in conjunction with Fig. 6 (V in figure _scan1it is the potential waveform that the first scan signal line Scan1 exports; V _scan2it is the potential waveform that the second scan signal line Scan2 exports; V _scan3it is the potential waveform that the 3rd scan signal line Scan3 exports; V _datafor the potential waveform that data voltage input end DATA exports; T1 is reseting stage; T2 was the first capacitance compensation stage; T3 was the second capacitance compensation stage; T4 is glow phase; ) four-stage is described in detail:

101, reseting stage, described first scan signal line Scan1 exports noble potential, and now, described second scan signal line Scan2 and the 3rd scan signal line Scan3 all exports electronegative potential; Described first scan signal line opens described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described third transistor opens described driving transistors DTFT;

Described second memory capacitance Cb stored charge is discharged into the incoming end VSS in described reference voltage end by transistor seconds T2, thus closes described the first transistor T1; The first end stored charge of described first memory capacitance CS is discharged into described second voltage end ELVSS via described third transistor T3, driving transistors DTFT and luminescent device OLED, and the second end stored charge of described first memory capacitance Cs is discharged into the incoming end VSS in described reference voltage end by the 4th transistor T4; When described first memory capacitance Cs and described second memory capacitance Cb electric charge discharge complete, the grid voltage of described driving transistors DTFT is made to be V _oLED+ V _th; Wherein, V _oLEDfor the voltage of the first voltage end ELVDD of described luminescent device OLED, V _thfor the threshold voltage of described driving transistors DTFT.V described in the present invention _oLEDand V _thfor steady state value.

102, the first memory capacitance compensated stage, described second scan signal line Scan2 exports noble potential, and described 3rd scan signal line Scan3 and described first scan signal line Scan1 exports electronegative potential; Described first scan signal line Scan1 closes described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described second scan signal line Scan2 opens described 5th transistor T5; Described data voltage input end DATA is charged to described first memory capacitance Cs by described 5th transistor T5.

Now, described data voltage input end DATA is by data voltage V _databe loaded on second end of described first memory capacitance Cs; The first end of described first memory capacitance Cs is made to be promoted to V _data+ V _oLED+ V _th; Again because the voltage of the first end of described first memory capacitance Cs is equal to (visible see Fig. 1-7) with the grid voltage of described driving transistors DTFT; Therefore, the grid voltage of described driving transistors DTFT is made to be promoted to V _data+ V _oLED+ V _th; Wherein, V _datafor described data voltage, V _thfor the threshold voltage of described driving transistors DTFT.Now, because described 6th transistor T6 does not open, therefore described second memory capacitance Cb is not charged.

103, the second memory capacitance compensated stage, described first scan signal line Scan2 closes described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described second scan signal line Scan2 closes described 5th transistor T5, and driving transistors DTFT is held open; Described 3rd scan signal line Scan3 opens described 6th transistor T6; Described 3rd scan signal line Scan3 is charged to described second memory capacitance Cb by described 6th transistor T6.

104, glow phase, described 3rd scan signal line Scan3 exports noble potential, and described second scan signal line Scan2 and described first scan signal line Scan1 exports electronegative potential; Described first scan signal line Scan2 closes described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described second scan signal line Scan2 closes described 5th transistor T5; Described 3rd scan signal line Scan3 closes described 6th transistor T6; Described second memory capacitance Cb opens described the first transistor T1, makes described first voltage end ELVDD and described second voltage end ELVSS constant conduction; Meanwhile, the electric charge conducting driving transistors DTFT that described first memory capacitance Cs stores, drives described luminescent device OLED luminous.

Now, the grid voltage of described driving transistors DTFT remains V _data+ V _oLED+ V _th; Described driving transistors DTFT drives described luminescent device OLED.

Embodiment three:

Image element circuit in the present embodiment and driving method are the improvement on embodiment two basis, and technology contents not repeated description disclosed in embodiment two, disclosed in embodiment two, content also belongs to content disclosed in the present embodiment.

Shown in Figure 7, as a deformation technology scheme of technical scheme in embodiment one; Described reset subcircuit comprises transistor seconds T2 and the 4th transistor T4, the source electrode of described transistor seconds T2 connects the grid of described the first transistor T1, the drain electrode of described transistor seconds T2 connects the source electrode of described 4th transistor T4, and the grid of described transistor seconds T2 connects the first scan signal line Scan1; The source electrode of described 4th transistor T4 connects second end of described first memory capacitance Cs, and the drain electrode of described 4th transistor T4 connects the incoming end VSS in described reference voltage end, and the grid of described 4th transistor T4 connects the first scan signal line Scan1; Thus simplify the design of circuit, save cost.

Shown in Fig. 8, Fig. 9, the driving method of image element circuit described in the present embodiment comprises reseting stage, compensated stage and glow phase; Wherein said compensated stage comprises again the first memory capacitance compensated stage and the second memory capacitance compensated stage.Below in conjunction with Fig. 9 (V in figure _scan1it is the potential waveform that the first scan signal line Scan1 exports; V _scan2it is the potential waveform that the second scan signal line Scan2 exports; V _scan3it is the potential waveform that the 3rd scan signal line Scan3 exports; V _datafor the potential waveform that data voltage input end DATA exports; T1 is reseting stage; T2 was the first capacitance compensation stage; T3 was the second capacitance compensation stage; T4 is glow phase; ) four-stage is described in detail:

201, reseting stage, described first scan signal line Scan1 exports noble potential, and now, described second scan signal line Scan2 and the 3rd scan signal line Scan3 all exports electronegative potential; Described first scan signal line Scan1 opens described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described third transistor opens described driving transistors DTFT;

The first end stored charge of described second memory capacitance Cb to be discharged into the incoming end VSS in described reference voltage end via described 4th transistor T4 by described transistor seconds T2, the electric charge of second end of described second memory capacitance Cb is also discharged into the incoming end VSS in described reference voltage end, thus closes described the first transistor T1; The first end stored charge of described first memory capacitance CS is discharged into described second voltage end ELVSS via described third transistor T3, driving transistors DTFT and luminescent device OLED, and the second end stored charge of described first memory capacitance Cs is discharged into the incoming end VSS in described reference voltage end by the 4th transistor T4; When described first memory capacitance Cs and described second memory capacitance Cb electric charge discharge complete, the grid voltage of described driving transistors DTFT is made to be V _oLED+ V _th; Wherein, V _oLEDfor the voltage of the first voltage end ELVDD of described luminescent device OLED, V _thfor the threshold voltage of described driving transistors DTFT.V described in the present invention _oLEDand V _thfor steady state value.

202, the first memory capacitance compensated stage, described second scan signal line Scan2 exports noble potential, and described 3rd scan signal line Scan3 and described first scan signal line Scan1 exports electronegative potential; Described first scan signal line Scan1 closes described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described second scan signal line Scan2 opens described 5th transistor T5; Described data voltage input end DATA is charged to described first memory capacitance Cs by described 5th transistor T5.

Now, described data voltage input end DATA is by data voltage V _databe loaded on second end of described first memory capacitance Cs; The first end of described first memory capacitance Cs is made to be promoted to V _data+ V _oLED+ V _th; Again because the voltage of the first end of described first memory capacitance Cs is equal to (visible see Fig. 1-7) with the grid voltage of described driving transistors DTFT; Therefore, the grid voltage of described driving transistors DTFT is made to be promoted to V _data+ V _oLED+ V _th; Wherein, V _datafor described data voltage, V _thfor the threshold voltage of described driving transistors DTFT.Now, because described 6th transistor T6 does not open, therefore described second memory capacitance Cb is not charged.

203, the second memory capacitance compensated stage, described first scan signal line Scan2 closes described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described second scan signal line Scan2 closes described 5th transistor T5, and driving transistors DTFT is held open; Described 3rd scan signal line Scan3 opens described 6th transistor T6; Described 3rd scan signal line Scan3 is charged to described second memory capacitance Cb by described 6th transistor T6.

204, glow phase, described 3rd scan signal line Scan3 exports noble potential, and described second scan signal line Scan2 and described first scan signal line Scan1 exports electronegative potential; Described first scan signal line Scan2 closes described transistor seconds T2, third transistor T3 and the 4th transistor T4; Described second scan signal line Scan2 closes described 5th transistor T5; Described 3rd scan signal line Scan3 closes described 6th transistor T6; Described second memory capacitance Cb opens described the first transistor T1, makes described first voltage end ELVDD and described second voltage end ELVSS constant conduction; Meanwhile, the electric charge conducting driving transistors DTFT that described first memory capacitance Cs stores, drives described luminescent device OLED luminous.

Now, the grid voltage of described driving transistors DTFT remains V _data+ V _oLED+ V _th; Described driving transistors DTFT drives described luminescent device OLED.

It should be noted that, the source electrode of all crystals pipe in the embodiment of the present invention and drain electrode do not distinguish, and such as, the source electrode of driving transistors also can be named the drain electrode of driving transistors, and correspondingly, now the drain electrode of driving transistors is the source electrode of driving transistors.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.

Claims (9)

1. an image element circuit, is characterized in that, comprises reset subcircuit, charging electronic circuit, drive sub-circuits and luminescent device, wherein,

The first end of described luminescent device connects the second voltage end;

Described drive sub-circuits comprises driving transistors, the first transistor, third transistor and the first memory capacitance, the second memory capacitance, the source electrode of described driving transistors connects the drain electrode of described the first transistor and the drain electrode of described third transistor, the drain electrode of described driving transistors connects the second end of described luminescent device, and the grid of described driving transistors connects the first end of described first memory capacitance; The source electrode of described the first transistor connects the first voltage end, and the grid of described the first transistor connects the first end of described second memory capacitance; Second end of described second memory capacitance connects reference voltage end; The source electrode of described third transistor connects the grid of described driving transistors, and the drain electrode of described third transistor connects the source electrode of described driving transistors, and the grid of described third transistor connects the first scan signal line;

Described reset subcircuit is discharged to described first memory capacitance and described second memory capacitance under being used for the control of the first sweep signal exported at the first scan signal line;

Described charging electronic circuit comprises the 5th transistor and the 6th transistor, the source electrode connection data voltage input end of described 5th transistor, the drain electrode of described 5th transistor connects the source electrode of described 4th transistor, and the grid of described 5th transistor connects the second scan signal line; The grid of described 6th transistor is connected the 3rd scan signal line with the source electrode of described 6th transistor, and the drain electrode of described 6th transistor connects the source electrode of described transistor seconds.

2. image element circuit according to claim 1, it is characterized in that, described reset subcircuit comprises transistor seconds and the 4th transistor, the source electrode of described transistor seconds connects the grid of described the first transistor, the drain electrode of described transistor seconds connects described reference voltage end, and the grid of described transistor seconds connects the first scan signal line; The source electrode of described 4th transistor connects the second end of described first memory capacitance, and the drain electrode of described 4th transistor connects described reference voltage end, and the grid of described 4th transistor connects the first scan signal line.

3. image element circuit according to claim 1, it is characterized in that, described reset subcircuit comprises transistor seconds and the 4th transistor, the source electrode of described transistor seconds connects the grid of described the first transistor, the drain electrode of described transistor seconds connects the source electrode of described 4th transistor, and the grid of described transistor seconds connects the first scan signal line; The source electrode of described 4th transistor connects the second end of described first memory capacitance, and the drain electrode of described 4th transistor connects described reference voltage end, and the grid of described 4th transistor connects the first scan signal line.

4. image element circuit according to claim 1, is characterized in that, the grid of described 5th transistor, the grid of described 6th transistor are connected the second scan signal line with the source electrode of described 6th transistor simultaneously.

5. image element circuit according to claim 1, is characterized in that, described luminescent device is organic electroluminescent LED.

6., according to the arbitrary described image element circuit of claim 1-5, it is characterized in that, described driving transistors, the first transistor, transistor seconds, third transistor, the 4th transistor, the 5th transistor, the 6th transistor are n type field effect transistor.

7. a driving method for image element circuit according to claim 1, is characterized in that, described method comprises:

Reseting stage, described first scan signal line opens described transistor seconds, third transistor and the 4th transistor, described second memory capacitance stored charge is discharged by transistor seconds, the first end stored charge of described first memory capacitance is via the release of described third transistor, driving transistors and luminescent device, and the second end stored charge of described first memory capacitance is by the 4th transistor release;

Compensated stage, described first scan signal line closes described transistor seconds, third transistor and the 4th transistor, described second scan signal line opens described 5th transistor, described 3rd scan signal line opens described 6th transistor, and described 3rd scan signal line is charged to described second memory capacitance by described 6th transistor; Described data voltage input end is charged to described first memory capacitance by described 5th transistor;

Glow phase, described first scan signal line closes described transistor seconds, third transistor and the 4th transistor, described second scan signal line closes described 5th transistor and the 6th transistor, described second memory capacitance opens described the first transistor, the electric charge that described first memory capacitance stores opens described driving transistors, drives described luminescent device luminous.

8. the driving method of image element circuit according to claim 7, is characterized in that, described second scan signal line controls described 5th transistor simultaneously and described 6th transistor is opened or closed.

9. the driving method of image element circuit according to claim 7, is characterized in that, also comprises:

Reseting stage, described first scan signal line opens described transistor seconds, third transistor and the 4th transistor; Described third transistor opens described driving transistors; The first end stored charge of described second memory capacitance is discharged via described 4th transistor by described transistor seconds, thus closes described the first transistor; The first end stored charge of described first memory capacitance is via the release of described third transistor, driving transistors and luminescent device, and the second end stored charge of described first memory capacitance is by the 4th transistor release.