CN1045320A - Preliminary treatment and demodulation M unit and the method and apparatus that moves keying (PSK) signal - Google Patents
Preliminary treatment and demodulation M unit and the method and apparatus that moves keying (PSK) signal Download PDFInfo
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Abstract
A kind of method and apparatus that is used for preliminary treatment and demodulation M unit psk signal.This method comprises, produces the harmonic wave of the source signal of modulation, then a harmonic signal of demodulation selection.This device comprises, source signal is divided into the phase splitter of two or three paths with pre-selection phase relationship, and one of phase place is delayed a specified bit period; One or two frequency mixers or multiplier, each frequency mixer are the phase component that postpones and remaining quadrature mixer, and the combiner that mixed frequency signal makes up in a predefined manner, the comparison combination signal is to provide at least one two level comparator of numeral output; Also can comprise the Digital Logical Circuits that numeral output is become numerical digit stream.
Description
The present invention relates to Digital Signal Processing, relate in particular to the technology of the big class digital phase modulation of demodulation signal and be used for the apparatus and method of the big class digital phase-shift keying of demodulation (digital phase shift keyed) modulation signal, wherein, phase change is limited to the adjacent phase state.
Digital phase-shift keying signal (psk signal) is widely used in communication.This signal produces by the phase place Discrete Change of periodic waveform.Phase place is according to changing as the serial digital data stream of control signal.The present invention is particularly useful to wherein modulating the psk signal that is limited to phse conversion between the adjacent phase state.
The PSK modulation scheme of prior art needs the proportional demodulator of complexity of its complexity and modulation signal.For example, a binary psk signal requires a fairly simple comparatively speaking demodulator, and this demodulator is made of a single channel, wherein, a multiplier that uses with this machine phase reference is arranged.And Quadrature Phase Shift Keying (quadrature phase shift keyed) (QPSK) signal need in the past two phase references and two multipliers (multi plier).When phase state increases, in order to distinguish different phase states, the also corresponding increase of quantity of phase reference, multiplier and the comparator that needs.Such circuit is complicated and the possibility cost is very high, but in the past, for enough signal to noise ratio surpluses are provided, this is essential.When number of phases increased, the complexity that is used for the synchronous circuit of the phase reference that produces with this machine also increased thereupon.The benchmark that this this machine produces needs the regular hour just can become synchronously, and it makes first's suitably demodulation between the pulse mode transmission period of information.Such circuit be complicated and also opportunity cost very high, but in the past, to given bit error rate, for for required signal to noise ratio provides enough surpluses, this is essential.
Fig. 1 represents to be applicable to bipolar phase shift keying (BPSK) demodulator 10 of the typical prior art of demodulated pulse Mode B PSK transmission.Referring to Fig. 1.Demodulator 10 among the figure is used one provides first phase component
1With second phase component
2The phase splitter 12 of output, wherein, second phase component provides the normal delay of a bit period (bit period) by a short delay line 14, first phase component and second phase component together in frequency mixer or multiplier 16 by mixing to produce a base-band bit-stream (base band bit stream) that is added to low pass filter 18.The output of low pass filter 18 is added to the comparator 20 of one or two level, and it is used for the stream of generation " 1 " and " 0 " and exports as numeral.
The Quadrature Phase Shift Keying modulation needs more complicated demodulator.In textbook " digital communication-satellite/terrestrial station engineering " (Ka Miluofei Hull (Kamilo Feher) work, Prentice-Hall (Prentice-Hall) publishing house publishes) 170-171 page or leaf, provide an example.A differential offset (differential offset) qpsk demodulator and differential QPSK demodulator have been narrated there.In this demodulator, the output of homophase (I) output and phase difference 90 ° (Q) before being reassembled into serial datum stream, is converted into digital level dividually.This priori that needs bit clock phase place (bit clock phase) that reconfigures.This demodulator is only applicable to the QPSK signal.Believe the simple demodulator that in my innocent life can be used for than high order M unit (M-ary) psk signal.
What people needed is a kind of simple demodulator, and it can not be to be used for M unit psk signal under the main situation about considering in signal to noise ratio.In addition, people also need the simple demodulator of a kind of QPSK of being used for, it can eliminate staggered (reinterleaving) signal of overline fuzzy, can not be to be used for M unit psk signal when mainly considering in signal to noise ratio, and can the time-delay with minimum provide valid data from transmission beginning back.
The invention provides a kind of method that its modulation of demodulation is limited to the M unit psk signal of phase transition between contiguous phase state that is used for.The method is included in the preceding harmonic wave that produces modulated source signal of demodulation, expands the phase difference between the adjacent phase state thus; The harmonic signal of a selection of demodulation then is just as it is one simple two or four phase place psk signals.The loss of the signal to noise ratio surplus that causes is thus compensated by the corresponding simplification and the cost savings of demodulator circuit.But the spectrum efficiency (Spectral efficiency) of complicated psk signal is retained.
The expansion maximum of phase difference is no more than 180 ° to avoid by bluring that phrase overlap causes.
According to the present invention, a kind of method and apparatus is provided for the M unit psk signal that its modulation of demodulation is limited to phase transition between contiguous phase state.This method is moved in such demodulator: it comprises source signal is divided into the phase splitter that each phasetophase has three paths of predetermined phase relation that one of phase place is delayed a specified bit period; The component that a pair of frequency mixer or multiplier, each frequency mixer receive a phase delay also receives one of other two phase components separately as an input as second input.Offered combiner (combiner) by the signal of mixing by frequency mixer, it adds and subtracts this composite signal and arrive N intermediate output signal to produce 1 according to the desired input signal type.Intermediate output signal is coupled to corresponding two level comparators, and each comparator receives and flows with the single numerical digit that this numeral output is constituted " 1 " and " 0 " with the numeral output that produces numeral output Digital Logical Circuits and respond each comparator in response to separately intermediate output signal.The loss of caused surplus and signal to noise ratio is compensated by the corresponding simplification of demodulator circuit and the saving of cost.But the spectrum efficiency of complicated M unit psk signal still keeps.
The invention provides a kind of method and apparatus that its modulation of demodulation is limited to the M unit psk signal of the phase transition between contiguous phase state that is used for.This method is moved in such demodulator: it comprises source signal only is divided into the phase splitter that has two paths of predetermined phase relation at phasetophase that one of phase place is delayed a specified bit period; Single frequency mixer or multiplier, its receives the phase component that postpones and another phase component is received as second input as an input.Output signal is coupled at least one two level comparator, and each comparator produces a numeral output.Digital Logical Circuits responds the numeral output of each comparator the single numerical digit that this numeral output constitutes " 1 " and " 0 " is flowed.Caused surplus and snr loss are compensated by the corresponding simplification and the cost savings of demodulator circuit.But the spectrum efficiency of complicated M unit psk signal still keeps.
Read being described in detail of being done below with reference to the accompanying drawings, the present invention can be better understood.
Fig. 1 is the block diagram that is applicable to the BPSK demodulator of prior art.
Fig. 2 is used for the M phase modulated signal is converted to the M/N phase modulated signal as preliminary treatment, passes through the block diagram of the method for M/N phase demodulator demodulation then.
Fig. 3 is the block diagram with differential bipolar phase shift keying (BPSK) demodulator of PM signal PM that interrelates according to conversion method of the present invention.
Fig. 4 is the block diagram according to the general M PSK of unit demodulator of the present invention.
Fig. 5 is the block diagram of the part of first concrete DOQPSK demodulator.
Fig. 6 is the block diagram of the part of second concrete DOMPSK demodulator.
Fig. 7 is the block diagram according to the general M PSK of unit demodulator of the present invention.
Fig. 8 is the block diagram of the part of first concrete DOQPSK demodulator.
Fig. 9 is the block diagram of the part of second concrete DOMPSK demodulator.
Figure 10 is used to decode the Digital Logical Circuits schematic diagram of output of comparator of Fig. 6 and Fig. 9 example.
Narrate embodiments of the invention with reference to the accompanying drawings.
Referring to Fig. 2.There is shown explanation and change the block diagram of the method for psk signal according to the present invention.The input digit modulation signal that differential phase that has a part of 360 ° changes is defeated by harmonic oscillator 112.This harmonic oscillator 112 for example is a multiplier, and it for example multiplies each other input signal with self, to obtain the frequency multiplication output signal that its phase component equals the input phase twice, so that phase state is input signal half.The frequency of harmonic oscillator 112 can be input signal first-harmonic 2,3,4 or N doubly, its expansion maximum that is limited in the phase difference between gained adjacent phase state can not be above 180 °.
Referring to Fig. 3.It shows a suitable difference bpsk signal demodulator 116.Such demodulator mainly is applicable to demodulation bipolar (N=2) psk signal.From band pass filter 114(Fig. 2) input modulating signal put on phase splitter 118, it is divided into input signal and has equal phase θ
1And θ
2Two paths.θ
1Phase signal directly offers frequency mixer, and it for example is a multiplier 120.The second phase signal θ
2 Offer delay line 122, its time-delay equals the bit period that flowed by demodulated data.The output of delay line 122 offer multiplier 120 second inputs with input signal θ
1Mixing.Its output signal be these two phase signals and with poor.This and offer low pass filter 126 with difference signal by output line 124.This low pass filter 126 has the characteristic that only allows difference frequency signal pass through.Therefore, have only difference frequency signal to be added on the comparator 130 by transmission line 128.Comparator 130 is accepted two analog signal levels, produces the digital output signal of two level of desirable bpsk signal.Be appreciated that by treatment circuit in fact this bpsk signal is represented is not this input signal of bpsk signal.
But should be appreciated that input signal still is limited to its modulation and is limited to that class signal that carries out phase transition between the adjacent phase state.
Any suitable harmonic oscillator can use.Except that multiplier, the non-linear element that has suitable filter also can be used as frequency multiplier, and full-wave rectifier can be used for the frequency multiplication of the frequency that produced, and the combination of any above-mentioned technology can be used to produce the harmonic wave of frequency.Another kind of possible frequency harmonics generator is a phase-locked loop, the frequency divider that it is N that phase-locked loop has a divide ratio, and this frequency divider is connected on the output of voltage controlled oscillator, and its output feeds back to phase detectors.Back one method is particularly advantageous, and favourable part is that it only produces the single harmonic wave of hope frequency.
Referring to Fig. 4.It shows the specific embodiment of a demodulator 230.Demodulator 230 has a phase splitter 232 that produces three outputs, signal delay line 234, first frequency mixer 236, second frequency mixer 238 and according to combiner 240 of the present invention.In addition, each specific embodiment of the present invention has the Several combination device output channel through selecting, and its signal is combined and analyzes the numeral output of wishing to take out.Concrete have first comparator, 242, the second comparators 244 and Digital Logical Circuits 246 as shown in Figure 4, will describe below.
Phase splitter has a single input end of analog signal 248 that is used to receive modulation signal, phase splitter is divided into three paths that predetermined phase relation is arranged at phasetophase to source signal, delayed line 234 of one of phase place or the device image charge coupled apparatus (CCD) that the is equal to bit period of being delayed time.In this one-level of demodulator, entire spectrum should be saved so that signal can be by demodulation.A pair of frequency mixer 236 and 238 can be a multiplier, the phase component that in the frequency mixer 236 and 238 each all is delayed by incoming line 250 acceptance, simultaneously, each frequency mixer 236 and 238 is also separately by second incoming line 252 and 254 another phase components of accepting from phase splitter 232.For example, the output of the phase place of phase splitter 232 is θ
1Be 0 °, θ
2Be 45 ° and θ
3It is 90 °.The time-delay of delay line 234 is added on 45 ° of phase lines.Specified delay is that one and phase delay are 360 ° multiples, and frequency is the incoming carrier frequency of input port 248.
Two composite signals on the holding wire 256 and 258 offer combiner 240 by frequency mixer 236 and 238.Combiner 240 is as described below at desirable demodulation form customization.Combiner 240 signal according to the class shape of desired input signal with the power addition selected or subtract each other so that for example for the combiner of two outputs, on holding wire 260 and 262, produce from 1 to N intermediate output signal usefulness for two output combinations.Filtered from the intermediate output signal of the combiner 240 that contains low pass filter with the additional high fdrequency component of filtering, be coupled to corresponding two level comparators 242 and 244 by holding wire 260 and 262 respectively then, each comparator produces the output of digital binary level respectively and offers Digital Logical Circuits 246 on output line 264 and 266.Digital Logical Circuits 246 is in response to the numeral output of each comparator 242 and 244.This numeral output transform is become the single numerical digit stream of " 1 " and " 0 " on output line 268.
Following Example for understand work of the present invention and in specific embodiment the function of each several part be useful.Referring to Fig. 5.First example is wherein to change differential offset Quadrature Phase Shift Keying (DOQPSK) (the Differential Offset Quadrature Phase Shift Keyed) modulation of only carrying out between the adjacent phase state.Consider that one has modulation phase shift and is+90 °, 0 ° and-90 ° and 248 input signals that offer phase splitter 232 through the input port.
Change output output output
A) 0 ° to 90 °-0.707+0.707 0.00
B) 0 ° is arrived-90 °+0.707-0.707 0.00
C) 0 ° to 0 °+0.707-0.707 1.414/2
Fig. 5 referring to the expression object lesson.The output of combiner 240 offers single comparator 242, because in the situation of DOQPSK, more comparator is unnecessary.The output of the logic level of comparator 242 is 0 a) to situation in above-mentioned example, to b) be 0, to c) be 1.
By as seen above-mentioned, for the situation of DOQPSK, with the power that equates the output addition and use at 0.3535 volt (0.707 volt 1/2, the output of combiner high voltage) strict comparator of exporting that limits of decision level and can rebuild initial data.Digital Logical Circuits 246 is unwanted for the single comparator of decoding as the output of comparator 242.Thereby the output of comparator 242 is desirable digital data streams.
The single output of combiner 240 can be coupled to the input (usually being shown in Fig. 4) of the dual input comparator 242,244 of two standards.In such configuration, the differential offset M of more complicated unit phase shift keying (DOMPSK) (Differential Offset Mary Phase Shift Keyed) modulated energy is analyzed with simple circuit.An example is as follows:
Referring to Fig. 6.Second example is skew M unit's phase shift keying (OMPSK) modulation of wherein only changing between the adjacent phase state.Consider one and have modulation phase shift+△ °, 0 ° ,-△ ° and through the input port 248 input signals that offer phase splitter 232.Be below at differential phase shift less than 180 ° but be not the transfer characteristic of the unit voltage of accurate 90 ° phase splitter output:
The phase mixer 1 voltage frequency mixer 2 voltage combiner voltages of input
Change output output output
A) 0 ° to ° (1/2) SIN+2 △ ° of+△ ° SIN+2 △ ° SIN0
B) 0 ° to-△ ° SIN0 ° SIN-2 △ ° (1/2) SIN-2 △ °
C) 0 ° to 0 ° SIN+ △ ° of SIN-△ ° 0
By as seen above-mentioned, situation to OMPSK, if use suitable Digital Logical Circuits 246, output to wait the power addition and use at (1/2) SIN(+2 △ °) volt 1/2 and (1/2) SIN(-2 △ °) comparator of 1/2 the strict restriction output of decision level of volt, this device will reconstitute initial data.For two comparators for example comparator 242 and 244 the output of decoding, simple numerical logical circuit 246 needs.
Referring to Fig. 7.There is shown specific embodiment according to demodulator 430 of the present invention.Demodulator 430 has phase splitter 412, single delay line 414, single frequency mixer 416 and the low pass filter 418 that produces two outputs.According to the present invention, each specific embodiment of the present invention all has from the selected some output channels 460,462 of the warp of low pass filter 418, and the signal of low pass filter is coupled to two level comparators.As shown in Figure 7, one first comparator 442, second comparator 444 and Digital Logical Circuits 446 are arranged, narrate below.
For function of understanding work of the present invention and respectively forming in this specific embodiment, a following example is useful.See also Fig. 8.First example is wherein to change differential offset Quadrature Phase Shift Keying (DOQPSK) modulation of only carrying out between the adjacent phase state.Consider one to have+90 °, 0 ° ,-90 ° modulation phase shift and 448 input signals that put on phase splitter 412 through the input port.
The output output of phase change voltage
A) 0 ° to 90 ° 0.0 0
B) 0 ° to-90 ° 0.0 0
C) 0 ° to 0 ° 1.0 1
Referring to Fig. 8 that object lesson is shown.Among the figure, the output of low pass filter 418 directly puts on single comparator 442, because under the situation of DOQPSK, more comparator is unnecessary.In above-mentioned example, the output of the logic level of comparator 442 is shown in row on the right of table.By as seen above-mentioned,, use comparator will reconstitute initial data in the strict restriction output of 0.5 volt decision level for the situation of DOQPSK.For the single comparator of decoding, for example output of comparator 442, Digital Logical Circuits 446 is unwanted.Thereby the output of comparator 442 is exactly desirable digital data stream.
Dual input comparator 442,444(that the single output of low pass filter 418 can be coupled to two standards see Fig. 7), in such configuration, use simple circuit, just can analyze complicated differential offset M unit's phase shift keying (DOMPSK) modulation.An example is as follows:
Referring to Fig. 9.Second example is skew M unit's phase shift keying (OMPSK) modulation of wherein changing only to carry out between contiguous phase state.Consider one have modulation phase shift for+△ °, 0 ° and-△ ° and 448 input signals that put on phase splitter 412 through the input port.Less than 180 ° but be not unit voltage on the output of accurate 90 ° phase splitter, its transfer characteristic is as follows for differential phase shift:
Input 448 frequency mixers 416 frequency mixers 416 logic levels
The voltage output output of voltage output of phase change
（△＝45°） （△＝45°）
A) 0 ° to+△ ° Cos90+ △ ° Cos135 ° 1
B) 0 ° to-△ ° Cos90-△ ° Cos45 ° 1
C) 0 ° to 0 ° Cos90 ° of 0 Cos90 ° 0
The single output of low pass filter 418 by putting on first comparator 442 on holding wire 460 and 462 respectively positive benchmark input end and the negative benchmark input end of second comparator 444, they equate with amplitude independently but opposite polarity different voltage reference 461,463 is a benchmark.Like this, in above-mentioned example, the amplitude that △ is depended in comparator 442 and 444 output with determine a), b) and the c) binary logic level during situation.An object lesson is as implied above.In above-mentioned example, the output of each comparator 442 and the output of 444 logic level and last logic level is provided by following table:
The output of situation comparator 442 comparators 444 logics
a） 1 0 1
b） 0 1 1
c） 0 0 0
By as seen above-mentioned, situation for OMPSK, with wait power the output addition and use at (1/2) Cos(+90+ △ °) volt and (1/2) Cos(90-△ °) comparator of strict restriction output during the decision level of volt, if use suitable Digital Logical Circuits 446, this device can be rebuild initial data.For two comparators of decoding, as the output of comparator 442 and 444, simple numerical logical circuit 446 needs.
See also Figure 10.There is shown a Digital Logical Circuits 246 and 446 circuit that use that are suitable among the present invention.Digital Logical Circuits 246 and 446 only be two inputs or the door.In a more general case, Digital Logical Circuits 246 and 446 can design to such an extent that the signal decoding of a plurality of comparators can be become individual digit numerical digit stream.In such configuration, just can demodulation modulate than the skew M unit phase shift keying of complicated difference and non-difference with simple circuit.
The present invention narrates with reference to specific embodiment, and those of ordinary skill in the art can propose other all embodiment fully, because this is conspicuous.For example, method of the present invention can be applied in the particular case, and in this case, phase transition is limited to respect to the initial phase state and is+a plurality of selected phase state between 90 ° and-90 °.In such particular case, by comparator bank 242,244(Fig. 4) or 442,444(Fig. 7) by relatively discerning each phase state, the number of each comparator 442,444 lacks 1 than possible phase state number.Therefore, except being proposed in the claim of back, the present invention does not intend being defined.
Claims (20)
1, a kind ofly be used for demodulation and wherein modulate the device (230,430) that is limited to M unit phase shift keying (MPSK) signal of between the adjacent phase state, changing, it is characterized in that described device comprises:
Be used to produce the harmonic wave of described mpsk signal so that obtain between contiguous phase state, to have the device (112) of N subharmonic mpsk signal of the difference of expansion;
Selection is used for the device (114) of the described N subharmonic mpsk signal of demodulation;
Be used for source signal is divided into two-way at least, and between first phase component and second phase component, have the phase splitter device (232,412) of predetermined phase relation at least;
Be received from the deferred mount (234,414) of described second phase component of described phase splitter (232,412) output, described second phase component is at described deferred mount (234,414) output is delayed a specified bit period, as the phase component that postpones;
The phase component of at least one described delay receives as an input and another phase component is imported the frequency mixer (236,238,416) that receives to produce at least one mixed frequency signal as second; With
At least one two level comparator device (242,442,444), each described two level comparator device receive described mixed frequency signal through weighting to produce digital output signal.
2, a kind ofly be used for the method that M unit phase shift keying (MPSK) signal that is limited to phase transition between the adjacent phase state is wherein modulated in demodulation, it is characterized in that described method comprises the steps:
The harmonic wave that produces (112) described mpsk signal has the N subharmonic mpsk signal of the phase difference of expansion between the adjacent phase state with acquisition;
Select (114) to be used for the described N subharmonic mpsk signal of demodulation; With
The described N subharmonic mpsk signal of demodulation (116) is as phase shift keying (PSK) signal than low value (lowervalue) M.
3, method as claimed in claim 2 is characterized in that, described harmonic wave produces that step (112) produces is that difference between adjacent phase is no more than described the N time mpsk signal of 180 °.
4, method as claimed in claim 3 is characterized in that, described harmonic wave produces step (112) and comprises described mpsk signal and self are multiplied each other.
5, method as claimed in claim 4 is characterized in that, described selection step (114) comprises with passband filtering selects described N subharmonic.
6, method as claimed in claim 3, it is characterized in that, described demodulation step (116) comprises bipolar phase shift keying demodulation is put on described N subharmonic mpsk signal that wherein, described N subharmonic mpsk signal has two phase states definitely.
7, a kind ofly be used for the method that M unit phase shift keying (MPSK) signal that is limited to phase transition between the adjacent phase state is wherein modulated in demodulation, it is characterized in that described method comprises the steps:
Source signal (248) is divided at the first phase component (θ
1), the second phase component (θ
2) and third phase position component (θ
3) between have predetermined phase relation three paths (250,252,254);
The described second phase component (θ
2) a specified bit period of delay, the described phase component (θ that is delayed
2) with respect to the described first phase component (θ
1) and described third phase position component (θ
3) all have phase difference to produce the phase component (250) that postpones;
The described first phase component (θ of the phase component of described delay (250)
1) mixing to be to produce first mixed frequency signal (256);
Phase component of described delay (250) and described third phase position component (θ
3) mixing to be to produce second mixed frequency signal (258);
Described first mixed frequency signal (256) and described second mixed frequency signal (258) combination, produce mixed frequency signal (260,262) by the weighting of the input signal form of expecting; With
In at least one comparator (242) device, described weighting mixed frequency signal (260,262) and previously selected decision gate limit value are compared, produce digital output signal (264).
8, method as claimed in claim 7 is characterized in that, a plurality of two level comparator devices (242,244) are provided, and this method further comprises:
Discern the unlike signal level of described weighting mixed frequency signal (260,262); With
Analyze the unlike signal level of described two level comparator devices (242,244),, produce described digital output signal (264) so that make up the output of described two level comparator devices.
9, method as claimed in claim 8 is characterized in that, just provide two two level comparator devices (242,244) and described Digital Logical Circuits device (246) comprise one two input or the door.
10, method as claimed in claim 7 is characterized in that, phase change is limited to the phase state with respect to the selection of original phase state between+90 ° and-90 °; And described comparison step comprises by each comparator device (242,244) discerns each phase state, and described each comparator lacks 1 than possible phase state number.
11, a kind ofly be used for the device (230) that the M unit phase-shift keying modulating signal (248) that is limited to phase transition between the adjacent phase state is wherein modulated in demodulation, it is characterized in that described device comprises:
Be used for source signal is divided into the phase splitter device (232) that has three paths of predetermined phase relation between first phase component, second phase component and third phase position component;
Reception is by the deferred mount (234) of described second phase component of described phase splitter (232) output, described second phase component is delayed a specified bit period as the phase component that postpones at the output of described deferred mount (234), has phase difference between described phase component that is delayed and described first phase component and the described third phase position component;
First frequency mixer (236);
Second frequency mixer (238);
The phase component of each described delay of described first frequency mixer (236) and described second frequency mixer (238) receives as an input, and described first frequency mixer (236) receives described first phase component as second input, to produce first mixed frequency signal, described second frequency mixer (238) receives described third phase position component as second input, produces second mixed frequency signal;
Receive described first mixed frequency signal and described second mixed frequency signal, described first mixed frequency signal of combination and described second mixed frequency signal to produce the device (240) of weighted blend signal according to the input signal types of expectation;
At least one two level comparator device (242), described each two level comparator device receive the mixed signal of described weighting to produce digital output signal.
12, device as claimed in claim 11, it is characterized in that, the unlike signal level that provides a plurality of two level comparator devices (242,244) to be used to discern described weighted blend signal, this demodulating equipment comprise that further the output that receives described two level comparator devices (242,244) is so that make up the Digital Logical Circuits device (246) that the output of described two level comparator devices (242,244) produces described digital output signal.
13, device as claimed in claim 12 is characterized in that, just provide two two level comparator devices (242,244) and described Digital Logical Circuits device (246) comprise one two input or the door (246).
14, a kind ofly be used for the method that M unit phase shift keying (MPSK) signal that is limited to the phase transition between the adjacent phase state is wherein modulated in demodulation, it is characterized in that described method comprises the steps:
Source signal (448) is divided at the first phase component (θ
1) and the second phase component (θ
2) between have two paths (452,450) of predetermined phase relation;
The described second phase component (θ
2) postpone a specified bit period to produce the phase component of a delay;
Make the phase component and the described first phase component (θ of this delay
1) mix to produce mixed frequency signal (456);
Select described mixed frequency signal (456) to produce filtering signal (460,462) with low-pass filtering; With
In at least one comparator device (442,444), described filtering signal (460,462) and the decision gate limit value of being scheduled to are compared, to produce digital output signal (464,466).
15, method as claimed in claim 14 is characterized in that, a plurality of two level comparator devices (442,444) are provided, and this method further comprises:
Discern the unlike signal level of described weighted blend signal (460,462); With
Analyze the unlike signal level of described two level comparator devices (442,444),, produce described digital output signal (464,466) so that make up the output of described two level comparator devices (442,444).
16, method as claimed in claim 15 is characterized in that, two two level comparator devices just are provided, and described Digital Logical Circuits device (446) comprise one two input or the door.
17, method as claimed in claim 14, it is characterized in that, phase change is limited to respect to the initial phase state and is the predetermined phase state between+90 ° and-90 °, and, described comparison step comprises, discern each phase state by each comparator device (442,444), the quantity of described each comparator (442,444) lacks 1 than possible phase state number.
18, a kind ofly be used for the device (430) that the M unit phase-shift keying modulating signal (448) that is limited to the phase transition between the adjacent phase state is wherein modulated in demodulation, it is characterized in that this device comprises:
Be used for source signal is divided into the phase splitter device (412) of two paths that between first phase component and second phase component, have predetermined phase relation;
Reception is by the deferred mount (414) of described second phase component of described phase splitter (412) output, and described second phase component is delayed a specified bit period at the output of described deferred mount (414), as the phase component that postpones;
The phase component that postpones received as an input and described first phase component as second input receive, with the frequency mixer (416) of generation mixed frequency signal;
Receive described mixed frequency signal, be used to produce the low-pass filter device (418) of filtering signal; With
At least one two level comparator device (442,444), each described two level comparator device (442,444) receive described filtering signal to produce digital output signal.
19, device as claimed in claim 18 is characterized in that, provides a plurality of two level comparator devices (442,444) to be used to discern the unlike signal level of described weighting mixed frequency signal; Described demodulating equipment further comprises, receives the output of described two level comparator devices (442,444) so that make up the output of described two level comparator devices (442,444), the Digital Logical Circuits device (446) of the described digital output signal of generation.
20, device as claimed in claim 19 is characterized in that, two two level comparator devices (442,444) just are provided, and described Digital Logical Circuits device (446) comprise two inputs or the door.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US317155 | 1989-02-28 | ||
| US317211 | 1989-02-28 | ||
| US317167 | 1989-02-28 | ||
| US07/317,211 US4881246A (en) | 1989-02-28 | 1989-02-28 | Method and apparatus for demodulating a class of M-ary phase shift keyed (PSK) signals |
| US07/317,167 US4989220A (en) | 1989-02-28 | 1989-02-28 | Method and apparatus for demodulating a class of M-ary phase shift keyed (PSK) signals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1045320A true CN1045320A (en) | 1990-09-12 |
| CN1022787C CN1022787C (en) | 1993-11-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 90101016 Expired - Fee Related CN1022787C (en) | 1989-02-28 | 1990-02-22 | Method and apparatus for preprocessing and demodulating m-ary phase shift K eyed (psk) signals |
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| Country | Link |
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| CN (1) | CN1022787C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101316158B (en) * | 2007-05-29 | 2010-11-17 | 北京良桑通信技术有限责任公司 | Additive waveshape pretreatment method in digital communication modulation |
| CN101969319A (en) * | 2010-08-10 | 2011-02-09 | 贵州航天天马机电科技有限公司 | Universal digital dual modulation-demodulation technology in wireless communication |
| CN101662437B (en) * | 2008-08-29 | 2012-05-30 | 北京良桑通信技术有限责任公司 | Time-frequency-phase mixed multicarrier modulation method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4560440B2 (en) * | 2005-05-16 | 2010-10-13 | Ｏｋｉセミコンダクタ株式会社 | Demodulation circuit and demodulation method |
-
1990
- 1990-02-22 CN CN 90101016 patent/CN1022787C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101316158B (en) * | 2007-05-29 | 2010-11-17 | 北京良桑通信技术有限责任公司 | Additive waveshape pretreatment method in digital communication modulation |
| CN101662437B (en) * | 2008-08-29 | 2012-05-30 | 北京良桑通信技术有限责任公司 | Time-frequency-phase mixed multicarrier modulation method |
| CN101969319A (en) * | 2010-08-10 | 2011-02-09 | 贵州航天天马机电科技有限公司 | Universal digital dual modulation-demodulation technology in wireless communication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1022787C (en) | 1993-11-17 |
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