CN104519359A - Device and method for video stream processing - Google Patents
Device and method for video stream processing Download PDFInfo
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- CN104519359A CN104519359A CN201310456600.4A CN201310456600A CN104519359A CN 104519359 A CN104519359 A CN 104519359A CN 201310456600 A CN201310456600 A CN 201310456600A CN 104519359 A CN104519359 A CN 104519359A
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Abstract
The invention discloses a device and a method for video stream processing. The device comprises an Intel master control chip, a PCI-E bridging chip and at least one Netra slave chip. The Intel master control chip reads video stream from an external device, configuring a slave chip mapping space, determining a mapping space address, and sending the video stream through the PCI-E bridging chip to a shared memory of the Netra slave chip corresponding to the mapping space address. The PCI-E bridging chip performs information interaction between the Intel master control chip and the Netra slave chips. The Netra slave chips read the video stream from the shared memories, process the video stream and send out the code stream after processing. By adopting the scheme of the invention, the stream processing capability can be improved, and the problem that video stream processing is limited can be solved.
Description
Technical field
The present invention relates to the information processing technology, particularly relate to the Apparatus and method for carrying out video code flow process.
Background technology
In video data process field, the performance requirement that people carry out video code flow process to equipment is more and more higher, and the equipment performance of one single chip can not be met the need of market, so multi core chip scheme development in recent years is rapid, various solution emerges in an endless stream.
The process that equipment carries out video code flow specifically comprises: chip reads the video code flow from external equipment, carries out streaming video process, is sent by the code stream after process.
Present multi core chip scheme is the combination of multiple Intel chip or the combination of multiple Netra chip substantially, is described respectively below.
Scheme one, equipment is made up of multiple Intel chip:
Because Intel chip processing capabilities is limited, make this scheme have obvious defect, cause the video code flow disposal ability of Intel chip can not meet user's demand growing to high integration, HD video.
Scheme two, equipment is made up of multiple Netra chip:
Netra is specially for the powerful digital media processing platform of digital video monitoring application; Netra integrated chip ARM-A8 and digital signal processor (DSP, Digital Signal Processor).Netra chip in the industry cycle has preferably code stream disposal ability, the reading of high definition multichannel code stream, compression, display and controlling functions is integrated on Netra chip, can meets the demand of HD video.But under Nerta chip operates in linux system, first Nerta chip uses SDK (SDK, Software Development Kit) SDK to read video code flow, particularly, call SDK and get the video code flow of stream function reading from external equipment; Then Nerta chip carries out video code flow process again.First SDK is described below.
SDK refers to the set for setting up the developing instrument of application software for specific software kit, software frame, hardware platform, operating system etc., and middle finger of the present invention is for carrying out the SDK of video flowing reading.The video code flow read is from external equipment, and external equipment is concrete as the watch-dog in video monitoring system, and watch-dog sends to code stream treatment facility to carry out code stream process after gathering video code flow, comprises coding, decoding, transcoding etc.Often comprise the watch-dog of multiple different vendor in video monitoring system, code stream treatment facility needs to carry out code stream process to the watch-dog of multiple different vendor.Linux is a kind of class Unix operating system of free and open source code, and the SDK that each manufacturer provides develops mostly under windows system, cause a lot of SDK cannot run on Netra chip, and then the video code flow that can not successfully read from different external equipment, make video code flow process limited.
By analyzing above, under adopting mode one, Intel chip to operate in windows system, stream function can be got by normal call SDK, reading the video code flow from external equipment, then carry out streaming video process; But because Intel chip processing capabilities is limited, but can not satisfy the demands.Employing mode two, although Netra chip has preferably disposal ability, because operating in linux system, can not integrated SDK, cause reading the video code flow from different external equipment, make video code flow process limited.
To sum up, existingly carry out the scheme of video code flow process or there is the defect of disposal ability deficiency, or existing because of can not compatible to SD K and the limited defect of the video code flow process that causes.
Summary of the invention
The invention provides a kind of equipment carrying out video code flow process, this equipment can improve code stream disposal ability, can solve again the limited problem of video code flow process.
The invention provides a kind of method of carrying out video code flow process, the method can improve code stream disposal ability, can solve again the limited problem of video code flow process.
Carry out an equipment for video code flow process, the method equipment comprises Intel main control chip, expanding peripherals component interconnection Standard PC I-E bridging chip and at least one piece of Netra from chip;
Described Intel main control chip, reads the video code flow from external equipment, configures from chip mapping space, determines mapping space address, sends to the Netra corresponding with mapping space address from chip shared drive video code flow by PCI-E bridging chip;
Described PCI-E bridging chip, carries out Intel main control chip and Netra from the information interaction between chip;
Described Netra, from chip, reads video code flow from shared drive, carries out streaming video process, is sent by the code stream after process.
Preferably, described Netra comprises ARM-A8 and digital signal processor DSP from chip;
Described Intel main control chip, before reading the video code flow from external equipment, also receives the mapping space address information from described ARM-A8, by described PCI-E bridging chip to described ARM-A8 feedback response message by described PCI-E bridging chip;
Described ARM-A8, sends to described Intel main control chip by described PCI-E bridging chip by mapping space address information, and receives the feedback response message from described Intel main control chip by described PCI-E bridging chip, starts described DSP;
Described DSP, reads video code flow from shared drive, carries out streaming video process to it, is sent by the code stream after process.
Preferably, described DSP, reads video code flow from shared drive, decodes, encodes or transcoding process to it, is sent by the code stream after process.
Preferably, described Intel main control chip, after receiving the mapping space address information from described ARM-A8, also sends to ARM-A8 by initiation parameter assignment by described PCI-E bridging chip.
Preferably, described Intel main control chip, calls SDK SDK and gets stream function, read from external equipment video code flow.
Carry out a method for video code flow process, the method comprises:
Intel main control chip reads the video code flow from external equipment;
The configuration of Intel main control chip, from chip mapping space, is determined mapping space address, is sent to the Netra corresponding with mapping space address from chip shared drive video code flow by PCI-E bridging chip;
Netra reads video code flow from chip from shared drive, carries out streaming video process;
Code stream after process sends from chip by Netra.
Preferably, before described Intel main control chip reads the video code flow from external equipment, the method also comprises:
Mapping space address information is sent to Intel main control chip from the ARM-A8 of chip by PCI-E bridging chip by Netra;
Intel main control chip receives from Netra after the mapping space address information of the ARM-A8 of chip, by the ARM-A8 feedback response message of PCI-E bridging chip to Netra from chip by PCI-E bridging chip;
Netra starts DSP after the ARM-A8 of chip receives feedback response message;
Netra reads video code flow from chip from shared drive, carries out streaming video process, is sent by the code stream after process, specifically comprises: DSP reads video code flow from shared drive, carry out streaming video process to it, is sent by the code stream after process.
Preferably, described DSP carries out streaming video process comprise the video code flow read:
DSP decodes to the video code flow read, encodes or transcoding process.
Preferably, before mapping space address information is sent to Intel main control chip from the ARM-A8 of chip by PCI-E bridging chip by described Netra, the method comprises:
Netra reads the index value type parameter from the ARM-A8 of chip, judge whether index value is from chip identification, if so, then by PCI-E bridging chip, mapping space address information is sent to Intel main control chip described in performing;
Initiation parameter assignment, after receiving the mapping space address information from ARM-A8, also sends to Netra from the ARM-A8 of chip by PCI-E bridging chip by Intel main control chip.
Preferably, described Intel main control chip reads the video code flow from external equipment, comprising:
Intel main control chip calls SDK and gets stream function, reads from external equipment video code flow.
As can be seen from such scheme, in the present invention, the equipment carrying out video code flow process comprises Intel main control chip, PCI-E bridging chip and at least one piece of Netra from chip; Intel main control chip reads the video code flow from external equipment; The configuration of Intel main control chip, from chip mapping space, is determined mapping space address, is sent to the Netra corresponding with mapping space address from chip shared drive video code flow by PCI-E bridging chip; Netra reads video code flow from chip from shared drive, carries out streaming video process; Code stream after process sends from chip by Netra.The present invention adopts Intel main control chip to add Netra and realizes video code flow treatment facility from the mode of chip, and Intel main control chip reads video code flow.Like this, under Intel main control chip operates in windows system, normally can run the reading that SDK carries out video code flow when needed; Further, the disposal ability that fully application Netra chip is extremely strong, processes the video code flow read.Thus, both improve code code stream disposal ability, solve again the problem that video code flow process is limited.
Accompanying drawing explanation
Fig. 1 is the device structure schematic diagram that the present invention carries out video code flow process;
Fig. 2 is the method indicative flowchart that the present invention carries out video code flow process;
Fig. 3 is main control chip of the present invention and from the example flow diagram carrying out starting communication between chip.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with embodiment and accompanying drawing, the present invention is described in more detail.
The present invention adopts Intel main control chip to add Netra and realizes video code flow treatment facility from the mode of chip, reads video code flow by Intel main control chip, then uses Netra to process from chip the video code flow read; Like this, under Intel main control chip operates in windows system, normally can run the reading that SDK carries out video code flow when needed; Further, the disposal ability that fully application Netra chip is extremely strong, processes the video code flow read.Thus, both improve code code stream disposal ability, solve again the problem that video code flow process is limited.
See Fig. 1, for the present invention carries out the device structure schematic diagram of video code flow process, this equipment comprises Intel main control chip, expanding peripherals component interconnection standard (PCI-E, Peripheral Component InterconnectExpress) bridging chip and at least one piece of Netra are from chip, and Fig. 1 is the examples of 4 Netra from chip;
Described Intel main control chip, reads the video code flow from external equipment, configures from chip mapping space, determines mapping space address, sends to the Netra corresponding with mapping space address from chip shared drive video code flow by PCI-E bridging chip;
Described PCI-E bridging chip, carries out Intel main control chip and Netra from the information interaction between chip;
Described Netra, from chip, reads video code flow from shared drive, carries out streaming video process, is sent by the code stream after process.
External equipment is the equipment of Intel main control chip carry, such as, by local area network (LAN) (LAN, Local AreaNetwork) the carry equipment that connects, or, the carry equipment connected by Inter integrated circuit (I2C, Inter-Integrated Circuit) bus.
Intel main control chip carries out entirety to video code flow process and controls, and stores the mapping space address of each Netra from chip in Intel main control chip, and the corresponding Netra in mapping space address is from the communal space of chip; When needed, determine mapping space address, video code flow is sent to the corresponding communal space by PCI-E bridging chip, what the mapping space address possibility determined was corresponding is the part or all of communal space of a Netra from chip, and also the corresponding two or more Netra of possibility is from the part or all of communal space of chip.
Intel main control chip and Netra carry out information interaction by PCI-E bridging chip between chip, adopt PCI-E bus to carry out information transmission; Particularly, send to Netra from chip the information from Intel main control chip, send to Intel main control chip by from Netra from the information of chip.
Preferably, described Netra specifically comprises ARM-A8 and DSP from chip;
Described Intel main control chip, before reading the video code flow from external equipment, also receives the mapping space address information from described ARM-A8, by described PCI-E bridging chip to described ARM-A8 feedback response message by described PCI-E bridging chip;
Described ARM-A8, sends to described Intel main control chip by described PCI-E bridging chip by mapping space address information, and receives the feedback response message from described Intel main control chip by described PCI-E bridging chip, starts described DSP;
Described DSP, reads video code flow from shared drive, carries out streaming video process to it, is sent by the code stream after process.
The process of described DSP to video code flow comprises multiple, such as, decode, encode or transcoding process etc.
Before Intel main control chip reads the video code flow from external equipment, Intel main control chip and Netra will carry out startup communication process between chip, in this process, respective mapping space address information is informed to Intel main control chip from the ARM-A8 of chip by Netra.
Preferably, described Intel main control chip, after receiving the mapping space address information from described ARM-A8, also sends to ARM-A8 by initiation parameter assignment by described PCI-E bridging chip.Described initiation parameter assignment is that Intel main control chip informs the initiation parameter of Netra from chip in start-up course, can set as required, such as, comprise the type of video code flow treatment facility, the total number of DSP, video formats etc. that equipment comprises; Wherein video formats is that Netra carries out the standard after video code flow process from chip.
When Intel main control chip reads from external equipment video code flow, for needing the situation running SDK, from self memory space, reading corresponding SDK, running SDK, calling SDK and get stream function, read from external equipment video code flow.The SDK stored in Intel main control chip can be kept at self memory space after appointed website obtains in advance.Certainly, the present invention program is not only applicable to need the situation using SDK, being applicable to other yet and never calling SDK and get the situation that stream function carries out video code flow reading, reading the situation of video code flow as adopted proprietary protocol or standard agreement from external equipment.
In the present invention, the equipment carrying out video code flow process comprises Intel main control chip, PCI-E bridging chip and at least one piece of Netra from chip; Intel main control chip reads the video code flow from external equipment; The configuration of Intel main control chip, from chip mapping space, is determined mapping space address, is sent to the Netra corresponding with mapping space address from chip shared drive video code flow by PCI-E bridging chip; Netra reads video code flow from chip from shared drive, carries out streaming video process; Code stream after process sends from chip by Netra.The present invention adopts Intel main control chip to add Netra and realizes video code flow treatment facility from the mode of chip, and Intel main control chip reads video code flow, and Netra processes from chip the video code flow read; Like this, under Intel main control chip operates in windows system, normally can run the reading that SDK carries out video code flow when needed; Further, the disposal ability that fully application Netra chip is extremely strong, processes the video code flow read.Thus, both improve code code stream disposal ability, solve again the problem that video code flow process is limited.
See Fig. 2, for the present invention carries out the method indicative flowchart of video code flow process, it comprises the following steps:
Step 201, Intel main control chip reads the video code flow from external equipment.
Before this step, Intel main control chip will carry out driving initialization, and Intel main control chip and Netra will carry out startup communication process between chip, in this process, respective mapping space address information will be informed to Intel main control chip from the ARM-A8 of chip by Netra.
Device power, Intel main control chip runs primary control program, and primary control program carries out driving initialization, carries out the initialized preparation of DSP; Driving initialization and the general Intel chip initiation process of Intel main control chip are similar, carry out brief description here; It roughly comprises: device power, and Intel main control chip resets to equipment, prevents equipment from cannot operate; The register address of Intel main control chip mapped device; Download uboot and equipment operational factor, start the operation of uboot, detect internal memory whether successful initialization; Download kernel; Download file system; Start kernel.After carrying out driving initialization, Intel main control chip and Netra will carry out startup communication process between chip.
Below by Fig. 3, Intel main control chip and Netra are illustrated from carrying out startup communication between chip, in this flow process Intel main control chip and Netra from the information interaction of chip by carrying out transfer transmission through PCI-E bridging chip, here for the ease of describing, not by the statement of PCI-E bridging chip on stream.In the flow process of Fig. 3, Intel main control chip runs Windows system, and Netra is performed by ARM-A8 wherein from the operating process of chip, application program in ARM-A8 is hicore, here, only run middle DSP initialization and the DSP command process thread of hicore, to realize starting DSP.
The flow process of Fig. 3 comprises the following steps:
Step 301, Intel main control chip and Netra read respective DSP index value (dspIdx) respectively from chip, if dspIdx is 0, then perform step 302, otherwise wait for since the startup of chip is interrupted.
Intel main control chip and Netra store respective type parameter respectively from chip, to be indicated as main control chip still from chip; Type parameter DSP index value represents, in this example, if be 0, is then indicated as main control chip, otherwise is from chip.After device power, Intel main control chip and Netra by reading respective dspIdx, carry out numerical value judgement from chip; Particularly, what first Netra started from chip is ARM-A8, carries out numerical value judgement by ARM-A8.
For needing the situation running SDK, this step specifically comprises: Intel main control chip calls SDK and gets stream function, reads from external equipment video code flow.
Step 302, Netra sends from chip to Intel main control chip to start and interrupts.
Intel main control chip is had no progeny in receiving and starting, and continues to wait for that Netra sends mapping space address information from chip.
Here carry out Intel main control chip and Netra to send to start from the first time time synchronized between chip: Netra from chip to Intel main control chip and interrupt, represent that the DSP having entered hicore from chip starts process.
Step 303, Netra sends mapping space address information from chip to Intel main control chip.
Particularly, ARM-A8 maps the space address of DSP, obtains the communal space address information of DSP, the communal space address information of acquisition is called mapping space address information here.
Step 304, initiation parameter assignment sends to Netra from chip by Intel main control chip.
Intel main control chip is that DSP carries out initiation parameter assignment.
Step 305, Intel main control chip sends initialization and interrupts to Netra from chip.
Here carry out Intel main control chip and Netra from the second time time synchronized between chip: master chip interrupts to sending the initialization completed about initiation parameter assignment from chip, represent and established DSP state mapping address and parameter assignment success on master chip.
Intel main control chip sends initialization and interrupts, to inform that Netra is from chip enable DSP to Netra from chip.
Step 306, the initialization that Netra receives Intel main control chip from chip is interrupted, and starts DSP.
Step 307, Netra sends initialization and completes interruption from chip to Intel main control chip.
Here Intel main control chip and Netra is carried out from the third time time synchronized between chip: after chip DSP has started, sent the initialization started about DSP and complete interruption.
Step 202, the configuration of Intel main control chip, from chip mapping space, is determined mapping space address, is sent to the Netra corresponding with mapping space address from chip shared drive video code flow by PCI-E bridging chip.
Store the mapping space address of each Netra from chip in Intel main control chip, the corresponding Netra in mapping space address is from the communal space of chip; When needed, determine mapping space address, video code flow is sent to the corresponding communal space by PCI-E bridging chip, and what the mapping space address determined may be corresponding is the communal space of a Netra from chip, and also the corresponding two or more Netra of possibility is from the communal space of chip.
Step 203, Netra reads video code flow from chip from shared drive, carries out streaming video process.
Decoding, coding or transcoding etc. are comprised to the process of video code flow.
Step 204, the code stream after process sends from chip by Netra.
Particularly, display wall is such as sent to show.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (10)
1. carry out an equipment for video code flow process, it is characterized in that, this equipment comprises Intel main control chip, expanding peripherals component interconnection Standard PC I-E bridging chip and at least one piece of Netra from chip;
Described Intel main control chip, reads the video code flow from external equipment, configures from chip mapping space, determines mapping space address, sends to the Netra corresponding with mapping space address from chip shared drive video code flow by PCI-E bridging chip;
Described PCI-E bridging chip, carries out Intel main control chip and Netra from the information interaction between chip;
Described Netra, from chip, reads video code flow from shared drive, carries out streaming video process, is sent by the code stream after process.
2. equipment as claimed in claim 1, it is characterized in that, described Netra comprises ARM-A8 and digital signal processor DSP from chip;
Described Intel main control chip, before reading the video code flow from external equipment, also receives the mapping space address information from described ARM-A8, by described PCI-E bridging chip to described ARM-A8 feedback response message by described PCI-E bridging chip;
Described ARM-A8, sends to described Intel main control chip by described PCI-E bridging chip by mapping space address information, and receives the feedback response message from described Intel main control chip by described PCI-E bridging chip, starts described DSP;
Described DSP, reads video code flow from shared drive, carries out streaming video process to it, is sent by the code stream after process.
3. equipment as claimed in claim 2, it is characterized in that, described DSP, reads video code flow from shared drive, decodes, encodes or transcoding process to it, is sent by the code stream after process.
4. equipment as claimed in claim 2, is characterized in that, described Intel main control chip, after receiving the mapping space address information from described ARM-A8, also initiation parameter assignment is sent to ARM-A8 by described PCI-E bridging chip.
5. the equipment according to any one of Claims 1-4, is characterized in that,
Described Intel main control chip, calls SDK SDK and gets stream function, read from external equipment video code flow.
6. carry out a method for video code flow process based on equipment described in claim 1, it is characterized in that, the method comprises:
Intel main control chip reads the video code flow from external equipment;
The configuration of Intel main control chip, from chip mapping space, is determined mapping space address, is sent to the Netra corresponding with mapping space address from chip shared drive video code flow by PCI-E bridging chip;
Netra reads video code flow from chip from shared drive, carries out streaming video process;
Code stream after process sends from chip by Netra.
7. method as claimed in claim 6, is characterized in that, before described Intel main control chip reads the video code flow from external equipment, the method also comprises:
Mapping space address information is sent to Intel main control chip from the ARM-A8 of chip by PCI-E bridging chip by Netra;
Intel main control chip receives from Netra after the mapping space address information of the ARM-A8 of chip, by the ARM-A8 feedback response message of PCI-E bridging chip to Netra from chip by PCI-E bridging chip;
Netra starts DSP after the ARM-A8 of chip receives feedback response message;
Netra reads video code flow from chip from shared drive, carries out streaming video process, is sent by the code stream after process, specifically comprises: DSP reads video code flow from shared drive, carry out streaming video process to it, is sent by the code stream after process.
8. method as claimed in claim 7, is characterized in that, described DSP carries out streaming video process to the video code flow read and comprises:
DSP decodes to the video code flow read, encodes or transcoding process.
9. method as claimed in claim 7, is characterized in that, before mapping space address information is sent to Intel main control chip from the ARM-A8 of chip by PCI-E bridging chip by described Netra, the method comprises:
Netra reads the index value type parameter from the ARM-A8 of chip, judge whether index value is from chip identification, if so, then by PCI-E bridging chip, mapping space address information is sent to Intel main control chip described in performing;
Initiation parameter assignment, after receiving the mapping space address information from ARM-A8, also sends to Netra from the ARM-A8 of chip by PCI-E bridging chip by Intel main control chip.
10. the method according to any one of claim 6 to 9, is characterized in that, described Intel main control chip reads the video code flow from external equipment, comprising:
Intel main control chip calls SDK and gets stream function, reads from external equipment video code flow.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020037620A1 (en) * | 2018-08-23 | 2020-02-27 | 深圳市汇顶科技股份有限公司 | Interrupt processing method, master chip, slave chip, and multi-chip system |
| CN114401418A (en) * | 2021-12-30 | 2022-04-26 | 北京北广科技股份有限公司 | Embedded audio and video server based on multiple ARM chip architectures |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433207A (en) * | 2003-02-26 | 2003-07-30 | 北京艾尼通科技有限公司 | Video telephone conference system and its audio/video processing method |
| US20060085563A1 (en) * | 1995-10-09 | 2006-04-20 | Tetsuya Nakagawa | Terminal apparatus |
| EP2228734A1 (en) * | 2009-03-10 | 2010-09-15 | Kabushiki Kaisha Toshiba | Portable electronic device and access control method in portable electronic device |
| CN102438127A (en) * | 2011-10-08 | 2012-05-02 | 杭州海康威视数字技术股份有限公司 | Monitoring device, monitoring system and monitoring method supporting hybrid access |
-
2013
- 2013-09-29 CN CN201310456600.4A patent/CN104519359B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060085563A1 (en) * | 1995-10-09 | 2006-04-20 | Tetsuya Nakagawa | Terminal apparatus |
| CN1433207A (en) * | 2003-02-26 | 2003-07-30 | 北京艾尼通科技有限公司 | Video telephone conference system and its audio/video processing method |
| EP2228734A1 (en) * | 2009-03-10 | 2010-09-15 | Kabushiki Kaisha Toshiba | Portable electronic device and access control method in portable electronic device |
| CN102438127A (en) * | 2011-10-08 | 2012-05-02 | 杭州海康威视数字技术股份有限公司 | Monitoring device, monitoring system and monitoring method supporting hybrid access |
Non-Patent Citations (1)
| Title |
|---|
| 管庆; 朱海; 王凯; 宋金涛; 袁高爽茜: "基于TMS320DM8168的视频监控跟踪系统", 《数据采集与处理》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020037620A1 (en) * | 2018-08-23 | 2020-02-27 | 深圳市汇顶科技股份有限公司 | Interrupt processing method, master chip, slave chip, and multi-chip system |
| CN111226203A (en) * | 2018-08-23 | 2020-06-02 | 深圳市汇顶科技股份有限公司 | Interrupt processing method, master chip, slave chip and multi-chip system |
| US11113098B2 (en) | 2018-08-23 | 2021-09-07 | Shenzhen GOODIX Technology Co., Ltd. | Interrupt processing method, master chip, slave chip, and multi-chip system |
| CN111226203B (en) * | 2018-08-23 | 2023-07-07 | 深圳市汇顶科技股份有限公司 | Interrupt processing method, master chip, slave chip and multi-chip system |
| CN114401418A (en) * | 2021-12-30 | 2022-04-26 | 北京北广科技股份有限公司 | Embedded audio and video server based on multiple ARM chip architectures |
| CN114401418B (en) * | 2021-12-30 | 2023-09-12 | 北京北广科技股份有限公司 | Embedded audio and video server based on multiple ARM chip architectures |
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| CN104519359B (en) | 2017-09-22 |
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