CN104518774B - Output driving circuit - Google Patents

Abstract

The present invention provides a kind of output driving circuit to drive a joint sheet.Output driving circuit includes a pull-up circuit and a pull-down circuit.Pull-up circuit includes first, second, with the three the first transistor npn npns, first and second first transistor npn npn is serially connected between high a power line and joint sheet, controlled jointly by one first logical signal, the three the first transistor npn npns are in parallel with the two the first transistor npn npns, and the three the first transistor npn npns provide bias by one first power line.Pull-down circuit includes first, second, with the three the second transistor npn npns, first and second Second-Type strings of transistors is connected between low a power line and joint sheet, controlled jointly by one second logical signal, 3rd Second-Type transistor AND gate the second Second-Type coupled in parallel, and the three the second transistor npn npns provide bias by a second source line.Reaction speed of the pull-up circuit by framework for the one the first transistor npn npns to the reaction speed of the first logical signal less than the two the first transistor npn npns to the first logical signal.

Description

Output driving circuit

Technical field

Embodiments of the invention are on output driving device, output driving circuit and current potential converting system.

Background technology

In general, integrated circuit can substantially divide into core (core portion) and input/output section (input and output portion).Input/output section plays the bridge of the external communication in core, a side Face is needed internal signal caused by core (core signal), through joint sheet (pad) be delivered to integrated circuit it Outside, on the other hand it is also required to the external world being sent to the external signal of joint sheet, core is delivered to, to be handled.

Electronic product often speeds the requirement with saving with arithmetic speed, and the operating voltage of core needs to decline. Similar, in order to increase external signal efficiency of transmission between integrated circuit, the driving voltage of external signal of new generation also can be with Decline.For example, a kind of specification of memory, third generation double data rate Synchronous Dynamic Random Access Memory (Double-Data-Rate Three Synchronous Dynamic Random Access Memory, commonly referred to as DDR3SDRAM), its driving voltage is defined as 1.5V, and 1st generation stores with 2nd generation double data rate synchronous dynamic random-access The driving voltage of device (abbreviation DDR1 and DDR2) is respectively 2.5V and 1.8V.And newest DDR4, the DDR of forth generation, or even rule Determine that driving voltage is low to arrive 1.2V.

Conventional semiconductors processing procedure can produce two kinds of elements on semiconductor wafer：Core parts (core ) and input and output element (input and output device) device.For example, the reliability of core parts, it is The operation bar of its various kinds combinations of voltages of all conducting ends (for example grid end, drain terminal, source) under 1.1V operating voltage Under part, problem cannot all occur；The reliability of input and output element, be its all conducting end (for example grid end, drain terminal, Source) various kinds combinations of voltages under 1.5V operating voltage operating condition under, problem cannot all occur.For example, If input and output element and core parts are all MOS elements, the gate oxide in that input and output element will be thicker than core The gate oxide of element.In comparison, the speed of core parts (core device), driving force are strong, but input and output member Part (IO device) is strongr, can bear the high voltage stress of comparison.

Fig. 1 is output driving device 100 known to one, goes for DDR3, its input belonged in an integrated circuit Output par, c.Output driving device 100 drives joint sheet 102, is transfused to out-put supply line Vddio and Vssio and is powered, and two The voltage of person is respectively 1.5V and 0V.Output driving device 100 has electric potential transfer circuit 106, upper buffer circuit 108H, lower buffering Circuit 108L and output driver 110.For considering for arithmetic speed and power saving, core parts are used in core circuit 104 (core device), the voltage for supplying electricity to core power the line Vddcore and Vsscore of core circuit 104 is respectively 1.1V And 0V.Output driving device 100 is using input and output element (IO device).In output driver 110, pull-up (high-side) PMOS PH and drop-down (low-side) NMOS NL, because it uses the weaker input and output element of driving force, Meet DDR3 driving force specification again, so sizable semiconductor area (silicon area) will be taken.

Prior art proposes can be in output driving device, using core parts, with the semiconductor surface needed for reduction Product.Fig. 2 shows another output driver 120 of the prior art, the output driver 110 being substituted in Fig. 1.Output is driven In dynamic device 120, PMOS PH1 and PH2 and NMOS NL1 and NL2 are to use core parts.PMOS PH2 and NMOS NL2's Control gate is connected respectively to power line Vbp and Vbn, and its voltage is respectively 0.4V and 1.1V.PMOS PH1 control gate then receives Logical signal Sp, its height logic level are 1.5V and 0.4V respectively.NMOS NL1 control gate then receives logical signal Sn, its Height logic level is 1.1V and 0V respectively.Here so-called high logic level refers to that a signal is equal in logic " 1 " when, its institute During the voltage potential of presentation, and to be then the signal be equal in logic low logic current potential " 0 ", the voltage potential that is presented.PMOS PH1 is serially connected with PH2, and NMOS NL1 and NL2 is serially connected.Such series connection structure can prevent that original from being for operating In the core parts (PMOS PH1 and PH2 and NMOS NL1 and NL2) of 1.1V operating voltage, too high operation can suffer from The stress of voltage (1.5V) and caused by infringement.

Among output driver 120, PMOS PH2 control gate is understood quite to the parasitic capacitance between joint sheet 102 Greatly.During in order to avoid signal intensity on joint sheet 102, because of Capacitance Coupled and caused by power line Vbp spread of voltage, because This, PMOS PH2 control gate to connect one it is sizable from coupling electric capacity 122.Similar, NMOS NL2 control gate also will Connect one it is sizable from coupling electric capacity 124, to reduce voltage influence of the signal intensity on joint sheet 102 to power line Vbn. Also can be quite from coupling electric capacity 122 and the semiconductor area shared by 124 it is considerable.

The content of the invention

A kind of output driving circuit of proposition (output driver) of the present invention, to drive a joint sheet (pad).Should Output driving circuit includes a pull-up circuit and a pull-down circuit.The pull-up circuit includes first, second, with the three the first types Transistor, first and second first transistor npn npn are serially connected between a high power line and the joint sheet, patrolled jointly by one first Volume signal is controlled, and the three the first transistor npn npns are in parallel with the two the first transistor npn npns, and the three the first transistor npn npns Bias is provided by one first power line.The pull-down circuit includes first, second, with the three the second transistor npn npns, this first and the Two Second-Type strings of transistors are connected between a low power line and the joint sheet, are controlled jointly by one second logical signal, and this Three Second-Type transistor AND gates the second Second-Type coupled in parallel, and the three the second transistor npn npns are provided by a second source line Bias.The pull-up circuit by framework for the one the first transistor npn npns to the reaction speed of first logical signal less than this second Reaction speed of first transistor npn npn to first logical signal.

The present invention also proposes a kind of current potential converting system, is powered by a high power line and a low power line.The current potential turns Change system and a bias offer circuit and one first electric potential transfer circuit are provided.The bias provides circuit and includes a reference current potential Change-over circuit and a feedback circuit.The reference electric potential transfer circuit is by one first input logic current potential and a reference bias Controlled, the output logic level of output one first.The feedback circuit, which provides, adjusts the reference bias, so that the first output logic Current potential is about stable at a preset value.First electric potential transfer circuit has uses electric potential transfer circuit identical circuit with the reference Framework, controlled by an input signal and the reference bias, to export an output signal.When the input signal is first defeated for this When entering logic level, the voltage of the output signal is approximately equal to the preset value；When the input signal is another input logic current potential When, the voltage of the output signal is approximately equal to one of voltage of high power line power line low with this.

Another output driving device of the present invention, include buffer circuit, once current potential conversion on upper electric potential transfer circuit, one Circuit, once buffer circuit and an output driving circuit.Input signal is converted into defeated on one by electric potential transfer circuit on this Go out signal.The input signal has a two input logic current potentials, and output signal has and exports logic level on two on this.Delay on this Circuit is rushed according to output signal on this, drives control terminal on one.The input signal is converted into by the lower electric potential transfer circuit Output signal, the lower output signal have two times output logic levels.The lower buffer circuit is according to the lower output signal, driving one Lower control terminal.The output driving circuit includes control terminal, lower control terminal on this, and the output driving circuit drives a joint sheet. This two times output logic level is identical with the two input logics current potential.

Brief description of the drawings

For the above objects, features and advantages of the present invention can be become apparent, the tool below in conjunction with accompanying drawing to the present invention Body embodiment elaborates, wherein：

Fig. 1 is output driving device known to one.

Fig. 2 shows another output driver of the prior art.

The output driving device that Fig. 3 displays are implemented according to the present invention.

Fig. 4 A show electric potential transfer circuit on one.

Fig. 4 B show a current potential converting system.

Fig. 5 A show electric potential transfer circuit.

Fig. 5 B show another current potential converting system.

Fig. 6 citings show some signal waveforms in Fig. 3.

Component label instructions are as follows in figure：

100 output driving devices

102 joint sheets

104 core circuits

106 electric potential transfer circuits

The upper buffer circuits of 108H

Buffer circuit under 108L

110 output drivers

120 output drivers

122nd, 124 from coupling electric capacity

600th, 600a, 600b output driving device

602 output driving circuits

604 buffer portions

606 current potential conversion portions

608H pull-up circuits

608L pull-down circuits

610 joint sheets

800th, the upper electric potential transfer circuit of 800a, 800b, 800-ref

802 current mirrors

860 biass provide circuit

862 operational amplifiers

900th, electric potential transfer circuit under 900a, 900b

902 current mirrors

960 biass provide circuit

The upper buffer circuits of BH

Buffer circuit under BL

BN inputs

BP inputs

CN is from coupling electric capacity

CP is from coupling electric capacity

IN inputs

Electric potential transfer circuit under lshn

The upper electric potential transfer circuits of lshp

Nbias reference bias

Ncon tie points

NL, NL1, NL2, NL6, NL7, NL8, NL9, NL10, NL11, NL12, NL13, NMOS transistor

OUT output ends

Pbias reference bias

Pcon tie points

PH, PH1, PH2, PH6, PH7, PH8, PH9 PMOS transistors

RN, RP resistance

Sinv-p reverse signals

Sin-n, Sin-p input signal

Sn logical signals

The non-return signals of Snon-p

Sout-n output signals

Sout-p output signals

Sout-p-ref output signals

Sp logical signals

Ssfn output signals

Ssfp output signals

S-core, S-core-a, S-core-b core signal

T0, t1, t2, t3, t4, t5 time point

Tdead-f, Tdead-r not overlapping period

The high-end unlatching sections of Ths-on

Open section in Tls-on lower ends

Vbp, Vbn power line

Vddio, Vssio input and output power line

Vddcore, Vsscore core power line

Vnth, Vpth change voltage

Vpad voltages

Embodiment

The output driving device 600 that Fig. 3 displays are implemented according to the present invention, it includes current potential conversion portion 606, buffer part Divide 604 and output driving circuit 602.Output driving device 600 all uses core parts, with the semiconductor surface needed for reduction Product.Output driving device 600 is only one embodiment of the invention, is not intended to limit the invention.For example, in another foundation In one output driving device of institute's embodiment of the present invention, while possess core parts and input and output element.

In following examples, core power line Vddcore and Vsscore are respectively 1.1V and 0V, and input and output power supply Line Vddio and Vssio are respectively 1.5V and 0V, as example, go for DDR3 input and output drive device.But this Invention not limited to this.For example, other embodiment of the invention, to go for the input and output of other kind of DDR specification Drive device, its input and output power line Vddio can be 1.35V or 1.2V.

In Fig. 3, current potential conversion portion 606 includes upper electric potential transfer circuit lshp and lower electric potential transfer circuit lshn.Upper electricity Position change-over circuit lshp is controlled by core signal S-core and reference bias pbias, and produces output signal Ssfp.Core Signal S-core low and high logic level, it is core power line Vsscore voltage and core power line Vddcore respectively Voltage, for example, be 0V and 1.1V respectively.Output signal Ssfp height logic level, about it is input and output respectively Power line Vddio and Vbp voltage；For example, it is respectively 1.5V and 0.4V.Lower electric potential transfer circuit lshn is by core signal S-core and reference bias nbias are controlled, and produce output signal Ssfn.Output signal Ssfn height and low logic electricity Position, about it is power line Vbn and Vssio voltage respectively；For example, it is respectively 1.1V and 0V.Bias provide circuit 860 with 960 provide reference bias pbias and nbias respectively.Herein it can be found that output signal Ssfn height and low logic current potential are with core As heart signal S-core.Although upper electric potential transfer circuit lshp and lower electric potential transfer circuit lshn are by input and output power supply Line Vddio and Vssio power supply, but only upper electric potential transfer circuit lshp provides the function of current potential conversion, and lower current potential turns Changing circuit lshn does not have.Upper electric potential transfer circuit lshp and lower electric potential transfer circuit lshn internal circuit will slightly with function mode After explain.

Buffer portion 604 has upper buffer circuit BH and lower buffer circuit BL.Upper buffer circuit BH is by input and output power line Vddio and Vbp powers, as shown in Figure 3, comprising two reversers, for reducing upper electric potential transfer circuit lshp capacitive character Load, according to output signal Ssfp, produce logical signal Sp.Similar, lower buffer circuit BL is supplied by power line Vbn and Vssio Electricity, for reducing lower electric potential transfer circuit lshn capacity load, according to output signal Ssfn, produce logical signal Sn.

Output driving circuit 602 has pull-up circuit 608H and pull-down circuit 608L.

There are resistance RP, PMOS PH6, PH7 and PH8 in pull-up circuit 608H.PMOS PH7 and PMOS PH8 are parallel to PMOS Between PH6 and joint sheet 610.PMOS PH6 are connected between input and output power line Vddio and PMOS PH7.PMOS PH8's One is connected between control terminal and input and output power line Vddio from coupling electric capacity CP, and PMOS PH8 control terminal is connected to electricity Source line Vbp.Influence of the signal intensity to power line Vbp on joint sheet 610 can be reduced from coupling electric capacity CP.

Although PMOS PH6 and PH7 are controlled by signal Sp, because resistance RP presence, PMOS PH6 are to letter Number Sp reaction speed, it will the reaction speed less than PMOS PH7 to signal Sp.

As illustrated, pull-down circuit 608L circuit framework is similar to pull-up circuit 608H, pull-up circuit can be passed through 608H explanation and understand, therefore be not repeated.

When logical signal Sp and Sn logical value are fixed as " 0 " when, its voltage is respectively 0.4V and 0V, now joint sheet 610 are charged to about 1.5V.Because NMOS NL8 strangulation effect, the tie point Ncon voltages between NMOS NL8 and NL6 1.1V-Vthn can be charged in advance, wherein, Vthn is the critical voltage (threshold of some nmos pass transistors in integrated circuit voltage).In an example, Vthn 0.81V, and in integrated circuit some PMOS transistors critical voltage Vthp=- 1.05V.When signal Sp and Sn logical value all by " 0 " be transformed into " and 1 " when, its voltage is respectively become as 1.5V and 1.1V.Now PMOS PH6 are closed into NMOS NL6, the NL7 that are switched on for open circuit, joint sheet 610 and NL8 is pulled down, so its magnitude of voltage returns Decline since 1.5V toward 0V.NMOS NL6 are less than NMOS NL7 for logical signal Sn for logical signal Sn reaction speed Reaction speed, so the decline that contact Ncon voltage can relax, avoid NMOS NL8 highest drain-source from biasing (maximum Drain-to-source voltage) excessively produce thermoelectron more than 1.1V and NMOS NL8 are caused damage.

Similar reason, when signal Sp and Sn logical value all by " 1 " be transformed into " and 0 " when, NMOS NL6 be closed into for Open circuit, joint sheet 610 PMOS PH6, PH7 switched on and PH8 are pulled up, so its magnitude of voltage can rise since 0V toward 1.5V. PMOS PH6 are less than reaction speeds of the PMOS PH7 for signal Sp for signal Sp reaction speed, so tie point Pcon It the rising that voltage can relax, can about control PMOS PH8 minimum drain-source to be biased near -1.1V, avoid producing energy mistake Strong thermoelectron and PMOS PH8 are caused damage.

Although pull-down circuit 608L and pull-up circuit 608H use the core parts suitable for 1.1V operating voltages, Powered by higher 1.5V power supplys.More than analysis with element reliability simplation verification it was found from, it is appropriately designed under drop-down Circuit 608L and pull-up circuit 608H can meet the demand of general business reliability.

From the perspective of reaching identical driving force, the current driving capability summation of NMOS NL7 and NL8 in Fig. 3 will The current driving capability of NMOS NL2 in approximately equal to prior art Fig. 2.Therefore, understood under comparing, for element size, NMOS NL8 can be smaller than NMOS NL2, so NMOS NL8 control gate also can be compared with to the parasitic capacitance between joint sheet 610 It is small.In Fig. 3 from coupling electric capacity CN, relative in prior art Fig. 2 from coupling electric capacity 124, it is possible to it is smaller, one can be saved A little semiconductor areas.It is similar, in Fig. 3 can also be smaller from coupling electric capacity 122 than in Fig. 2 from coupling electric capacity CP, save some half Conductor area.

Fig. 4 A show electric potential transfer circuit 800 on one, can be as the upper electric potential transfer circuit lshp in Fig. 3.Upper current potential Change-over circuit 800 is all to use core parts.Upper electric potential transfer circuit 800 receives input signal respectively from input IN and BP Sin-p and reference bias pbias, output signal Sout-p is produced in output end.

(voltage is respectively by core power line Vddcore and core power line Vsscore for three reversers in Fig. 4 A 1.1V and 0V) powered, produce reverse signal Sinv-p and non-return signal Snon-p according to input signal Si n-p.Other NMOS and PMOS annexation as shown in Figure 4 A, by input and output power line Vddio and input and output power line Vssio Powered, its voltage is respectively 1.5V and 0V.NMOS NL9, NL10 and NL11 annexation are similar to the drop-down electricity in Fig. 3 Road 608L, its operating principle and the contributing effect for element reliability, which can analogize, to be learnt, therefore is no longer repeated.

When input signal Si n-p logical value is " 0 " when, its voltage is 0V, reverse signal Sinv-p and non-return signal Snon-p voltage is respectively 1.1V and 0V.Now, because NMOS NL11 are closed as open circuit, output signal Sout-p meetings A charging current is charged caused by current mirror 802, until output signal Sout-p voltage is equal to input and output power supply Untill line Vddio voltage (1.5V).Output signal Sout-p logical value becomes " 1 ".

When input signal Si n-p logical value is " 1 " when, its voltage is 1.1V, reverse signal Sinv-p and non-return letter Number Snon-p voltage is respectively 0V and 1.1V.Now, because NMOS NL12 and NL13 is open circuit (open circuit), So current mirror 802 disappears (becoming 0) to output signal Sout-p charging current.Because it is in short-circuit conducting state, NMOS NL9, NL10, NL11 combination can be considered as a pull down resistor with equivalent.PMOS PH9 grid end is connected to reference bias pbias, PMOS PH9 can be considered as a pull-up resistor with equivalent.Pull down resistor and pull-up resistor form a bleeder circuit so that now defeated Going out signal Sout-p voltage can finally stablize in a preset value.It will illustrate later, as long as giving appropriate reference bias Pbias, this preset value can control the voltage in 0.4V, approximately equal to power line Vbp.Output signal Sout-p logical value Become " 0 ".

Fig. 4 B show a current potential converting system, to explain in one embodiment, reference bias pbias be how to produce with Using.Fig. 4 B include a bias and provide circuit 860 and output driving device 600a, 600b.Each output driving device 600a, 600b can be realized with the output driving device 600 in Fig. 3.Output driving device 600a, 600b have upper current potential respectively Change-over circuit 800a, 800b.Bias, which provides circuit 860, also has upper electric potential transfer circuit 800-ref.Each upper electricity in Fig. 4 B Position change-over circuit can be realized with the upper electric potential transfer circuit 800 in Fig. 4.The present invention is not limited to a bias and provides electricity Road can only provide reference bias to two output driving devices, can also give one or more output driving devices.

Bias, which provides circuit 860, also has an operational amplifier 862, and it produces reference bias pbias.Reference bias Pbias is supplied to the input BP of all upper electric potential transfer circuits in Fig. 4 B.Two inputs of operational amplifier 862 connect respectively It is connected to electric potential transfer circuit 800-ref output end OUT and power line Vbp.Upper electric potential transfer circuit 800-ref input End IN is then connected to 1.1V, that is, core signal S-core high logic level.Operational amplifier 862 provides one and born back Infeed mechanism, reference bias pbias is controlled, so that the output signal Sout-p-ref that upper electric potential transfer circuit 800-ref is exported About stablize the voltage (0.4V) in power line Vbp.

As illustrated by previous Fig. 4 A, when input signal Si n-p logical value is " 0 ", its voltage is 0V, is now exported Signal Sout-p logical value can become " 1 ", its voltage is 1.5V；When input signal Si n-p logical value is " 1 ", its voltage For 1.1V, output signal Sout-p logical value can become " 0 ", its voltage is controlled by reference bias pbias.Since make Fig. 4 B In reference bias pbias electric potential transfer circuit 800-ref output signal Sout-p-ref is about stablized in 0.4V, So each logical value of upper electric potential transfer circuit 800a, 800b output signal " low output logic level corresponding to 0 ", All big appointment is 0.4V.

Current potential converting system in Fig. 4 B at least possesses and has a benefit：The output signal of each upper electric potential transfer circuit, Its low output logic level (being in this embodiment 0.4V), will not substantially change with manufacture of semiconductor drift.This It is because bias provides the negative feedback mechanism provided in circuit 860, no matter the drift of manufacture of semiconductor, can adjust why automatically Whole reference bias pbias, output signal Sout-p-ref is stablized in 0.4V, also stabilizes each upper electric potential transfer circuit together Output signal low output logic level.

Fig. 5 A show electric potential transfer circuit 900, can be as the lower electric potential transfer circuit lshn in Fig. 3.Fig. 5 B show Show another current potential converting system.Fig. 5 A and Fig. 5 B running and explanation can the running with reference to figure 4A and Fig. 4 B and explanations respectively And deduce.Briefly, the lower electric potential transfer circuit 900 in Fig. 5 A, its output signal Sout-n low output logic level are 0V, its height output logic level are determined by reference bias nbias.Bias provides in circuit 960 and provides negative feedback in Fig. 5 B Mechanism, though the drift of manufacture of semiconductor why, can be with adjust automatically reference bias nbias, output signal Sout-n-ref It is stable in 1.1V, also the height output logic level of the Simultaneous Stabilization output signal of each upper electric potential transfer circuit is 1.1V.

Substantially, the lower electric potential transfer circuit lshn in Fig. 3 does not carry out current potential conversion, because its output signal Ssfn Height logic level, all as core signal S-core height logic level.But lower electric potential transfer circuit lshn with Upper electric potential transfer circuit lshp is together present, and can automatically provide a not overlapping function, that is, cause the pull-down circuit in Fig. 3 608L and pull-up circuit 608H will not start simultaneously at conducting., will if pull-down circuit 608L simultaneously turns on pull-up circuit 608H A current path can be formed between input and output power line Vddio and Vssio, generation runs through electric current (shoot through Current), power supply is more than wasted, more likely causes input and output power line Vddio or Vssio voltage instability, triggers one The logic judgment mistake of a little logic circuits.

As Fig. 4 A are explained, output signal Sout-p is by logic " 0 " become " 1 " when, be in no drop-down electricity Under conditions of stream, only 1.5V is lifted to since 0.4V by current mirror 802.As long as so charging that current mirror 802 provides Electric current is enough big, suitable big of output signal Sout-p raised voltage rate of change can.It is opposite, output signal Sout-p by 1 " becomes in logic " " 0 " when, be with the contention balance of pull down resistor, being become by 1.5V in a pull-up resistor 0.4V.It is expected that, output signal Sout-p drop-out voltage rate of change, should relatively thereon for up voltage rate of change This can be slow.

Reason in similar Fig. 4 A, in fig. 5, output signal Sout-n raised voltage rate of change, relative to its decline For voltage change ratio, it should can be slow.

In practice, very simply output signal Sout-n raised voltage rate of change, design can be believed less than output Number Sout-p raised voltage rate of change；Output signal Sout-p drop-out voltage rate of change, design is less than output signal Sout-n drop-out voltage rate of change.Can thus produce not overlapping function, at the same can also be in simplification figure 3 buffering up and down Circuit BH and BL design.

Fig. 6 citings show some signal waveforms in Fig. 3, are core signal S-core, output letter respectively from top to bottom Voltage Vpad on number Ssfp, logical signal Sp, output signal Ssfn, logical signal Sn and joint sheet 610.Illustrate below It please also refer to the output driving device 600 in Fig. 3.

Before time point t0, core signal S-core is 0V, and output signal Ssfp, signal Sp, output signal Ssfn are with believing Number Sn is entirely in logic " 1 ", pull-up circuit 608H is closed, pull-down circuit 608L conductings, so voltage Vpad is 0V.

Become 1.1V from 0V in time point t0, core signal S-core.Therefore, upper electric potential transfer circuit lshp output letter Number Ssfp starts from 1.5V, and relatively slow past 0.4V declines；And lower electric potential transfer circuit lshn output signal Ssfn starts It is comparatively faster to drop to 0V from 1.1V.Because the low conversion electricity descended excessively set by buffer circuit BL of output signal Ssfn quickly Vnth is pressed, so signal Sn turns into 0V also about in time point t0 from 1.1V drops.Now, pull-down circuit 608L starts to be closed, Open circuit is presented.

In time point t1, the output signal Ssfp low excessively upper set conversion voltage Vpth of buffer circuit BH of voltage, institute 0.4V is just transformed into from 1.5V with signal Sp.Now, pull-up circuit 608H is opened, and is begun to turn on.Voltage Vpad is pulled up electricity Road 608H is pulled upward to 1.5V from 0V.

It is a not overlapping period Tdead-r, because pull-up circuit 608H and pull-down circuit in the section of time t0 to t1 608L is to close, and is not turned on.Because now joint sheet 610 is not charged or discharged, therefore its voltage Vpad maintains the time State before t0, so being 0V.

Become 0V from 1.1V in time t2, core signal S-core.Upper electric potential transfer circuit lshp output signal Ssfp Start from 0.4V, it is comparatively faster to be raised to 1.5V；And lower electric potential transfer circuit lshn output signal Ssfn starts from 0V, relatively Slower past 1.1V rises.Because the conversion voltage Vpth under the exceeding of output signal Ssfp quickly set by buffer circuit BH, So signal Sp is changed into 1.5V also about in time point t2 from 0.4V.Now, pull-up circuit 608H is closed, and open circuit is presented.

Time t1 to t2 section, high-end unlatching section Ths-on can be defined as, because only that pull-up circuit 608H is led It is logical, and pull-down circuit 608L is closed.

In time point t3, output signal Ssfn voltage just exceeds the set conversion voltage Vnth of lower buffer circuit BL, institute 1.1V is just transformed into from 0V with signal Sn.Now, pull-down circuit 608L is opened, and is initially entered lower end and is opened section Tls-on, Pull-up circuit 608H is closed, and pull-down circuit 608L is turned on.Voltage Vpad is pulled down circuit 608L and pulls down to 0V from 1.5V.

It is another not overlapping period Tdead-f, because pull-up circuit 608H and pull-down circuit in time t2 to t3 section 608L is to close, and is not turned on.Because now joint sheet 610 is not charged or discharged, therefore its voltage Vpad maintains the time State before t2, so being 1.5V.

Although not overlapping period Tdead-f and Tdead-r length, substantially by upper buffer circuit BH and lower buffering electricity Voltage Vpth and Vnth is changed defined in the BL of road to determine.But it was found from the analysis more than, though conversion voltage Vpth with Vnth is why, as long as suitably separating output signal Ssfp and Ssfn voltages rise and fall rate of change, not overlapping period Tdead-f and Tdead-r is just bound to exist.This means upper buffer circuit BH and lower buffer circuit BL design can be held very much Easily, the reduction of consideration capacity load is generally only needed.In other words, although lower electric potential transfer circuit lshn is false similar to one (dummy) electric potential transfer circuit, not as upper electric potential transfer circuit lshp is provided with the function of current potential conversion.But lower current potential Change-over circuit lshn together exists with upper electric potential transfer circuit lshp, can provide not overlapping function, buffer circuit BH in simplification With lower buffer circuit BL design.

Although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention, any this area skill Art personnel, without departing from the spirit and scope of the present invention, when a little modification and perfect, therefore the protection model of the present invention can be made Enclose to work as and be defined by what claims were defined.

Claims (5)

1. a kind of output driving circuit, to drive a joint sheet, comprising：

One pull-up circuit, comprising：

First, secondth, with the three the first transistor npn npns, first and second first transistor npn npn be serially connected with a high power line with should Between joint sheet, controlled jointly by one first logical signal, the three the first transistor npn npns and the two the first transistor npn npns Parallel connection, and the three the first transistor npn npns provide bias by one first power line；And

One pull-down circuit, comprising：

First, secondth, with the three the second transistor npn npns, first and second Second-Type strings of transistors be connected to a low power line with should Between joint sheet, controlled jointly by one second logical signal, the transistor npn npn of the 3rd Second-Type transistor AND gate the two the second Parallel connection, and the three the second transistor npn npns provide bias by a second source line；

Wherein, the pull-up circuit is by framework：The one the first transistor npn npns are less than to the reaction speed of first logical signal Reaction speed of the two the first transistor npn npns to first logical signal；The pull-down circuit is by framework：First Second-Type Transistor is to the reaction speed of second logical signal, less than the two the second reactions of the transistor npn npn to second logical signal Speed.

2. as claimed in claim 1 output driving circuit, it is characterised in that the three the first transistor npn npns have a control terminal The bias of first power line offer is received, the three the second transistor npn npns have another control terminal to receive the second source line The bias of offer, the high logic level and a low logic current potential of first logical signal be respectively the high power line with this first The voltage of power line, and another high logic level of second logical signal and another low logic current potential are respectively second electricity The voltage of source line power line low with this.

3. the as claimed in claim 1 output driving circuit, also comprising first and second from coupling electric capacity, this is first from coupling capacitance connection Between a control terminal of the three the first transistor npn npns and the high power line, this second from coupling capacitance connection in the three the second Between another control terminal of transistor npn npn and the low power line.

4. output driving circuit as claimed in claim 1, it is characterised in that the voltage of first power line is less than the second source The voltage of line.

5. output driving circuit as claimed in claim 1, it is characterised in that the electricity between the high power line and first power line Pressure difference, equal to the voltage difference between the second source line and the low power line.