CN104517964B - Three-dimensional semiconductor memory devices and its three-dimensional logic array structure - Google Patents
Three-dimensional semiconductor memory devices and its three-dimensional logic array structure Download PDFInfo
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Abstract
The invention discloses a kind of three-dimensional semiconductor memory devices and its three-dimensional logic array structure.Three-dimensional semiconductor memory devices, including one array architecture, a perimeter circuit structure and a three-dimensional logic array structure.Array structure has Y the first contacts.These Y the first contacts are located at the side of array structure.Y is between MN‑1To MNBetween.Y, M and N is natural number.M is more than or equal to 2.Three-dimensional logic array structure includes N groups gate electrode, an input electrode and Y output electrode.Each group gate electrode has M gate electrode.These Y output electrode connects Y contact.These MN gate electrode and input electrode are connected to perimeter circuit structure.
Description
Technical field
The invention relates to a kind of semiconductor device and its logic array architecture, and in particular to a kind of three-dimensional half
Conductor device and its three-dimensional logic array structure.
Background technology
During fabrication, the amount of data storage of per unit area will be that key refers to high density memory devices on integrated circuit
Mark.Therefore, when storage arrangement critical dimension technology has reached bottleneck, in order to reach every bigger storage density and drop
The low production cost per bit, the mode of general recommendations is by multi-level memory cell lamination.In addition, new memory technology
Expansion, including phase transition storage (phase change memory), ferromagnetic store (ferromagnetic memory), gold
Belong to oxide type memory (metal oxide based memory) etc..
Memory technology needs a series of different processing steps, followed by the manufacture for secondary peripheral circuit, outside
It is, for example, address decoder (address decoders), state machine (state machines), and Instruction decoding to enclose circuit
Device (command decoder).Because memory array and peripheral circuit are required for the support of manufacturing step, so to hold
The production line of line memory storage device may costly, or the circuit to manufacture peripheral circuit is used as compromise.It will so cause
The integrated circuit of storage arrangement is manufactured using the technology of higher order, causes process costs more to improve.
When the memory performance lifting in integrated circuit so that manufacturing cost more and more higher, it is necessary to propose a low manufacture
The integrated circuit memory structure of cost.
The content of the invention
The invention relates to a kind of three-dimensional semiconductor memory devices and its three-dimensional logic array structure, and it utilizes three-dimensional logic battle array
Array structure is arranged at the design between one array architecture and a perimeter circuit structure, to reduce manufacturing cost.
According to the first aspect of the invention, a kind of three-dimensional semiconductor memory devices are proposed.Tie up semiconductor device, including an array knot
Structure, a perimeter circuit structure and a three-dimensional logic array structure.Array structure has Y the first contacts.These Y the first contacts
Positioned at the side of array structure.Y is between MN-1To MNBetween.Y, M and N is natural number.M is more than or equal to 2.Three-dimensional logic battle array
Array structure includes N groups gate electrode, an input electrode and Y output electrode.Each group gate electrode has M gate electrode.This
A little Y output electrodes connect Y contact.These MN gate electrode and input electrode are connected to perimeter circuit structure.
According to the second aspect of the present invention, a kind of three-dimensional logic array structure is proposed.Three-dimensional logic array structure includes N
Group gate electrode, an input electrode and Y output electrode.Each group gate electrode has M gate electrode.These Y output electricity
Pole connects Y contact of one array architecture.These Y contact is located at the side of array structure.These MN gate electrode and
Input electrode connects a perimeter circuit structure.Y is between MN-1To MNBetween.Y, M and N is natural number.M is more than or equal to 2.
According to the third aspect of the present invention, a kind of three-dimensional logic array structure is proposed.Three-dimensional logic array structure includes M
Individual first gate electrode, several first grids, N number of second grid electrode, several second grids and Y semiconductor laminated.It is each
First gate electrode is applied in a positive voltage, a negative voltage or a ground voltage.Each first grid is linked in sequence in these
One of first gate electrode.Each second grid electrode is applied in positive voltage, negative voltage or ground voltage.Each second
Grid is connected to one of these second grid electrodes.It is each semiconductor laminated positioned at wherein the two of these first grids
Between and wherein the two of these second grids between.The quantity of these first grids is equal to the quantity of these second grids.This
The quantity of a little first grids is equal to or less than M*N+1.Y is equal to or less than M*N.M and N is natural number.M and N is more than or equal to 4.M
Greatest common factor (G.C.F.) (greatest common divisor) with N is 1.
More preferably understand to have to the above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinate institute
Accompanying drawings, it is described in detail below：
Brief description of the drawings
Fig. 1 illustrates the schematic diagram of a three-dimensional logic array.
Fig. 2 illustrates the schematic diagram of another three-dimensional logic array.
Fig. 3 illustrates the schematic diagram of another three-dimensional logic array.
Fig. 4 illustrates the schematic diagram of another three-dimensional logic array.
Fig. 5 illustrates the schematic diagram of a three-dimensional semiconductor memory devices.
Fig. 6 illustrates the schematic diagram of another three-dimensional semiconductor memory devices.
Fig. 7 illustrates the schematic diagram of a three-dimensional logic array.
Fig. 8 illustrates the schematic diagram of another three-dimensional semiconductor memory devices.
Fig. 9 illustrates the schematic diagram of another three-dimensional logic array.
Figure 10 illustrates the schematic diagram of another three-dimensional logic array.
【Symbol description】
100、200、300、400、500、600、700、800、900、900’：Three-dimensional logic array structure
110th, 211,212,910, Y1~Y20：It is semiconductor laminated
121、122、221、222、223、224、921、922、923、924：Grid
130、230、X0：Input electrode
141st, 142,214,243,243,244, X1~X8：Gate electrode
150th, 251,252, Y1~Y16：Output electrode
4000、5000、7000：Three-dimensional semiconductor memory devices
4100：First perimeter circuit structure
4200、5200：Second perimeter line line structure
4300、7300：Array structure
925：First grid
926：Second grid
A、A1、A2、A3、A4、A5、B、B1、B2、B3、B4、C、D、 Logical value
X1’、X2’、X3’、X4’、X5’：First gate electrode
X6’、X7’、X8’、X9’：Second grid electrode
Embodiment
It is to propose that various embodiments are described in detail below, it is arranged at an array knot using three-dimensional logic array structure
Design between structure and a perimeter circuit structure, to reduce manufacturing cost.However, embodiment is as example only to illustrate, and
The scope of the invention to be protected will not be limited.In addition, the schema system in embodiment omits unnecessary element, to clearly show that this
The technical characterstic of invention.
Fig. 1 is refer to, it illustrates the signal of a three-dimensional logic array structure (3D logic array structure) 100
Figure.Three-dimensional logic array structure 100 includes semiconductor lamination 110, the input electrode 130 of two grid 121,122, one, two grids
Electrode 141,142 and an output electrode 150.Grid 121,122 is arranged on semiconductor laminated 110.Each grid 121,122
It is connected to gate electrode 141, one of 142.Input electrode 130 and output electrode 150 are arranged at semiconductor laminated 110
Relative both ends.
When grid 121,122 is applied in appropriate voltage respectively through gate electrode 141,142, a passage will be formed
In semiconductor laminated 110, and input electrode 130 and output electrode 150 will be electrically conducted.
For example, it refer to following table one.Logical value (logic value) A represents whether gate electrode 141 has and applied
Add appropriate voltage.If logical value A is " 0 ", gate electrode 141 is not applied to appropriate voltage；If logical value A is " 1 ",
Gate electrode 141 is applied in appropriate voltage.Similarly, logical value B represents whether gate electrode 142 has and is applied in appropriate electricity
Pressure.If logical value B is " 0 ", gate electrode 142 is not applied to appropriate voltage；If logical value B is " 1 ", gate electrode
142 are applied in appropriate voltage.
When gate electrode 141 and gate electrode 142 are applied in appropriate voltage (i.e. logical value A and B is all " 1 "), then
Output electrode 150 can obtain the value " V " inputted by input electrode 130.
Table one
| Input electrode 130 | Logical value A | Logical value B | Output electrode 150 |
| V | 0 | 0 | 0 |
| V | 0 | 1 | 0 |
| V | 1 | 0 | 0 |
| V | 1 | 1 | V |
Fig. 2 is refer to, it illustrates the schematic diagram of another three-dimensional logic array structure 200.Three-dimensional logic array structure 200 wraps
Include two semiconductor laminated 211,212, four 221,222,223,224, one input electrodes of grid, 230, four gate electrodes 241,
242nd, 243,244 and two output electrodes 251,252.Wherein the two of grid 221,222,223,224 are arranged at semiconductor and folded
On layer 211, one of 212.Each grid 221,222,223,224 is connected to gate electrode 241,242,243,244
One of.Input electrode 230 and output electrode 251, one of 252 are arranged at its of semiconductor laminated 211,212
One of opposite end.
When grid 221,222 is applied in an appropriate voltage respectively through gate electrode 241,242, a passage will shape
Into within semiconductor laminated 211, and input electrode 230 and output electrode 251 will electrically conduct.When grid 223,224 is saturating
When crossing gate electrode 243,244 and being applied in an appropriate voltage respectively, another passage will be formed at semiconductor laminated 212 it
It is interior, and input electrode 230 and output electrode 252 will electrically conduct.
For example, it refer to following table two.Logical value A represents whether gate electrode 241 has and is applied in appropriate voltage.
If logical value A is " 0 ", gate electrode 241 is not applied to appropriate voltage；If logical value A is " 1 ", the quilt of gate electrode 241
Apply appropriate voltage.Similarly, logical value B represents whether gate electrode 243 has and is applied in appropriate voltage.If logical value B
For " 0 ", then gate electrode 243 is not applied to appropriate voltage；If logical value B is " 1 ", gate electrode 243 is applied in suitably
Voltage.
Furthermore logical value(logical value A inverse value) represents whether gate electrode 242 has and is applied in appropriate voltage.
If logical value A is " 0 ", logical valueAppropriate voltage is applied in for " 1 " and gate electrode 242；If logical value A is " 1 ",
Logical valueAppropriate voltage is not applied to for " 0 " and gate electrode 242.Similarly, logical value(logical value B inverse value)
Represent whether gate electrode 244 has and be applied in appropriate voltage.If logical value B is " 0 ", logical valueFor " 1 " and grid electricity
Pole 244 is applied in appropriate voltage；If logical value B is " 1 ", logical valueIt is not applied to suitably for " 0 " and gate electrode 244
Voltage.
When gate electrode 241 and gate electrode 243 are applied in appropriate voltage, (i.e. logical value A and B is all " 1 ", then defeated
The value " V " inputted by input electrode 230 can be obtained by going out electrode 251.Similarly, when gate electrode 242 and gate electrode 244
Being applied in appropriate voltage, (i.e. logical value A and B is all " 0 ", then output electrode 252 can obtain defeated by the institute of input electrode 230
The value " V " entered.
Table two
Fig. 3 is refer to, it illustrates the schematic diagram of another three-dimensional logic array structure 300.Three-dimensional logic array structure 300 wraps
Include an input electrode X0,8 gate electrode X1~X8 and 16 output electrode Y1~Y16.
It refer to following table three.Logical value A represents whether gate electrode X1 has and is applied in appropriate voltage.If logical value A
For " 0 ", then gate electrode X1 is not applied to appropriate voltage；If logical value A is " 1 ", it is appropriate that gate electrode X1 is applied in
Voltage.Similarly, logical value B, C, D represents whether gate electrode X3, X5, X7 have and is applied in appropriate voltage respectively.If logic
Value B is " 0 ", then gate electrode X3 is not applied to appropriate voltage；If logical value B is " 1 ", gate electrode X3 is applied in suitably
Voltage.
Furthermore logical value(i.e. logical value A inverse value) represents whether gate electrode X2 has and is applied in appropriate voltage.
If logical value A is " 0 ", logical valueAppropriate voltage is applied in for " 1 " and gate electrode X2；If logical value A is " 1 ",
Logical valueAppropriate voltage is not applied to for " 0 " and gate electrode X2.Similarly, logical valueAnd(it is respectively
The inverse value of logical value B, C and D) represent whether gate electrode X4, X6, X8 have and be applied in appropriate voltage respectively.If logical value B
For " 0 ", then logical valueAppropriate voltage is applied in for " 1 " and gate electrode X4；If logical value A is " 1 ", logical value
Appropriate voltage is not applied to for " 0 " and gate electrode X4.
Each output electrode Y1~Y16 is be electrically connected at gate electrode X1~X8 with four contact C wherein four.Lift
For example, output electrode Y1 is to be electrically connected at gate electrode X1, X3, X5, X7 with four connection pad C.Output electrode Y2 is with four
Individual contact C is electrically connected at gate electrode X1, X3, X5, X8.Wherein four are selected from 8 gate electrode X1~X8, can there is 16
Kind selection mode.Wherein the four of gate electrode X1~X8 are electrically connected with each output electrode Y1~Y16 through four contact C
Selection mode and differ.
It is when gate electrode X1, X3, X5, X7 are all applied in appropriate voltage (i.e. logical value A, B, C, D is all " 1 "), then defeated
The value " V " inputted by input electrode X0 can be obtained by going out electrode Y1.Similarly, gate electrode X1, X3, X5, X8 is all applied in
Appropriate voltage (i.e. logical value A, B, C is all " 1 " and logical value D is " 0 "), then output electrode Y2 can be obtained by input electrode
The value " V " that X0 is inputted.
Table three
| X0 | A | B | C | D | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 | Y8 | Y9 | Y10 | Y11 | Y12 | Y13 | Y14 | Y15 | Y16 |
| V | 1 | 1 | 1 | 1 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 1 | 1 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 1 | 0 | 1 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 1 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 |
| V | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 |
| V | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 |
| V | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 |
| V | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 |
| V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V |
In figure 3, corresponding to four groups of logical value A andB andC andD and8 gate electrode X1~X8 and 1
Individual input electrode X0 can represent 16 output electrode Y1~Y16 value.Therefore, 9 input signals can obtain 16 it is defeated
Go out signal.Similarly, in order to obtain 2N-1~2NIndividual output signal, then need 2N+1 input signal.N is natural number.2N+1
Input signal corresponds to N groups gate electrode and 1 input electrode.Each group gate electrode includes 2 gate electrodes.
In figure 3, each group logical value has Liang Ge stratum, is, for example, " 0 " and " 1 ".In one embodiment, each group logical value
Can have M stratum, be, for example, " 0 ", " 1 " ..., " M-1 ".M logical value of each group gate electrode is mutual exclusion
(exclusive).M is the natural number more than 2.Therefore, if in order to obtain MN-1~MNIndividual output signal, only need MN+1 individual defeated
Enter signal.N and M is natural number.MN+1 input signal corresponds to N groups gate electrode and an input electrode.Each group grid
Electrode includes M gate electrode.
Fig. 4 is refer to, it illustrates the schematic diagram of another three-dimensional logic array structure 800.Three-dimensional logic array structure 800 wraps
Include an input electrode X0,6 gate electrode X1~X6 and 9 output electrode Y1~Y9.
It refer to following table four.Logical value A1 represents whether gate electrode X1 is applied in appropriate voltage.If logical value A1
For " 0 ", then gate electrode is not applied to appropriate voltage；If logical value A1 is " 1 ", gate electrode X1 is applied in appropriate electricity
Pressure.Similarly, logical value A2, A3, B1, B2 and B3 represents whether gate electrode X2, X3, X4, X5 and X6 are applied in suitably respectively
Voltage.In logical value A1, A2 and A3, only one logical value A1, A2 and A3 are " 1 ", and other are " 0 ".Patrolling
Collect in value B1, B2 and B3, only one logical value B1, B2 and B3 are " 1 ", and other are " 0 ".
Each output electrode Y1~Y9 be with two contact C be electrically connected at one of gate electrode X1~X3, with
One of gate electrode X4~X6.For example, output electrode Y1 is to be electrically connected at gate electrode X1 with two contact C
And X4.Output electrode Y2 is to be electrically connected at gate electrode X1 and X5 with two contact C.Selected from 3 gate electrode X1~X3
1 is selected, and selects the selection mode of 1 there are 9 kinds from gate electrode X4~6.
When gate electrode X1 and X4 are applied in appropriate voltage (i.e. logical value A1 and B1 is " 1 "), then output electrode Y1 can
To obtain the value " V " inputted by input electrode X0.Similarly, (patrolled when gate electrode X1 and X5 are applied in appropriate voltage
It is " 1 " to collect value A1 and B2), then output electrode Y2 can obtain the value " V " inputted by input electrode X0.
Table four
| X0 | A1 | A2 | A3 | B1 | B2 | B3 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 | Y8 | Y9 |
| V | 1 | 0 | 0 | 1 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 0 | 0 | 0 | 1 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 | 0 |
| V | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 | 0 |
| V | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 | 0 |
| V | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 | 0 |
| V | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 | 0 |
| V | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V | 0 |
| V | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | V |
In Fig. 4, corresponding to 6 gate electrode X1~X6 two groups of logical values A1, A2, A3；B1, B2, B3 and 1 input
Electrode X0 can represent 9 output electrode Y1~Y9 value.Therefore, 7 input signals can obtain 9 output signals.Class
As, in order to obtain 3N-1~3NIndividual output signal, then need 3N+1 input signal.N is natural number.3N+1 input signal
Corresponding to N groups gate electrode and 1 input electrode.Each group gate electrode includes 3 gate electrodes.
It refer to following table five.Corresponding to 3 groups of logical values A1, A2, A3, B1, B2, B3 and C1 of 9 gate electrodes, C2,
C3 and 1 input electrode X0 can represent 27 output electrodes.In order to obtain 27 output signals, it is only necessary to which 33+1 defeated
Enter signal.
Table five
Above-mentioned three-dimensional logic array structure 100,200 and 300 and similar structures can be used in three-dimensional semiconductor memory devices, with
Reduce the number of the circuit of perimeter circuit structure.Fig. 5 is refer to, it illustrates the schematic diagram of a three-dimensional semiconductor memory devices 4000.Three
Tieing up semiconductor device 4000 includes one array architecture 4300, one first perimeter circuit structure 4100, one second perimeter line line structure
4200 and a three-dimensional logic array structure 400.Array structure 4300 is to trapped electrons to store data.For example, array
Structure 4300 can be nor gate flash array (NOR flash array) or a dynamic ram array (DRAM
array).First perimeter circuit structure 4100 can be a word line structure (word line structure).For example, word
Cable architecture can include some decoders (decoders).Second perimeter line line structure 4200 can be a bit line structure (bit
line structure).For example, bit line structure can include some page buffers (page buffer).
Array structure 4300 has 16 the first contact C1 and 16 the second contact C2.First contact C1 is located at the first side,
Second contact C2 is located at the second side.Array structure 4300 has the data of 256 (i.e. 16*16) positions.Three-dimensional logic array structure 400
Similar to Fig. 3 three-dimensional logic array structure 300, something in common is not repeated to describe.Three-dimensional logic array structure 400 is arranged at
Between the perimeter circuit structure 4100 of array structure 4300 and first, to reduce the number of the circuit of the first perimeter circuit structure 4100
Mesh.
By using three-dimensional logic array structure 400, the quantity of the circuit of the first perimeter circuit structure 4100 is reduced by 16
To 9.Similarly, if the first contact C1 number be Y (between MN-1To MNBetween), three-dimensional logic array structure 400 has N groups
Gate electrode, 1 input electrode and Y output electrode, each group gate electrode have M gate electrode, then the first perimeter circuit
The number of the circuit of structure 4100 can be reduced to MN+1 by Y.Consequently, it is possible to manufacturing cost can be effectively reduced.
Fig. 6 is refer to, it illustrates the schematic diagram of another three-dimensional semiconductor memory devices 5000.In one embodiment, it is three-dimensional partly to lead
Body device 5000 can further include another three-dimensional logic array structure 500.Three-dimensional logic array structure 500 is arranged at array structure
4300 and second between perimeter line line structure 5200, to reduce the number of the circuit of the second perimeter line line structure.
If the number of the second contact is Z (between TS-1To TSBetween), three-dimensional logic array structure 500 has S groups grid electricity
Pole, 1 input electrode and Z output electrode, each group gate electrode have T gate electrode, then the second perimeter line line structure 500
The number of circuit TS+1 can be reduced to by Z.Consequently, it is possible to manufacturing cost can be lowered.
Above-mentioned three-dimensional logic array structure 100,200,300,400 and 500 can be a pair of grid array structure or
It is a single grid array structure.For example, Fig. 1 and Fig. 2 is refer to, three-dimensional logic array structure 100,200 is with bigrid
Explained exemplified by array structure.Fig. 7 is refer to, it illustrates the schematic diagram of three-dimensional logic array structure 600.For example, it is three-dimensional
Logic array architecture 600 is explained by taking single grid array structure as an example.
Fig. 8 is refer to, it illustrates the schematic diagram of another three-dimensional semiconductor memory devices 7000.In one embodiment, it is three-dimensional partly to lead
The array structure 7300 of body device 7000 can be that a NAND gate is serial (NAND string).Three-dimensional logic array structure 700 can
With controlling the array structure 7300 of NAND gate string.Three-dimensional logic array structure 700 is similar to Fig. 3 three-dimensional logic array junctions
Structure 300, something in common are not repeated to describe.In Fig. 3 three-dimensional logic array structure 300, each group gate electrode X1~X8's
Two logical values are opposite.In Fig. 8 three-dimensional logic array structure 700, each group gate electrode X1~X8 two logical values
It is and not always opposite.For example, all gate electrode X1~X8 can be applied in an appropriate voltage, so that all is defeated
Go out electrode Y1~Y16 and be applied in the conducting voltage (pass voltage) inputted by input electrode X0.Then, it is suitable by applying
When voltage in wherein the four of gate electrode X1~X8, make some selected NAND gate (NAND) that a reading can be applied in
Power taking pressure (read voltage) or a program voltage (program voltage).
Fig. 9 is refer to, it illustrates the schematic diagram of another three-dimensional logic array structure 900 '.In one embodiment, three-dimensional is patrolled
Double-grid structure can be used by collecting array 900 '.Three-dimensional logic array 900 ' includes 3 semiconductor laminated 910 and 4 grids
921st, 922,923 and 924.Each semiconductor laminated 910 are arranged between wherein the two of grid 921,922,923,924.When
Grid 922,923 is applied in an appropriate positive voltage "+V " and grid 921,922 and is applied in a negative voltage "-V "；One passage will
It is formed in semiconductor laminated 910 between grid 922 and 923.
Figure 10 is refer to, it illustrates the schematic diagram of another three-dimensional logic array structure.Three-dimensional logic array structure 900 includes
5 first gate electrode X1 '~X5 ', 21 first electrodes, 925,4 second electrode X6 '~X9 ', 21 second grids 926 and
20 semiconductor laminated Y1~Y20.Each first grid 925 is sequentially connected to these first gate electrodes X1 '~X5 ' wherein
One of.For example, the order of connection of 21 first grids 925 for " X5 ', X1 ', X2 ', X3 ', X4 ', X5 ', X1 ', X2 ',
X3’、X4’、X5’、X1’、X2’、X3’、X4’、X5’、X1’、X2’、X3’、X4’、X5’」。
Each second grid 926 is sequentially connected to one of these second grid electrodes X6 '~X9 '.For example,
The order of connection of 21 second grids 926 for " X9 ', X6 ', X7 ', X8 ', X9 ', X6 ', X7 ', X8 ', X9 ', X6 ', X7 ', X8 ',
X9’、X6’、X7’、X8’、X9’」。
Each semiconductor laminated 910 between wherein the two of these first grids 925, and are located at these second grids
Between wherein the two of 926.When two first grids 925 and two second grids 926 that are adjacent to a certain semiconductor laminated 910
It is applied in an appropriate voltage "+V ", a passage will be formed at this in semiconductor laminated 910.
Each first gate electrode X1 '~X5 ' be applied in a positive voltage "+V ", a negative voltage "-V " or a ground voltage "
0 ", each second grid electrode X6 '~X9 ' is applied in a positive voltage "+V ", a negative voltage "-V " or a ground voltage " 0 ".Please
With reference to following table six.If logical value is " 1 ", first gate electrode X1 ' is applied in positive voltage "+V "；If logical value A1 for "-
1 ", then first gate electrode X1 ' be applied in negative voltage "-V "；If logical value A1 is " 0 ", first gate electrode X1 ' is applied in
Ground voltage " 0 ".Similarly, logical value A2, A3, A4 and A5 represents that first gate electrode X2 '~X5 ' is applied in positive electricity respectively
Press "+V ", negative voltage "-V " or ground mat pressure " 0 ".Logical value B1, B2, B3 and B4 represent second grid electrode X6 '~X9 ' respectively
It is applied in positive voltage "+V ", negative voltage "-V " or ground mat pressure " 0 ".
5 first gate electrode X1 '~X5 ' apply respectively "+V ,-V, 0 ,-V ,+V " or "+V ,+V ,-V, 0 ,-V " or "-
V ,+V ,+V ,-V, 0 " or " 0 ,-V ,+V ,+V ,-V " or "-V, 0 ,-V ,+V ,+V ".4 second grid electrode X6 '~X9 ' is respectively
It is applied in "+V ,-V ,-V ,+V " or "+V ,+V ,-V ,-V " or "-V ,+V ,+V ,-V " or "-V ,+V ,+V ,-V ".
When first gate electrode X1 '~X5 ' is applied in "-V ,+V ,+V,-V, 0 " (i.e. logical value A1~A5 for " -1,1,1, -
1st, 0 ", and second grid electrode X6 '~X9 ' is applied in "-V ,+V ,+V,-V " (i.e. logical value B1~B4 is " -1,1,1, -1 ", then
One passage will be formed among semiconductor laminated Y3.Similarly, when first gate electrode X1 '~X5 ' is applied in "+V ,+V ,-
V, 0,-V " (i.e. logical value A1~A5 be " 1,1, -1,0, -1 " and second grid electrode X6 '~X9 ' be applied in "-V ,+V ,+V, -
(i.e. logical value B1~B4 is " -1,1,1, -1 " to V ", then a passage will be formed among semiconductor laminated Y7.
Table six
| Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 | Y8 | Y9 | Y10 | Y11 | Y12 | Y13 | Y14 | Y15 | Y16 | Y17 | Y18 | Y19 | Y20 | |
| A1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 |
| A2 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 |
| A3 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 |
| A4 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 |
| A5 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 | 1 | -1 | 0 | -1 | 1 |
| B1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 |
| B2 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 |
| B3 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 |
| B4 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 | 1 | -1 | -1 | 1 |
In one embodiment, the quantity of first grid 925 is same as second grid 926.The quantity of first gate electrode can
To be M, the quantity of second grid electrode can be N, and the quantity of output electrode can be Y.The quantity of first grid 925 be equal to or
Less than M*N+1.It is natural number that Y, which is equal to or less than M*N, M and N, and M and N is more than or equal to 4, and M and N greatest common factor (G.C.F.)
(greatest common divisor) is 1.
In summary, although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.This hair
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, protection scope of the present invention is worked as and is defined depending on what appended claims scope was defined.
Claims (20)
1. a kind of three-dimensional semiconductor memory devices, including：
One array architecture, to store data, the array structure has Y the first contacts, and these Y the first contacts are located at the battle array
One first side of array structure, wherein Y is between MN-1To MNBetween, Y, M and N are natural number, and M is more than or equal to 2；
One first perimeter circuit structure；And
One first three-dimensional logic array structure, it is arranged between the array structure and the first perimeter circuit structure, the one or three
Dimension logic array architecture includes：
N group first gate electrodes, wherein each group first gate electrode have M first gate electrode；
One first input electrode；And
Y the first output electrodes, wherein these Y the first output electrodes connect these Y the first contacts, these MN individual first
Gate electrode and the first input electrode are connected to the first perimeter circuit structure.
2. three-dimensional semiconductor memory devices according to claim 1, wherein M are two logics of 2 and each group first gate electrode
It is opposite to be worth (logic value).
3. three-dimensional semiconductor memory devices according to claim 1, wherein M are more than M logic of 2 and each group first gate electrode
It is worth for mutual exclusion (exclusive).
4. three-dimensional semiconductor memory devices according to claim 1, wherein respectively first output electrode connection each group first grid
One of electrode first gate electrode.
5. three-dimensional semiconductor memory devices according to claim 1, wherein the three-dimensional logic array structure are a thin film transistor (TFT)
With door grid array structure (TFT AND gate array structure).
6. three-dimensional semiconductor memory devices according to claim 1, wherein the three-dimensional logic array structure are a pair of grid array
Structure (double gate array structure).
7. three-dimensional semiconductor memory devices according to claim 1, wherein the three-dimensional logic array structure are a single grid array
Structure (single gate array structure).
8. three-dimensional semiconductor memory devices according to claim 1, the wherein array structure are a nor gate flash array (NOR
Flash array) or a dynamic ram array (DRAM array).
9. three-dimensional semiconductor memory devices according to claim 1, the wherein array structure are the serial (NAND of a NAND gate
string)。
10. three-dimensional semiconductor memory devices according to claim 1, the wherein array structure have more Z the second contacts, these
Z the second contacts are located at one second side of the array structure, and Z is between TS-1And TSBetween, Z, T and S are natural number, T be more than or
Equal to 2, and three-dimensional semiconductor memory devices further include：
One second perimeter line line structure；And
One second three-dimensional logic array structure, including：
S group second grid electrodes, wherein each group second grid electrode have T second grid electrode；
One second input electrode；And
Z the second output electrodes, wherein these Z the second output electrodes connect these Z the second contacts, these TS individual second
Gate electrode and second input electrode connect the second perimeter line line structure.
11. a kind of three-dimensional logic array structure, being arranged between one array architecture and a perimeter circuit structure, the array structure is used
To store data, the three-dimensional logic array structure includes：
N group gate electrodes, wherein each group gate electrode have M gate electrode；
One input electrode；And
Y output electrode, wherein these Y output electrode connect Y contact of the array structure, and these Y contact is located at should
The side of array structure, these MN gate electrode and input electrode connect the perimeter circuit structure, and Y is between MN-1To MN
Between, Y, M and N are natural number, and M is more than or equal to 2.
12. three-dimensional logic array structure according to claim 11, wherein M is 2, and two logics of each group gate electrode
It is worth to be opposite.
13. three-dimensional logic array structure according to claim 11, wherein M is more than 2, and M of each group gate electrode patrol
It is mutual exclusion (exclusive) to collect value.
14. three-dimensional logic array structure according to claim 11, wherein respectively output electrode connection each group gate electrode
One of gate electrode.
15. three-dimensional logic array structure according to claim 11, wherein the three-dimensional logic array structure are that a film is brilliant
Body Guan Yumen grid arrays structure (TFT AND gate array structure).
16. three-dimensional logic array structure according to claim 11, wherein the three-dimensional logic array structure are a bigrid
Array structure (double gate array structure).
17. three-dimensional logic array structure according to claim 11, wherein the three-dimensional logic array structure are a single grid
Array structure (single gate array structure).
18. a kind of three-dimensional logic array structure, including：
M first gate electrode, respectively the first gate electrode be applied in a positive voltage, a negative voltage or a ground voltage；
Multiple first grids, respectively the first grid be linked in sequence in one of these first gate electrodes；
N number of second grid electrode, respectively the second grid electrode be applied in the positive voltage, the negative voltage or the ground voltage；
Multiple second grids, respectively the second grid be connected to one of these second grid electrodes；And
Y is semiconductor laminated, and respectively this is semiconductor laminated between wherein the two of these first grids and these second grids
Wherein two between；
Wherein the quantity of these first grids is equal to the quantity of these second grids, and the quantity of these first grids is equal to or less than
It is natural number that M*N+1, Y, which are equal to or less than M*N, M and N, and M and N is more than or equal to 4, and M and N greatest common factor (G.C.F.) (greatest
Common divisor) it is 1.
19. three-dimensional logic array structure according to claim 18, wherein M is 4, these M first gate electrode system quilt
Apply "+V ,-V ,-V ,+V " or "+V ,+V ,-V ,-V " or "-V ,+V ,+V ,-V " respectively.
20. three-dimensional logic array structure according to claim 18, wherein M is more than 4, these M first grid array system
Be applied in respectively "+V ,-V, 0 ..., 0 ,-V ,+V " or "+V ,+V ,-V, 0 ..., 0 ,-V " or "-V ,+V ,+V ,-V, 0 ..., 0 ",
Or " 0 ..., 0 ,-V ,+V ,+V ,-V " or "-V, 0 ..., 0 ,-V ,+V ,+V ".
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