CN104484160A - Instruction scheduling and register allocation method on optimized clustered VLIW (Very Long Instruction Word) processor - Google Patents

Abstract

The invention discloses an optimized instruction scheduling and register allocation method on a clustered VLIW processor, which includes two stages: in the first stage, a unified algorithm is used to perform the first-pass instruction scheduling and register allocation for all basic blocks ; In the second stage, according to the length of the longest path to which the basic block belongs and the highest execution frequency, perform instruction rescheduling and register reallocation on the basic block with register overflow. The invention has the advantages of wide application range, good performance optimization effect, can effectively reduce the longest execution time of the program in the real-time system, and the like.

Description

An Optimized Instruction Scheduling and Register Allocation Method on Clustered VLIW Processor

technical field

The invention mainly relates to the technical field of processor compilation optimization, in particular to an optimized instruction scheduling and register allocation method suitable for clustered VLIW processors.

Background technique

The longest execution time of the program is one of the important bases to measure the design of embedded real-time system, and all time constraints must be met to ensure the correctness of the real-time system. The maximum execution time of a program has a significant impact on assigning a feasible schedule to the program. The running time of the program is different because different branches may be executed during the running of the program, and the longest running time of the program refers to the longest running time of the program on the target platform. A program cannot be assigned a feasible schedule if its maximum execution time is greater than the time limit of the real-time system. If the maximum execution time of a program can be reduced, it is more likely that the program will be assigned a feasible schedule. Therefore, minimizing the maximum execution time of a program is an important issue.

For embedded systems with sub-cluster VLIW architecture, instruction scheduling and register allocation are important components in an optimizing compiler, which have a great impact on the longest execution time of a program. Traditionally, register allocation and instruction scheduling are performed separately. However, performing each phase separately causes phase order issues, making the compiled code less optimal. Clustering is an effective technique to improve the scalability and energy consumption of VLIW processors. However, clustering VLIW processors increases the difficulty of instruction scheduling and register allocation. First, when variables are passed to different clusters, new active intervals are dynamically generated, and multiple registers on different clusters are required to hold copies of the same variable. Second, the precise live range of a variable depends on when its first definition and last used associated instruction was dispatched, and cannot be determined by traditional live range analysis for static code. Third, improper inter-cluster instruction allocation can lead to unnecessary inter-cluster communication, which increases the scheduling time of basic blocks.

Contents of the invention

The technical problem to be solved by the present invention is that: aiming at the technical problems existing in the prior art, the present invention provides an optimized analysis system with wide application range, good performance optimization effect, and effective reduction of the longest execution time of programs in real-time systems. Instruction Scheduling and Register Allocation Methods on Cluster VLIW Processors.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

An optimized instruction scheduling and register allocation method on a clustered VLIW processor, including two stages: in the first stage, a unified algorithm is used to perform the first-pass instruction scheduling and register allocation for all basic blocks; in the second stage In the first stage, according to the length of the longest path to which the basic block belongs and the highest execution frequency, instruction rescheduling and register reallocation are performed on the basic block with register overflow.

As a further improvement of the present invention: the steps in the first stage are:

(1) Construct the authorized control flow graph G of the program P; the program P is represented by the authorized control flow graph G=(V,E,W), where V={B ₁ ,B ₂ ,...,B _n : is the program The basic block of , E={(B _i , B _j ): B _j depends on the control of B _i }, W={w _i : w _i is the execution time of basic block B _i };

(2) Perform instruction scheduling and register allocation for each basic block B _i in reverse order according to the unified algorithm.

As a further improvement of the present invention: in the step (2), the unified algorithm combines the incremental register allocation method with the priority-based instruction scheduling method; the instruction scheduling method schedules all basic blocks according to the reverse order, and according to The instruction priority in each basic block schedules each instruction; the priority of each instruction considers the inter-instruction delay and processor resource constraints. During the scheduling process, the instruction priority is dynamically updated to reduce register pressure.

As a further improvement of the present invention: the steps in the second stage are:

(1) Update the weight w _i of each basic block B _i in the control flow graph G;

(2) Construct an acyclic graph DAG(G); transform the authorized control flow graph G into an acyclic graph DAG(G)=(V',E',W'), where V'=V is the basic block of P Set, E'=E–{(B _i ,B _j ):(B _i ,B _j ) is a return edge}, which is the set of edges in DAG(G), W'={w' _i :w' _i is the weight of node B _i , w' _i =w _i *N(B _i ), w _i is the execution time of B _i , N(B _i ) is the highest execution frequency of B _i };

(3) Repeat the following steps until the longest path of DAG(G) can no longer be shortened;

(3a) Calculate the longest path of DAG(G);

(3b) Find the basic block B _k with the highest execution frequency among the basic blocks with register overflow on the longest path;

(3c) performing instruction rescheduling and register reallocation on B _k ;

(3d) Update the weight of node B _k in DAG(G).

As a further improvement of the present invention: in the second stage, the basic block B _i with the highest execution frequency on the longest path of DAG(G) is selected each time, and the following steps are performed for each active cycle R _j overflowed to the memory Reduce overflow:

1. Find out the active cycle R _k that has the least impact on the longest path, and satisfy the condition: the cycle of R _k is greater than the cycle of R _j , and the register of R _k is assigned to R _j ;

II, adding the overflow code of R _k , and rescheduling all affected instructions;

III. Recalculate the execution time of each basic block affected by R _k .

As a further improvement of the present invention: in the step I, in order to find the active period R _k that satisfies the conditions, it is carried out by introducing a new graph DAG (G, k); the graph DAG (G, k) is DAG (G), the length of any path of DAG(G,k) is not greater than k+l _min , where l _min is the length of the shortest path of DAG(G); the value of k is set to (l _max -l _min )/2, where l _max is the length of the longest path of DAG(G); after constructing DAG(G,(l _max -l _min )/2), the priority rank of each active cycle R _s is calculated as follows: rank (R _s )=n1(R _s )/n(R _s ), where n1(R _s ) is the total number of references to R _s in all basic blocks in DAG(G,(l _max -l _min )/2), n(R _s ) is the total number of used R _s in all basic blocks; the chosen R _k is the active cycle with the highest priority on the longest path.

Compared with the prior art, the present invention has the advantages of:

1. The method for instruction scheduling and register allocation on the optimized clustered VLIW processor of the present invention, before executing instruction rescheduling and register reallocation, not only performs the first pass of instruction scheduling, but also performs the first pass of register allocation. Compared with the traditional method, which only performs the first-pass instruction scheduling without considering register allocation, the longest path obtained by the present invention is more accurate and reliable.

2. The instruction scheduling and register allocation method on the clustered VLIW processor optimized by the present invention, in the instruction rescheduling and register redistribution process, the basic block with the highest execution frequency on the longest path is selected for priority processing, compared with the traditional method selection In view of the basic block with the highest execution frequency on the longest path having the greatest influence on reducing the length of the longest path, the selection strategy of the present invention is obviously better.

3. The instruction scheduling and register allocation method on the clustered VLIW processor optimized by the present invention, when the register pressure is very high, the present invention assigns a dynamic priority to each instruction of the basic block to reduce instruction-level parallelism, thereby reducing register overflow. Traditional methods do not consider reducing instruction-level parallelism, which may lead to multiple register overflows. The invention integrates register allocation and instruction scheduling into one stage, and can generate performance-optimized compiled codes.

Description of drawings

Fig. 1 is a schematic flow chart of the present invention.

Fig. 2 is a right control flow graph G=(V, E, W) of the present invention in a specific application.

Fig. 3 is an acyclic graph DAG(G)=(V', E', W') of the present invention in a specific application.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 1, the instruction scheduling and register allocation method on a kind of optimized sub-clustering VLIW processor of the present invention, aim at minimizing the longest execution time of the program, it comprises two phases: in the first phase, Use a unified algorithm to perform the first-pass instruction scheduling and register allocation for all basic blocks; in the second stage, according to the length of the longest path and the highest execution frequency to which the basic block belongs, perform instruction rescheduling on the basic blocks with register overflow and register reallocation.

During specific application, the detailed flow process of the present invention is:

(1) Construct the privileged control flow graph G of program P, where w _i is undefined.

(2) Perform instruction scheduling and register allocation for each basic block B _i in reverse order according to the unified algorithm.

(3) Update the weight w _i of each basic block B _i in the control flow graph G.

(4) Construct an acyclic graph DAG(G).

(5) Repeat the following steps until the longest path of DAG(G) can no longer be shortened:

(5a) Calculate the longest path of DAG(G).

(5b) Find the basic block B _k with the highest execution frequency among the basic blocks with register overflow on the longest path.

(5c) Perform instruction rescheduling and register reallocation on B _k .

(5d) Update the weight of node B _k in DAG(G).

In a specific application example, as shown in Figure 2, a program P is represented by an authorized control flow graph G=(V, E, W), where V={B ₁ , B ₂ ,...,B _n : is the basic Block, E={(B _i , B _j ): B _j controls dependence on B _i }, W={w _i : w _i is the execution time of basic block B _i }. As shown in Figure 3, convert G into an acyclic graph (Directed Acyclic Graph) DAG(G)=(V', E', W'), where V'=V is the basic block set of P, E'=E –{(B _i ,B _j ):(B _i ,B _j ) is a return edge}, which is the set of edges in DAG(G), W'={w' _i :w' _i is the weight of node B _i value, w' _i =w _i *N(B _i ), where w _i is the execution time of B _i , and N(B _i ) is the highest execution frequency of B _i }.

In the above steps, in the first stage, the unified algorithm combines the incremental register allocation method with the priority-based instruction scheduling method. The instruction scheduling method schedules all basic blocks in reverse order, and schedules each instruction according to the instruction priority in each basic block. The priority of each instruction takes into account inter-instruction latency and processor resource constraints. During scheduling, instruction priorities are dynamically updated to reduce register pressure. For the schedulable instruction with the highest priority, the instruction is allocated to the functional units on the cluster, and the incremental register allocation method is called to allocate the physical register to the virtual register of the instruction. Inter-cluster instruction allocation needs to consider the start time of the instruction and the register pressure of each cluster.

In the above steps, the goal of the second stage is to minimize the register overflow on the longest path through instruction rescheduling and register reallocation. Each time the basic block B _i with the highest execution frequency on the longest path of DAG(G) is selected, the following steps are performed for each active cycle R _j spilled into memory to reduce overflow:

I. Find the active cycle R _k that has the least impact on the longest path, and satisfy the condition: the cycle of R _k is greater than the cycle of R _j , and assign the register of R _k to R _j .

II. Add the overflow code of R _k , and reschedule all affected instructions.

III. Recalculate the execution time of each basic block affected by R _k .

In the above step I, in order to find the active period R _k that satisfies the conditions, a new graph DAG(G,k) is introduced in this embodiment. DAG(G,k) is a subgraph of DAG(G), and the length of any path of DAG(G,k) is not greater than k+l _min , where l _min is the length of the shortest path of DAG(G). The value of k is set to (l _max -l _min )/2, where l _max is the length of the longest path in DAG(G). After constructing DAG(G,(l _max -l _min )/2), calculate the priority rank of each active period R _s as follows: rank(R _s )=n1(R _s )/n(R _s ), where n1(R _s ) is the total number of references to R _s in all basic blocks in DAG(G,(lmax-l _min )/2), and n(R _s ) is the total number of used R _s in all basic blocks. The R _k selected by the present invention is the active cycle with the highest priority on the longest path.

The above are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (6)

1. instruction scheduling and register allocation method on an optimized sub-clustering VLIW processor, it is characterized in that, comprise two stages: in the first stage, use unified algorithm to carry out first pass instruction scheduling and all basic blocks Register allocation; in the second stage, according to the length of the longest path and the highest execution frequency to which the basic block belongs, instruction rescheduling and register reallocation are performed on the basic block with register overflow. 2. instruction scheduling and register allocation method on the clustered VLIW processor of optimization according to claim 1, is characterized in that, the step of described first stage is: (1) Construct the authorized control flow graph G of the program P; the program P is represented by the authorized control flow graph G=(V,E,W), where V={B ₁ ,B ₂ ,...,B _n : is the program The basic block of , E={(B _i , B _j ): B _j depends on the control of B _i }, W={w _i : w _i is the execution time of basic block B _i }; (2) Perform instruction scheduling and register allocation for each basic block B _i in reverse order according to the unified algorithm. 3. instruction scheduling and register allocation method on the clustered VLIW processor of optimization according to claim 2, it is characterized in that, in described step (2), unified algorithm will increase the register allocation method and the instruction based on priority The scheduling methods are combined; the instruction scheduling method schedules all basic blocks in reverse order, and schedules each instruction according to the priority of instructions in each basic block; the priority of each instruction takes into account inter-instruction delay and processor resources Constraints, instruction priorities are dynamically updated during scheduling to reduce register pressure. 4. instruction scheduling and register allocation method on the clustered VLIW processor of optimization according to claim 2 or 3, is characterized in that, the step of described second stage is: (1) Update the weight w _i of each basic block B _i in the control flow graph G; (2) Construct an acyclic graph DAG(G); transform the authorized control flow graph G into an acyclic graph DAG(G)=(V',E',W'), where V'=V is the basic block of P Set, E'=E–{(B _i ,B _j ):(B _i ,B _j ) is a return edge}, which is the set of edges in DAG(G), W'={w' _i :w' _i is the weight of node B _i , w' _i =w _i *N(B _i ), w _i is the execution time of B _i , N(B _i ) is the highest execution frequency of B _i }; (3) Repeat the following steps until the longest path of DAG(G) can no longer be shortened; (3a) Calculate the longest path of DAG(G); (3b) Find the basic block B _k with the highest execution frequency among the basic blocks with register overflow on the longest path; (3c) performing instruction rescheduling and register reallocation on B _k ; (3d) Update the weight of node B _k in DAG(G). 5. instruction scheduling and register allocation method on the optimized sub-clustering VLIW processor according to claim 4, is characterized in that, in the second stage, the execution frequency is the highest on the longest path of DAG (G) selected at every turn For a basic block B _{i of} , for each active cycle R _j that is spilled into memory, the following steps are performed to reduce the overflow: 1. Find out the active cycle R _k that has the least impact on the longest path, and satisfy the condition: the cycle of R _k is greater than the cycle of R _j , and the register of R _k is assigned to R _j ; II, adding the overflow code of R _k , and rescheduling all affected instructions; III. Recalculate the execution time of each basic block affected by R _k . 6. instruction scheduling and register allocation method on the optimal sub-clustering VLIW processor according to claim 5, is characterized in that, in described step 1, in order to find the active cycle R _k that satisfies the condition, by introducing a new The graph DAG (G, k) is performed; the graph DAG (G, k) is a subgraph of DAG (G), and the length of any path of DAG (G, k) is not greater than k+l _min , where l _min is the length of the shortest path of DAG(G); the value of k is set to (l _max -l _min )/2, where l _max is the length of the longest path of DAG(G); in constructing DAG(G,(l _max - After l _min )/2), calculate the priority rank of each active period R _s as follows: rank(R _s )=n1(R _s )/n(R _s ), where n1(R _s ) is DAG(G, The total number of references to R _s in all basic blocks in (l _max -l _min )/2), n(R _s ) is the total number of used R _s in all basic blocks; the selected R _k is the priority on the longest path Maximum active period.