CN104462729A - Layout method for anti-fuse field-programmable gate array - Google Patents

Abstract

The invention discloses a layout method for an anti-fuse field-programmable gate array. The layout method for the anti-fuse field-programmable gate array comprises the steps that (1) first layout which comprises N nets and formed by connecting M units through horizontal nets and vertical nets is established; (2) the cost of the first layout is obtained; (3) a part of units in the M units are selected to be moved, and the cost of second layout is obtained according to the step (1) and the step (2); (4) the cost of the second layout is compared with that of the first layout, the first layout is reserved when the cost of the second layout is higher than that of the first layout, the first layout is replaced by the second layout when the cost of second layout is lower than that of the first layout, layout is conducted repeatedly till at least movement is conducted M times, and the optimum layout is determined. According to the layout method for the anti-fuse field-programmable gate array, the layout speed of the anti-fuse field-programmable gate array is greatly increased, and layout results are optimized.

Description

A kind of layout method of antifuse series on-site programmable gate array

Technical field

The present invention relates to integrated circuit fields, particularly a kind of layout method of antifuse series on-site programmable gate array.

Background technology

Field programmable gate array (Field Programmable Gate Array, FPGA) is the product further developed on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, overcomes again the shortcoming that original programming device gate circuit number is limited.Fpga chip layout mainly for be the layout of logical block (being called CELL in antifuse series, i.e. unit) on chip and the annexation between them, for each logical block finds rational position.

Three kinds of common at present FPGA are SRAM, Flash and anti-fuse FPGA respectively.And the placement algorithm of main flow is mainly developed for the FPGA of SRAM series and is applied.Because chip structure exists larger difference, the placement algorithm of main flow exists in the application of the FPGA to antifuse series that efficiency is low, layout result is unreasonable, to distinct disadvantage such as the pressure of wiring are larger.

Existing layout method be by initial layout, iteration carry out logical block movement, check the steps such as layout result and find layout result, the method is when antifuse Series FPGA chip application, iteration holding time is long, result of calculation is unreasonable, and layout speed is slow, and layout result is undesirable.

Summary of the invention

In view of the foregoing defects the prior art has, the present invention proposes a kind of layout method of antifuse field programmable gate array, the method comprises:

1) create and to be connected by horizontal gauze the first layout comprising N number of gauze that M unit formed with vertical gauze, wherein,

For the interconnection resource of the horizontal direction in field programmable gate array chip and vertical direction sets relevant parameter β x and β y respectively, wherein β y< β x;

Optional two unit connect into gauze i, according to horizontal gauze length and the vertical gauze length of gauze i, set horizontal gauze cost frame bbx and vertical gauze cost frame bby, 1≤i≤N;

According to the fan-out line netting index amount of each unit in described gauze i, determine fan-out cost fanout (i)=bbx × bby × Δ I of fan-out gauze cost gain delta I and described gauze i;

2) cost of described first layout is obtained;

I-th gauze cost value is determined with the horizontal gauze cost frame of β y, described gauze i with fan-out cost fanout (i) of vertical gauze cost frame bbx and bby, described gauze i with the interconnection resource parameter beta x of vertical direction according to described horizontal direction, wherein, i-th gauze cost value is directly proportional to bbx, bby and fanout (i), be inversely proportional to β x and β y

Until N root gauze from first gauze, each gauze cost value is added, draws the cost of the first layout;

3) a part of unit chosen in M unit moves, according to described step 1), 2) obtain the cost of the second layout;

4) cost of the cost of described second layout with described first layout is compared, wherein,

When the cost of the second layout is greater than the cost of the first layout, retain the first layout;

When the cost of the second layout is less than the cost of the first layout, the second layout is utilized to substitute the first layout;

5) utilize step 3) choose except described a part of unit residue unit in a part of unit move, obtain the 3rd layout cost;

6) step 4 is utilized), the 3rd layout cost is compared with the second layout cost, determines reservation second layout or utilize the 3rd layout to substitute the second layout;

7) step 5 is repeated) and 6), until perform at least M movement, determine initial layout.

The present invention is by introducing cost determination methods, and comparison mechanism, determination preferably antifuse Series FPGA initial layout that can be relatively reasonable, and based on the direct layout of this initial layout.

In some embodiments, the computing formula of the cost of described first layout is:

$\cos t={\mathrm{\&Sigma;}}_{i=1}^{\mathrm{Nnet}.}(\frac{\mathrm{bbx}\&CenterDot;\mathrm{fanout}\left(i\right)}{\mathrm{\&beta;x}}+\frac{\mathrm{bby}\&CenterDot;\mathrm{fanout}\left(i\right)}{\mathrm{\&beta;y}}).$

Should be understood that this formula just schematically reacts layout cost; non-essential accurately corresponding cost itself; to one skilled in the art; can change the parameter of above-mentioned formula; or other amendment or computing is carried out to the relation between parameter; such as increase a cost offset, these all belong to the invention design, within protection scope of the present invention.

Further, on the basis of above-mentioned initial layout, comparison mechanism can be optimized, carry out a movement taken turns again, by the expansion of sample space, more reasonably can determine preferably antifuse Series FPGA layout.

Specifically: in above-mentioned steps 7) also can comprise afterwards:

8) mobile acceptance probability rat is set _succ, 0<rat _succ<1;

9) a part of unit chosen in M unit in described initial layout moves, according to described step 1), 2) obtain the first cost moving layout;

10) cost that described first moves layout is compared with 0 with the difference of the cost of described initial layout, wherein,

When difference is less than 0, utilizes first to move layout and substitute initial layout;

When difference is greater than 0, calculate the first movement probability, when the first movement probability rat (1) is greater than mobile acceptance probability rat _succtime, utilize first to move layout and substitute initial layout; When the first movement probability is less than mobile acceptance probability rat _succtime, retain initial layout,

Wherein, described first movement probability is according to following formulae discovery:

rat＝exp(-Δt/T)，

T (t+1)=k × T (t), k (0.9<k<1), t is the number of times of movement

$T\left(1\right)=20\&times;\frac{{\mathrm{\&Sigma;}}_{j=1}^M\left|\mathrm{\&Delta;t}\left(j\right)\right|}{M}$

Δ t is for from initial layout, and the cost of layout adjacent is between two poor;

11) utilize step 9) choose except described a part of unit residue unit in a part of unit move, obtain second and move layout cost;

12) step 10 is utilized), move layout cost and first by second and move layout cost and compare, determine that reservation first is moved layout or utilized second to move layout and substitute first and move layout;

13) step 11 is repeated) and 12), until perform at least M movement, determine selected layout.

Favourable, based on the above method, applicant finds reasonably to determine displacement, contributes to optimizing antifuse Series FPGA layout, and saves layout time.

Specifically: above-mentioned steps 9), the restriction rlimx of setting horizontal direction displacement and the restriction rlimy of vertical direction displacement, wherein,

The computing formula of the restriction of described horizontal direction movement is:

rlimx＝rlimx _old(1-0.44+rat _succ)Cx

Cx is the average wiring channel width of horizontal direction, rlimx _oldthe last horizontal direction displacement restriction before current movement, rlimx _oldinitial value be the length available of the horizontal direction of field programmable gate array chip;

The computing formula of the restriction of described vertical direction movement is:

rlimy＝rlimy _old(1-0.44+rat _succ)Cy

Cy is the average wiring channel width of vertical direction, rlimy _oldthe last vertical direction displacement restriction before current movement, rlimy _oldinitial value be the available width of the vertical direction of field programmable gate array chip.

Preferably, described mobile acceptance probability rat _succbe 0.44, at rat _succmobile restriction when being 0.44, closest to last displacement, makes layout more reasonable.

Preferably, a part of unit choosing movement is a unit.Wherein, choose a unit at every turn and move, make mobile sample range larger, layout is more reasonable.

The present invention significantly promotes the layout speed of antifuse Series FPGA, optimizes layout result.

Embodiment

In order to allow above-mentioned feature and advantage of the present invention more become apparent, below be specifically described for two example two especially.

What following examples described is compare according to layout cost adjacent between two, chooses the first embodiment that wherein smaller value carries out loop arrangement:

The present embodiment is under the prerequisite of the structure of known chip, and carry out layout to the antifuse field programmable gate array chip circuit of specifying, concrete grammar step is as follows:

Step S001: create and to be connected by horizontal gauze the first layout comprising N number of gauze that M unit formed with vertical gauze, wherein,

FPGA structure due to antifuse series mostly is N input, single logical block exported.Structurally encourage by the multiple logical block layouts exporting driving on same level arranges, shunt excitation circuits as practical utilizes horizontal interconnection resource, therefore, for the interconnection resource of the horizontal direction in field programmable gate array chip and vertical direction distinguishes setup parameter β x and β y, wherein β y< β x;

Optional two unit connect into gauze i, according to horizontal gauze length and the vertical gauze length of gauze i, set horizontal gauze cost frame bbx and vertical gauze cost frame bby, 1≤i≤N;

Fanout (i) is the fan-out cost according to current gauze neti, in order to reduce horizontal layout cost, improve longitudinal layout cost, therefore to be more the gauze consideration of many fan-outs when cost calculates, according to the fan-out line netting index amount of each unit in described gauze i, determine fan-out gauze cost gain delta I, draw fan-out cost fanout (i)=bbx × bby × Δ I of described gauze i;

In different chips, because the scale of the difference of gauze resource in X, Y-direction, the number difference of logical block pin and chip is different, gain delta I is also different for fan-out gauze cost, fan-out gauze cost gain delta I datum table has been drawn through large quantity research, with reference to following known table 1, fan-out cost fanout (i)=bbx × bby × Δ I of gauze i can be drawn.

Table 1

Step S002: the cost obtaining described first layout;

Step S0021 determines i-th gauze cost value with the horizontal gauze cost frame of β y, described gauze i with fan-out cost fanout (i) of vertical gauze cost frame bbx and bby, described gauze i with the interconnection resource parameter beta x of vertical direction according to described horizontal direction, wherein, i-th gauze cost value is directly proportional to bbx, bby and fanout (i), be inversely proportional to β x and β y, specific formula for calculation is:

$\cos t={\mathrm{\&Sigma;}}_{i=1}^{\mathrm{Nnet}.}(\frac{\mathrm{bbx}\&CenterDot;\mathrm{fanout}\left(i\right)}{\mathrm{\&beta;x}}+\frac{\mathrm{bby}\&CenterDot;\mathrm{fanout}\left(i\right)}{\mathrm{\&beta;y}}).$

Each gauze cost value until N root gauze, is added, draws the cost of the first layout by step S0022 from first gauze.

Enumerate two simple gauze layouts below, formula in above-mentioned steps S0021 be described in detail:

Example 1 is by the layout of the single fan-out formed of a simple line, as follows shown in concrete:

Unit A is the starting point of gauze, A coordinate: (x=1, y=1), and unit B is the terminating point of gauze, B coordinate: (x=2, y=2), and constructing a model is BOX (x _min=1, x _max=2, y _min=1, y _max=2) object of this model construction is the cabling in order to predict wiring, how because be not know to connect up actual meeting cabling when layout, so layout can only predict wiring meeting cabling in this cost frame, that is, wiring carries out cabling by two kinds of modes below possibly:

The first: (1,1)-> (1,2)-> (2,2)

The second: (1,1)-> (2,1)-> (2,2)

Example 2 is layouts of fan-out more than, specifically describes as follows:

A unit drives B and C two unit, now, fanout is 2.Concrete, A is the starting point of gauze, A coordinate: (x=1, y=1), B and C is the terminating point of gauze, B coordinate: (x=2, y=2), C point coordinate (x=2, y=1).

Under equal conditions, example 1 is a simple line, and example 2 but will connect two unit.Their cost is different, so, in fact to compensate many fan-outs gauze.Compensation is for cost frame model, because the gauze of many fan-outs may need to get around wiring to be cabled successfully, that is may exceed the scope wiring of Model B OX, in order to compensate this situation, increase so do the scope of Model B OX.

In addition, in above-mentioned cost frame model, layout needs the direction estimating wiring, and suppose that A connects B, A coordinate (1,1), B coordinate is undetermined.The rational position of obvious B is exactly (2,1) or (1,2), because only have them to be close to A.When which is more reasonable in judgement (2,1) or (1,2), need the gauze resource seeing horizontal and vertical direction.Suppose vertical direction there are 40 interconnection resources, 50 interconnection resources in horizontal direction, if so B is placed on (2,1) upper possibility is just more reasonable, because wiring is walked from horizontal direction like this, wiring unit can choose one from 50 interconnection resources, and the leeway selected than 40 is many.In large complicated circuit, need to allow wiring unit have well-to-do choice to realize wiring.β x and β y are generally the levels according to actual chips, vertical gauze resource is determined.

Step S003: at least one unit chosen in M unit moves, and obtains the cost of the second layout according to described step S001, S002;

Step S004: the cost of the cost of described second layout with described first layout is compared, wherein,

When the cost of the second layout is greater than the cost of the first layout, retain the first layout;

When the cost of the second layout is less than the cost of the first layout, the second layout is utilized to substitute the first layout;

Step S005: a part of unit in the residue unit utilizing step S003 to choose except described a part of unit moves, obtains the 3rd layout cost;

Step S006: utilize step S004 the 3rd layout cost to be compared with the second layout cost, determines reservation second layout or utilizes the 3rd layout to substitute the second layout;

Step S007: repeat step S005 and S006, until perform at least M movement, determine initial layout.

In above-mentioned iterative process, specifically find a logical block at random, record its current coordinate.Then in transportable scope, find the coordinate that new.New coordinate may there be logical block or sky, all old coordinate position and new coordinate position be exchanged in any case.Will certainly affect that this old logical block attaches with connection gauze that is other unit after so exchanging.If new coordinate has unit, the gauze of there also receives impact.If these gauze distances become far away, or the gauze passage that gauze may pass through is very crowded, all pressure can be produced to cost and time delay.So layout is may through the cost pressure value (layout cost) of gauze resource used in other words to the distance of gauze after exchanging and gauze to estimating after exchanging.If this value has diminished, be exactly so reasonably, specifically exchange be accepted.If unreasonable, so gain.This process always iteration repeats, until algorithm thinks that have found rational position terminates.

Test according to a large amount of layout, cloth linear velocity and wiring on-state rate are compared, applicant finds: above-mentioned first embodiment is compared according to layout cost adjacent between two, choose wherein smaller value and carry out loop arrangement, all prior art is better than in layout speed and placement quality, but although the cost of some layout costs slightly higher than last layout can be missed, but the movement of the better unit in position, therefore, applicant is when judging whether to need to move unit, optimize comparison mechanism, combine layout cost difference adjacent between two and these two kinds of factors of mobile acceptance probability, carry out the description of the second embodiment below in this approach:

Step S001-step S007 is identical with the step of above-mentioned first embodiment;

Step S008: set mobile acceptance probability rat _succ, 0<rat _succ<1;

Step S009: a part of unit chosen in M unit in described initial layout moves, according to described step 1), 2) obtain the first cost moving layout;

Wherein, because horizontal wiring resource is than vertical wirings aboundresources, thus placement algorithm can by Cx and Cy limit vertical direction to exchange, the adjustment speed in direction of improving the standard.

Specifically, when unit moves, setting moves horizontally the upper limit of distance in the horizontal direction, sets the upper limit of vertical displacement in the vertical direction, described upper level is relevant to the average length of arrangement wire of horizontal direction, and the described vertical upper limit is relevant to the average length of arrangement wire of vertical direction.

Wherein, the restriction rlimx of setting horizontal direction displacement and the restriction rlimy of vertical direction displacement, wherein, the computing formula of the restriction of described horizontal direction movement is:

rlimx＝rlimx _old(1-0.44+rat _succ)Cx

Cx is the average wiring channel width of horizontal direction, rlimx _oldthe last horizontal direction displacement restriction before current movement, rlimx _oldinitial value be the length available of the horizontal direction of field programmable gate array chip; When layout starts, can carry out in the scope of whole chip exchange.When layout proceeds to a certain degree, in order to save layout time and efficiency, just no longer need in so on a large scale, to find destination to exchange, so be provided with a mobile upper limit, regulation only to do movement in the scope of specifying.

The computing formula of the restriction of described vertical direction movement is:

rlimy＝rlimy _old(1-0.44+rat _succ)Cy

Cy is the average wiring channel width of vertical direction, rlimy _oldthe last vertical direction displacement restriction before current movement, rlimy _oldinitial value be the available width of the vertical direction of field programmable gate array chip.

Wherein, draw according to known experimental data: rat _succ=0.44 is best mobile receptance, uses (1-0.44+rat with the formula _succ) most suitable exchange can be found to limit.

Step S010: the cost that described first moves layout is compared with 0 with the difference of the cost of described initial layout, wherein,

When difference is less than 0, utilizes first to move layout and substitute initial layout;

When difference is greater than 0, calculate the first movement probability, when the first movement probability rat (1) is greater than mobile acceptance probability rat _succtime, utilize first to move layout and substitute initial layout; When the first movement probability is less than mobile acceptance probability rat _succtime, retain initial layout,

Wherein, described first movement probability is according to following formulae discovery:

rat＝exp(-Δt/T)，

Wherein, Δ t is for from initial layout, and the cost of layout adjacent is between two poor;

T is the reference value of setting, and its value corresponds to the number of times of movement and successively decreases gradually and be tending towards 0, and its formula is as follows:

T (t+1)=k T (t), k (0.9<k<1), t is the number of times of movement

The initial value setting method of T is as follows:

First, what establishment one was random comprises M unit way circuit layout;

Then, successively an above-mentioned M unit is carried out secondary mobile, calculate mobile standard deviation.

Finally, the initial value of default reference value is set to 20 times of above-mentioned mobile standard deviation.

Specifically, the computing formula of the initial value of described T is:

$T\left(1\right)=20\&times;\frac{{\mathrm{\&Sigma;}}_{j=1}^M\left|\mathrm{\&Delta;t}\left(j\right)\right|}{M}$

Step S011: a part of unit in the residue unit utilizing step S009 to choose except described a part of unit moves, obtains second and moves layout cost;

Step S012: utilize step S010), move layout cost and first by second and move layout cost and compare, determine that reservation first is moved layout or utilized second to move layout and substitute first and move layout;

Step S013: repeat step S011 and step S012, until perform at least M movement, determine selected layout.

In above-described embodiment, a part of unit is chosen in each movement, be like this in order to movement speed sooner, and choose a unit at every turn and move, make mobile sample range more greatly, layout is more reasonable.

Above-described is only some embodiments of the present invention.For the person of ordinary skill of the art, without departing from the concept of the premise of the invention, can also make some distortion and improvement, these all belong to protection scope of the present invention.Such as, in the present invention, adopt some computing formula, but they calculate, and are convenient to reflect and select preferably layout intuitively while just schematically reacting layout cost also relatively simple.To one skilled in the art; can change the parameter of above-mentioned formula, or other amendment or computing is carried out to the relation between parameter, such as increase a cost offset; these all belong to the invention design, within protection scope of the present invention.

Claims (6)

1. a layout optimization method for antifuse field programmable gate array, comprising:

1) create and to be connected by horizontal gauze the first layout comprising N number of gauze that M unit formed with vertical gauze, wherein,

For the interconnection resource of the horizontal direction in field programmable gate array chip and vertical direction sets relevant parameter β x and β y respectively, wherein β y< β x;

Optional two unit connect into gauze i, according to horizontal gauze length and the vertical gauze length of gauze i, set horizontal gauze cost frame bbx and vertical gauze cost frame bby, 1≤i≤N;

According to the fan-out line netting index amount of each unit in described gauze i, determine fan-out cost fanout (i)=bbx × bby × Δ I of fan-out gauze cost gain delta I and described gauze i;

2) cost of described first layout is obtained;

I-th gauze cost value is determined with the horizontal gauze cost frame of β y, described gauze i with fan-out cost fanout (i) of vertical gauze cost frame bbx and bby, described gauze i with the interconnection resource parameter beta x of vertical direction according to described horizontal direction, wherein, i-th gauze cost value is directly proportional to bbx, bby and fanout (i), be inversely proportional to β x and β y

Until N root gauze from first gauze, each gauze cost value is added, draws the cost of the first layout;

3) a part of unit chosen in M unit moves, according to described step 1), 2) obtain the cost of the second layout;

4) cost of the cost of described second layout with described first layout is compared, wherein,

When the cost of the second layout is greater than the cost of the first layout, retain the first layout;

When the cost of the second layout is less than the cost of the first layout, the second layout is utilized to substitute the first layout;

5) utilize step 3) choose except described a part of unit residue unit in a part of unit move, obtain the 3rd layout cost;

6) step 4 is utilized), the 3rd layout cost is compared with the second layout cost, determines reservation second layout or utilize the 3rd layout to substitute the second layout;

7) step 5 is repeated) and 6), until perform at least M movement, determine initial layout.

2. method according to claim 1, is characterized in that, the computing formula of the cost of described first initial layout is:

$\cos t={\mathrm{\&Sigma;}}_{i=1}^{\mathrm{Nuet}:}(\frac{\mathrm{bbx}\&CenterDot;\mathrm{fanout}\left(i\right)}{\mathrm{\&beta;x}}+\frac{\mathrm{bby}\&CenterDot;\mathrm{fanout}\left(i\right)}{\mathrm{\&beta;y}}).$

3. method according to claim 1, is characterized in that, in described step 7) after also comprise:

8) mobile acceptance probability rat is set _succ, 0<rat _succ<1;

9) a part of unit chosen in M unit in described initial layout moves, according to described step 1), 2) obtain the first cost moving layout;

10) cost that described first moves layout is compared with 0 with the difference of the cost of described initial layout, wherein,

When difference is less than 0, utilizes first to move layout and substitute initial layout;

When difference is greater than 0, calculate the first movement probability, when the first movement probability rat (1) is greater than mobile acceptance probability rat _succtime, utilize first to move layout and substitute initial layout; When the first movement probability is less than mobile acceptance probability rat _succtime, retain initial layout,

Wherein, described first movement probability is according to following formulae discovery:

rat＝exp(-Δt/T)，

T (t+1)=k × T (t), k (0.9<k<1), t is the number of times of movement

$T\left(1\right)=20\&times;\frac{{\mathrm{\&Sigma;}}_{j=1}^M\left|\mathrm{\&Delta;t}\left(j\right)\right|}{M}$

Δ t is for from initial layout, and the cost of layout adjacent is between two poor;

11) utilize step 9) choose except described a part of unit residue unit in a part of unit move, obtain second and move layout cost;

12) step 10 is utilized), move layout cost and first by second and move layout cost and compare, determine that reservation first is moved layout or utilized second to move layout and substitute first and move layout;

13) step 11 is repeated) and 12), until perform at least M movement, determine selected layout.

4. method according to claim 3, is characterized in that, described step 9) in, the restriction rlimx of setting horizontal direction displacement and the restriction rlimy of vertical direction displacement, wherein,

The computing formula of the restriction of described horizontal direction movement is:

rlimx＝rlimx _old(1-0.44+rat _succ)Cx

Cx is the average wiring channel width of horizontal direction, rlimx _oldthe last horizontal direction displacement restriction before current movement, rlimx _oldinitial value be the length available of the horizontal direction of field programmable gate array chip;

The computing formula of the restriction of described vertical direction movement is:

rlimy＝rlimy _old(1-0.44+rat _succ)Cy

Cy is the average wiring channel width of vertical direction, rlimy _oldthe last vertical direction displacement restriction before current movement, rlimy _oldinitial value be the available width of the vertical direction of field programmable gate array chip.

5. the method according to claim 3 or 4, is characterized in that, described mobile acceptance probability rat _succbe 0.44.

6. the method according to claim 1 or 3, is characterized in that, a part of unit choosing movement is a unit.