CN104461676A - Binary translation stack operation accelerated processing method and processor thereof - Google Patents
Binary translation stack operation accelerated processing method and processor thereof Download PDFInfo
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Abstract
A binary translation stack operation accelerated processing method includes a stack data loading instruction and a stack data storage instruction, the two instructions finish reading, writing, modification of a stack pointer, inspection of stack boarder crossing and processing of stack boarder crossing on the basis of a stack boarder universal register, a stack pointer universal register, a stack boarder crossing transfer address universal register, a source universal register set and a target universal register set, and finish updating of the state of a processor according to whether stack access crosses the boarder or not. The invention provides the binary translation stack operation accelerated processor. On the situation that it is guaranteed that hardware resources are unchanged, binary translation system performance and code density are greatly improved.
Description
Technical field
The present invention relates to Java Virtual Machine field, especially a kind of scale-of-two translates stack manipulation accelerated processing method and processor thereof.
Background technology
By storehouse transmission procedure variable scale-of-two translation system (as Java Virtual Machine), each variable transferring comprises to be write storehouse and reads storehouse two processes, writing storehouse for the stack address place that the variable data needing to transmit pointed to stored in stack pointer adjusts stack pointer, reads storehouse for obtaining desired data and adjust stack pointer from storehouse.Based on the security consideration of system, before writing storehouse at every turn and reading storehouse, all need to detect according to the data volume transmitted and current stack pointer the storehouse behavior of crossing the border and process.These stack manipulations often need many processor instructions just can complete, and a large amount of stack manipulations that variable transferring brings frequently are one of scale-of-two performance bottlenecks of translating technology.
How to accelerate scale-of-two translate stack manipulation with carry out fast variable transferring be scale-of-two translation system designer must faced by problem.For stacked data read-write and stack pointer adjustment, a lot of dynamically translation system is by introducing the instruction that contiguous memory area data is loaded into multiple general register instruction and multiple general purpose register data is stored into contiguous memory region to accelerate to translate scale-of-two the read-write operation of stacked data, and some dynamic translation system add stack pointer adjustment function to accelerate to translate scale-of-two the operation of storehouse further to the above two instruction in addition; For stack boundaries inspection, most of scale-of-two translation system completes this inspection operation by using relatively also jump instruction, also has partial binary translation system to complete this inspection operation by introducing proprietary hardware module.These methods are due to the process stack manipulation by software serial, and the acceleration effect therefore obtained is limited.Although adopt the proprietary hardware detection module that crosses the border can obtain good scale-of-two translation system performance, the method needs to increase certain processor hardware resource, and cost is higher.
Summary of the invention
Many processor instructions are needed to affect scale-of-two translation system performance and this problem of code density to overcome existing scale-of-two translation system when processing stack manipulation, the invention provides a kind of scale-of-two and translate stack manipulation accelerated processing method and processor thereof, propose a kind of scale-of-two and translate stack manipulation assisted instruction pair, only need an instruction to complete and reading or writing of stacked data is translated to scale-of-two, the adjustment of stack pointer and the inspection of stack boundaries and process of crossing the border, when ensureing that processor hardware resource is constant, strong lifting scale-of-two translation system performance and code density.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of scale-of-two translates stack manipulation accelerated processing method, and this accelerated processing method comprises a stacked data load instructions and a stacked data stores instruction;
The processing procedure of this stacked data load instructions is: complete the detection of scale-of-two being translated to stack boundaries according to stack boundaries general-purpose register and stack pointer general-purpose register, calculate according to stack pointer general-purpose register when detecting that heap stack addressing is not crossed the border and obtain storehouse reference address, then the data this address being pointed to storehouse place are loaded into the set of target general-purpose register according to the order of sequence, and according to the data width adjustment stack pointer general-purpose register loaded; When storehouse Access Violation being detected, the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform;
The processing procedure that this stacked data stores instruction is: complete the detection of scale-of-two being translated to stack boundaries according to stack boundaries general-purpose register and stack pointer general-purpose register, calculate according to stack pointer general-purpose register when detecting that heap stack addressing is not crossed the border and obtain storehouse reference address, then the data of source general-purpose register set are stored into according to the order of sequence this address and point to storehouse place, and according to the data width adjustment stack pointer general-purpose register stored; When storehouse Access Violation being detected, the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform.
Further, described stack boundaries general-purpose register comprises storehouse coboundary general-purpose register and storehouse lower boundary general-purpose register, this storehouse coboundary general-purpose register, storehouse lower boundary general-purpose register, stack pointer general-purpose register and storehouse cross the border register number corresponding to transfer address general-purpose register or specify in instruction encoding, or are implicitly fixed as particular value.
Further again, described scale-of-two translates that stack manipulation comprises stack reads operation, storehouse write operation, stack pointer adjustment operation, storehouse cross the border detection operation and storehouse crosses the border, and process operates;
The operation of this stack reads refers to: calculate according to stack pointer general-purpose register and obtain storehouse reference address, when detecting that heap stack addressing is not crossed the border, is stored into according to the order of sequence by the stacked data obtained in the set of target general-purpose register from this storehouse reference address;
This storehouse write operation refers to: calculate according to stack pointer general-purpose register and obtain storehouse reference address, when detecting that heap stack addressing is not crossed the border, the data in source general-purpose register set is stored in the storehouse of this storehouse reference address sensing according to the order of sequence;
This stack pointer adjustment operation refers to: when detecting that heap stack addressing is not crossed the border, and adds or deducts the total data width loading from storehouse or store to storehouse, can adopt the stack pointer adjustable strategies that two kinds are different to stack pointer general-purpose register:
Stack pointer adjustable strategies one: stacked data stores instruction stack pointer general-purpose register and adds that the result of the total data width stored to storehouse is to upgrade stack pointer general-purpose register, and stacked data load instructions stack pointer general-purpose register deducts the result of the total data width loaded from storehouse to upgrade stack pointer general-purpose register;
Stack pointer adjustable strategies two: stacked data stores instruction stack pointer general-purpose register and deducts the result of the total data width stored to storehouse to upgrade stack pointer general-purpose register, stacked data load instructions stack pointer general-purpose register adds that the result of the total data width loaded from storehouse is to upgrade stack pointer general-purpose register;
This storehouse cross the border detection operation refer to: judge whether storehouse reference address is in storehouse coboundary general-purpose register and the address realm specified by storehouse lower boundary general-purpose register, when adopting above-mentioned stack pointer adjustable strategies for the moment, stacked data stores instruction and can only check the behavior of crossing the border of storehouse coboundary, and stacked data load instructions can only check the behavior of crossing the border of storehouse lower boundary; When adopting above-mentioned stack pointer adjustable strategies two, stacked data stores instruction and can only check the behavior of crossing the border of storehouse lower boundary, and stacked data load instructions can only check the behavior of crossing the border of storehouse coboundary;
This storehouse cross the border process operation refer to: the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform.
Further, described data width refers to load from storehouse or to the total bytes of storehouse stored in data, in the target general-purpose register set of being specified by stacked data load instructions, general-purpose register number or stacked data store general-purpose register number in the source general-purpose register set that instruction specifies and are multiplied by the metadata width that each general-purpose register loads from storehouse or store to storehouse and obtain, and this metadata width is specified by the certain bits in instruction encoding.
Described instruction width refers to that stacked data load instructions or stacked data store the byte number of the corresponding order code of instruction.
A kind of scale-of-two translates stack manipulation OverDrive Processor ODP, and described processor comprises:
Scale-of-two translates stack manipulation assisted instruction to decoding unit, know that whether the instruction when pre-treatment is that stacked data load instructions or stacked data store instruction according to order code, and obtain metadata width and storehouse coboundary general-purpose register, storehouse lower boundary general-purpose register, stack pointer general-purpose register, storehouse cross the border the corresponding register number of transfer address general-purpose register, the set of target general-purpose register and source general-purpose register set;
Scale-of-two translates stack manipulation control module, be connected to scale-of-two and translate stack manipulation assisted instruction translates stack manipulation data processing unit output terminal to the output terminal of decoding unit and scale-of-two, translate stack manipulation assisted instruction from this scale-of-two to cross the border fox message to the decoding information of decoding unit with from the storehouse that this scale-of-two translates stack manipulation data processing unit in order to receive, instruction is stored according to stacked data load instructions and stacked data, and after judging whether stack checking crosses the border, carry out the control that loads, stores and cross the border;
Scale-of-two translates stack manipulation data processing unit, be connected to the output terminal that the output terminal of general-purpose register and scale-of-two translate stack manipulation control module, complete scale-of-two according to stack pointer general-purpose register and stack boundaries general-purpose register and translate the detection of piling stack addressing and whether crossing the border, receive the control information of translating stack manipulation control module from this scale-of-two simultaneously, utilize these control informations: complete according to stack pointer general-purpose register and the stacked data width of having accessed the calculating that scale-of-two translates storehouse reference address, the calculating of stack pointer general-purpose register updated value is completed according to stack pointer general-purpose register and total stacked data width of accessing, the calculating of link register updated value is completed according to link register and instruction width, complete storehouse to cross the border the calculating of transfer address according to the storehouse transfer address general-purpose register that crosses the border, and prepare to storehouse store data or receive from storehouse load data to complete the read-write of storehouse,
General-purpose register, be connected to scale-of-two and translate the output terminal that the output terminal of stack manipulation control module and scale-of-two translate stack manipulation data processing unit, for providing scale-of-two to translate stack manipulation desired data, and translate according to scale-of-two the data that general-purpose register that stack manipulation control module provides number and scale-of-two translate stack manipulation data processing unit and provide and complete the write back operations that scale-of-two translates stack manipulation related register.
Further, described scale-of-two is translated in stack manipulation control module, when decoding information instruction present instruction is stacked data load instructions and stack checking does not cross the border, this scale-of-two translates the write-back control information that stack manipulation control module generates stack pointer general-purpose register, the set of target general-purpose register, and indicates scale-of-two to translate stack manipulation data processing unit to calculate storehouse reference address and obtain target general-purpose register set write-back with stack accessing and complete the calculating of stack pointer general-purpose register write-back value.
Described scale-of-two is translated in stack manipulation control module, when decoding information instruction present instruction is stacked data storage instruction and stack checking does not cross the border, this scale-of-two translates the write-back control information that stack manipulation control module generates stack pointer general-purpose register and storehouse, and indicates scale-of-two to translate stack manipulation data processing unit to prepare storehouse write-back and write back address with write-back storehouse and complete the calculating of stack pointer general-purpose register write-back value.
Described scale-of-two is translated in stack manipulation control module, when decoding information instruction present instruction is that scale-of-two translates the centering instruction of stack manipulation assisted instruction and stack checking crosses the border, this scale-of-two is translated stack manipulation control module and is generated the write-back control information of link register and storehouse and to cross the border transfer control information, and indicates scale-of-two to translate stack manipulation data processing unit to complete the calculating of link register write-back value and storehouse and to cross the border the calculating of transfer address.
The technical conceive of this device is: the stack manipulation of scale-of-two translation system comprises stacked data read-write, stack pointer adjustment, stack boundaries inspection and storehouse cross the border process etc., current most of scale-of-two translation system widely uses contiguous memory area data and loads and store instruction to accelerate stacked data read-write and stack pointer adjustment operation, uses relatively and jump instruction or proprietary hardware module accelerate stack boundaries inspection and process operates.These methods or fully do not excavate the concurrency of stack manipulation, or add more additional hardware resources and cost for processor.The present invention is that microprocessor is introduced a kind of scale-of-two and translated stack manipulation assisted instruction pair, stacked data reads or writes, stack pointer is safeguarded, storehouse crosses the border inspection and the scale-of-two such as process that cross the border translate stack manipulation for completing of only needing an instruction to walk abreast, and effectively can improve scale-of-two translation system performance under the prerequisite not affecting processor hardware cost.This instruction is to comprising stacked data load instructions and stacked data storage instruction, wherein stacked data load instructions complete read storehouse while implicitly carry out storehouse cross the border check and process, stacked data store instruction complete write storehouse while implicitly carry out storehouse cross the border check and process.The present invention complete storehouse cross the border check and process time, the jump address register etc. that storehouse coboundary register, storehouse lower boundary register and storehouse crossed the border is fixed as processor general-purpose register, without the need to increasing extra register resources for processor, also enhance dirigibility and the usable range of this method simultaneously.
Beneficial effect of the present invention is mainly manifested in: only need a microprocessor instruction can complete scale-of-two and translate the relevant operation of storehouse, improve the performance of scale-of-two translation system effectively; Stack boundaries inspection and process information needed of crossing the border are stored in general-purpose register simultaneously, enhance dirigibility and the usable range of this method.
Accompanying drawing explanation
Fig. 1 is stacked data load instructions process flow diagram.
Fig. 2 is that stacked data stores instruction flow chart.
Fig. 3 is that scale-of-two translates stack manipulation storehouse coboundary general-purpose register, storehouse lower boundary general-purpose register and storehouse cross the border the schematic diagram of transfer address general-purpose register specified scheme, wherein (a) formulates all storehouse related registers for implicit expression, b () is Explicit designation stack pointer general-purpose register, c () is Explicit designation stack pointer general-purpose register and stack boundaries general-purpose register, d () to be crossed the border transfer address general-purpose register for Explicit designation stack pointer general-purpose register and storehouse, e () to be crossed the border transfer address general-purpose register and stack boundaries general-purpose register for explicit storehouse, f () is all storehouse related registers of Explicit designation.
Fig. 4 introduces scale-of-two to translate the right microprocessor architecture figure of stack manipulation assisted instruction.
Fig. 5 introduces scale-of-two to translate each cellular construction figure in the right microprocessor of stack manipulation assisted instruction, wherein, a () is general-purpose register, b () loads for stacked data and stores instruction decoding unit, c () is data processing unit storehouse reference address generation module, d () is data processing unit stack reads writing module, e () to be crossed the border checking module for data processing unit storehouse, f () to be crossed the border branch target address computing module for data processing unit storehouse, (g) translates stack manipulation control module for scale-of-two.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Embodiment 1
With reference to Fig. 1 ~ Fig. 5, a kind of scale-of-two translates stack manipulation accelerated processing method, and this accelerated processing method comprises a stacked data load instructions and a stacked data stores instruction;
The processing procedure of this stacked data load instructions is: complete the detection of scale-of-two being translated to stack boundaries according to stack boundaries general-purpose register and stack pointer general-purpose register, calculate according to stack pointer general-purpose register when detecting that heap stack addressing is not crossed the border and obtain storehouse reference address, then the data this address being pointed to storehouse place are loaded into the set of target general-purpose register according to the order of sequence, and according to the data width adjustment stack pointer general-purpose register loaded; When storehouse Access Violation being detected, the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform;
The processing procedure that this stacked data stores instruction is: complete the detection of scale-of-two being translated to stack boundaries according to stack boundaries general-purpose register and stack pointer general-purpose register, calculate according to stack pointer general-purpose register when detecting that heap stack addressing is not crossed the border and obtain storehouse reference address, then the data of source general-purpose register set are stored into according to the order of sequence this address and point to storehouse place, and according to the data width adjustment stack pointer general-purpose register stored; When storehouse Access Violation being detected, the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform.
In the present embodiment, stacked data load instructions, based on stack boundaries general-purpose register, stack pointer general-purpose register, cross the border transfer address general-purpose register and the set of target general-purpose register of storehouse completes the stack reads operation of scale-of-two being translated to storehouse, stack pointer adjustment operation, cross the border detection operation and storehouse of storehouse crosses the border process operation: complete the detection of scale-of-two being translated to stack boundaries according to stack boundaries general-purpose register and stack pointer general-purpose register, when detecting that heap stack addressing is not crossed the border, stack pointer general-purpose register is pointed to the Data import at storehouse place to the set of target general-purpose register, and according to the data width adjustment stack pointer general-purpose register loaded, when storehouse Access Violation being detected, the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform.
Stacked data stores instruction, based on stack boundaries general-purpose register, stack pointer general-purpose register, cross the border transfer address general-purpose register and source general-purpose register set of storehouse completes the storehouse write operation of scale-of-two being translated to storehouse, stack pointer adjustment operation, cross the border detection operation and storehouse of storehouse crosses the border process operation: complete the detection of scale-of-two being translated to stack boundaries according to stack boundaries general-purpose register and stack pointer general-purpose register, when detecting that heap stack addressing is not crossed the border, the data of source general-purpose register set are stored into stack pointer general-purpose register and point to storehouse place, and according to the data width adjustment stack pointer general-purpose register stored, when storehouse Access Violation being detected, the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform.
Further, described stack boundaries general-purpose register comprises storehouse coboundary general-purpose register and storehouse lower boundary general-purpose register, this storehouse coboundary general-purpose register, storehouse lower boundary general-purpose register, stack pointer general-purpose register and storehouse cross the border register number corresponding to transfer address general-purpose register or specify in instruction encoding, or are implicitly fixed as particular value.
Further again, described scale-of-two translates that stack manipulation comprises stack reads operation, storehouse write operation, stack pointer adjustment operation, storehouse cross the border detection operation and storehouse crosses the border, and process operates;
The operation of this stack reads refers to: calculate according to stack pointer general-purpose register and obtain storehouse reference address, when detecting that heap stack addressing is not crossed the border, is stored into according to the order of sequence by the stacked data obtained in the set of target general-purpose register from this storehouse reference address;
This storehouse write operation refers to: calculate according to stack pointer general-purpose register and obtain storehouse reference address, when detecting that heap stack addressing is not crossed the border, the data in source general-purpose register set is stored in the storehouse of this storehouse reference address sensing according to the order of sequence;
This stack pointer adjustment operation refers to: when detecting that heap stack addressing is not crossed the border, and adds or deducts the total data width loading from storehouse or store to storehouse, can adopt the stack pointer adjustable strategies that two kinds are different to stack pointer general-purpose register:
Stack pointer adjustable strategies one: stacked data stores instruction stack pointer general-purpose register and adds that the result of the total data width stored to storehouse is to upgrade stack pointer general-purpose register, and stacked data load instructions stack pointer general-purpose register deducts the result of the total data width loaded from storehouse to upgrade stack pointer general-purpose register;
Stack pointer adjustable strategies two: stacked data stores instruction stack pointer general-purpose register and deducts the result of the total data width stored to storehouse to upgrade stack pointer general-purpose register, stacked data load instructions stack pointer general-purpose register adds that the result of the total data width loaded from storehouse is to upgrade stack pointer general-purpose register;
This storehouse cross the border detection operation refer to: judge whether storehouse reference address is in storehouse coboundary general-purpose register and the address realm specified by storehouse lower boundary general-purpose register, when adopting above-mentioned stack pointer adjustable strategies for the moment, stacked data stores instruction and can only check the behavior of crossing the border of storehouse coboundary, and stacked data load instructions can only check the behavior of crossing the border of storehouse lower boundary; When adopting above-mentioned stack pointer adjustable strategies two, stacked data stores instruction and can only check the behavior of crossing the border of storehouse lower boundary, and stacked data load instructions can only check the behavior of crossing the border of storehouse coboundary;
This storehouse cross the border process operation refer to: the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform.
Further, described data width refers to load from storehouse or to the total bytes of storehouse stored in data, in the target general-purpose register set of being specified by stacked data load instructions, general-purpose register number or stacked data store general-purpose register number in the source general-purpose register set that instruction specifies and are multiplied by the metadata width that each general-purpose register loads from storehouse or store to storehouse and obtain, and this metadata width is specified by the certain bits in instruction encoding.
Described instruction width refers to that stacked data load instructions or stacked data store the byte number of the corresponding order code of instruction.
With reference to shown in Fig. 3, what storehouse coboundary general-purpose register, storehouse lower boundary general-purpose register and storehouse crossed the border transfer address general-purpose register is set with kinds of schemes, CPU design personnel are when this scale-of-two of specific implementation translates stack manipulation assisted instruction pair within a processor, namely these registers of appointment that can be explicit in instruction encoding, also implicitly can be appointed as these registers by specific general-purpose register.
Embodiment 2
With reference to Fig. 4 and Fig. 5, a kind of scale-of-two translates stack manipulation OverDrive Processor ODP, comprises scale-of-two and translates that stack manipulation assisted instruction translates stack manipulation control module to decoding unit, scale-of-two, scale-of-two translates stack manipulation data processing unit and general-purpose register:
Scale-of-two translates stack manipulation assisted instruction to decoding unit, know that whether the instruction when pre-treatment is that stacked data load instructions or stacked data store instruction according to order code, and obtain metadata width and storehouse coboundary general-purpose register, storehouse lower boundary general-purpose register, stack pointer general-purpose register, storehouse cross the border the corresponding register number of transfer address general-purpose register, the set of target general-purpose register and source general-purpose register set;
Scale-of-two translates stack manipulation control module, be connected to scale-of-two and translate stack manipulation assisted instruction translates stack manipulation data processing unit output terminal to the output terminal of decoding unit and scale-of-two, translate stack manipulation assisted instruction from this scale-of-two to cross the border fox message to the decoding information of decoding unit with from the storehouse that this scale-of-two translates stack manipulation data processing unit in order to receive, be handled as follows respectively according to these information:
(1) when decoding information instruction present instruction is stacked data load instructions and stack checking does not cross the border, this scale-of-two translates the write-back control information that stack manipulation control module generates stack pointer general-purpose register, the set of target general-purpose register, and indicates scale-of-two to translate stack manipulation data processing unit to calculate storehouse reference address and obtain target general-purpose register set write-back with stack accessing and complete the calculating of stack pointer general-purpose register write-back value;
(2) when decoding information instruction present instruction is stacked data storage instruction and stack checking does not cross the border, this scale-of-two translates the write-back control information that stack manipulation control module generates stack pointer general-purpose register and storehouse, and indicates scale-of-two to translate stack manipulation data processing unit to prepare storehouse write-back and write back address with write-back storehouse and complete the calculating of stack pointer general-purpose register write-back value;
(3) when decoding information instruction present instruction be scale-of-two translate stack manipulation assisted instruction to and stack checking crosses the border time, this scale-of-two is translated stack manipulation control module and is generated the write-back control information of link register and storehouse and to cross the border transfer control information, and indicates scale-of-two to translate stack manipulation data processing unit to complete the calculating of link register write-back value and storehouse and to cross the border the calculating of transfer address;
Scale-of-two translates stack manipulation data processing unit, be connected to the output terminal that the output terminal of general-purpose register and scale-of-two translate stack manipulation control module, complete scale-of-two according to stack pointer general-purpose register and stack boundaries general-purpose register and translate the detection of piling stack addressing and whether crossing the border, receive the control information of translating stack manipulation control module from this scale-of-two simultaneously, utilize these control informations: complete according to stack pointer general-purpose register and the stacked data width of having accessed the calculating that scale-of-two translates storehouse reference address, the calculating of stack pointer general-purpose register updated value is completed according to stack pointer general-purpose register and total stacked data width of accessing, the calculating of link register updated value is completed according to link register and instruction width, complete storehouse to cross the border the calculating of transfer address according to the storehouse transfer address general-purpose register that crosses the border, and prepare to storehouse store data or receive from storehouse load data to complete the read-write of storehouse,
General-purpose register, be connected to scale-of-two and translate the output terminal that the output terminal of stack manipulation control module and scale-of-two translate stack manipulation data processing unit, for providing scale-of-two to translate stack manipulation desired data, and translate according to scale-of-two the data that general-purpose register that stack manipulation control module provides number and scale-of-two translate stack manipulation data processing unit and provide and complete the write back operations that scale-of-two translates stack manipulation related register.
Claims (9)
1. scale-of-two translates a stack manipulation accelerated processing method, it is characterized in that: this accelerated processing method comprises a stacked data load instructions and a stacked data stores instruction;
The processing procedure of this stacked data load instructions is: complete the detection of scale-of-two being translated to stack boundaries according to stack boundaries general-purpose register and stack pointer general-purpose register, calculate according to stack pointer general-purpose register when detecting that heap stack addressing is not crossed the border and obtain storehouse reference address, then the data this address being pointed to storehouse place are loaded into the set of target general-purpose register according to the order of sequence, and according to the data width adjustment stack pointer general-purpose register loaded; When storehouse Access Violation being detected, the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform;
The processing procedure that this stacked data stores instruction is: complete the detection of scale-of-two being translated to stack boundaries according to stack boundaries general-purpose register and stack pointer general-purpose register, calculate according to stack pointer general-purpose register when detecting that heap stack addressing is not crossed the border and obtain storehouse reference address, then the data of source general-purpose register set are stored into according to the order of sequence this address and point to storehouse place, and according to the data width adjustment stack pointer general-purpose register stored; When storehouse Access Violation being detected, the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform.
2. a kind of scale-of-two as claimed in claim 1 translates stack manipulation accelerated processing method, it is characterized in that: described stack boundaries general-purpose register comprises storehouse coboundary general-purpose register and storehouse lower boundary general-purpose register, this storehouse coboundary general-purpose register, storehouse lower boundary general-purpose register, stack pointer general-purpose register and storehouse cross the border register number corresponding to transfer address general-purpose register or specify in instruction encoding, or are implicitly fixed as particular value.
3. a kind of scale-of-two as claimed in claim 1 or 2 translates stack manipulation accelerated processing method, it is characterized in that: described scale-of-two translates that stack manipulation comprises stack reads operation, storehouse write operation, stack pointer adjustment operation, storehouse cross the border detection operation and storehouse crosses the border process operation;
The operation of this stack reads refers to: calculate according to stack pointer general-purpose register and obtain storehouse reference address, when detecting that heap stack addressing is not crossed the border, is stored into according to the order of sequence by the stacked data obtained in the set of target general-purpose register from this storehouse reference address;
This storehouse write operation refers to: calculate according to stack pointer general-purpose register and obtain storehouse reference address, when detecting that heap stack addressing is not crossed the border, the data in source general-purpose register set is stored in the storehouse of this storehouse reference address sensing according to the order of sequence;
This stack pointer adjustment operation refers to: when detecting that heap stack addressing is not crossed the border, and adds or deducts the total data width loading from storehouse or store to storehouse, can adopt the stack pointer adjustable strategies that two kinds are different to stack pointer general-purpose register:
Stack pointer adjustable strategies one: stacked data stores instruction stack pointer general-purpose register and adds that the result of the total data width stored to storehouse is to upgrade stack pointer general-purpose register, and stacked data load instructions stack pointer general-purpose register deducts the result of the total data width loaded from storehouse to upgrade stack pointer general-purpose register;
Stack pointer adjustable strategies two: stacked data stores instruction stack pointer general-purpose register and deducts the result of the total data width stored to storehouse to upgrade stack pointer general-purpose register, stacked data load instructions stack pointer general-purpose register adds that the result of the total data width loaded from storehouse is to upgrade stack pointer general-purpose register;
This storehouse cross the border detection operation refer to: judge whether storehouse reference address is in storehouse coboundary general-purpose register and the address realm specified by storehouse lower boundary general-purpose register, when adopting above-mentioned stack pointer adjustable strategies for the moment, stacked data stores instruction and can only check the behavior of crossing the border of storehouse coboundary, and stacked data load instructions can only check the behavior of crossing the border of storehouse lower boundary; When adopting above-mentioned stack pointer adjustable strategies two, stacked data stores instruction and can only check the behavior of crossing the border of storehouse lower boundary, and stacked data load instructions can only check the behavior of crossing the border of storehouse coboundary;
This storehouse cross the border process operation refer to: the programmable counter of stacked data load instructions is added that the result of this instruction width is stored into link register, then jump to by storehouse cross the border the computing of transfer address general-purpose register obtain address place perform.
4. a kind of scale-of-two as claimed in claim 1 or 2 translates stack manipulation accelerated processing method, it is characterized in that: described data width refers to load from storehouse or to the total bytes of storehouse stored in data, in the target general-purpose register set of being specified by stacked data load instructions, general-purpose register number or stacked data store general-purpose register number in the source general-purpose register set that instruction specifies and are multiplied by the metadata width that each general-purpose register loads from storehouse or store to storehouse and obtain, and this metadata width is specified by the certain bits in instruction encoding.
5. a kind of scale-of-two as claimed in claim 1 or 2 translates stack manipulation accelerated processing method, it is characterized in that: described instruction width refers to that stacked data load instructions or stacked data store the byte number of the corresponding order code of instruction.
6. scale-of-two translates a stack manipulation OverDrive Processor ODP, it is characterized in that: described processor comprises:
Scale-of-two translates stack manipulation assisted instruction to decoding unit, know that whether the instruction when pre-treatment is that stacked data load instructions or stacked data store instruction according to order code, and obtain metadata width and storehouse coboundary general-purpose register, storehouse lower boundary general-purpose register, stack pointer general-purpose register, storehouse cross the border the corresponding register number of transfer address general-purpose register, the set of target general-purpose register and source general-purpose register set;
Scale-of-two translates stack manipulation control module, be connected to scale-of-two and translate stack manipulation assisted instruction translates stack manipulation data processing unit output terminal to the output terminal of decoding unit and scale-of-two, translate stack manipulation assisted instruction from this scale-of-two to cross the border fox message to the decoding information of decoding unit with from the storehouse that this scale-of-two translates stack manipulation data processing unit in order to receive, instruction is stored according to stacked data load instructions and stacked data, and after judging whether stack checking crosses the border, carry out the control that loads, stores and cross the border;
Scale-of-two translates stack manipulation data processing unit, be connected to the output terminal that the output terminal of general-purpose register and scale-of-two translate stack manipulation control module, complete scale-of-two according to stack pointer general-purpose register and stack boundaries general-purpose register and translate the detection of piling stack addressing and whether crossing the border, receive the control information of translating stack manipulation control module from this scale-of-two simultaneously, utilize these control informations: complete according to stack pointer general-purpose register and the stacked data width of having accessed the calculating that scale-of-two translates storehouse reference address, the calculating of stack pointer general-purpose register updated value is completed according to stack pointer general-purpose register and total stacked data width of accessing, the calculating of link register updated value is completed according to link register and instruction width, complete storehouse to cross the border the calculating of transfer address according to the storehouse transfer address general-purpose register that crosses the border, and prepare to storehouse store data or receive from storehouse load data to complete the read-write of storehouse,
General-purpose register, be connected to scale-of-two and translate the output terminal that the output terminal of stack manipulation control module and scale-of-two translate stack manipulation data processing unit, for providing scale-of-two to translate stack manipulation desired data, and translate according to scale-of-two the data that general-purpose register that stack manipulation control module provides number and scale-of-two translate stack manipulation data processing unit and provide and complete the write back operations that scale-of-two translates stack manipulation related register.
7. scale-of-two as claimed in claim 6 translates stack manipulation OverDrive Processor ODP, it is characterized in that: described scale-of-two is translated in stack manipulation control module, when decoding information instruction present instruction is stacked data load instructions and stack checking does not cross the border, this scale-of-two is translated stack manipulation control module and is generated stack pointer general-purpose register, the write-back control information of target general-purpose register set, and indicate scale-of-two to translate stack manipulation data processing unit to calculate storehouse reference address and obtain target general-purpose register set write-back with stack accessing and complete the calculating of stack pointer general-purpose register write-back value.
8. scale-of-two as claimed in claim 6 translates stack manipulation OverDrive Processor ODP, it is characterized in that: described scale-of-two is translated in stack manipulation control module, when decoding information instruction present instruction is stacked data storage instruction and stack checking does not cross the border, this scale-of-two translates the write-back control information that stack manipulation control module generates stack pointer general-purpose register and storehouse, and indicates scale-of-two to translate stack manipulation data processing unit to prepare storehouse write-back and write back address with write-back storehouse and complete the calculating of stack pointer general-purpose register write-back value.
9. scale-of-two as claimed in claim 6 translates stack manipulation OverDrive Processor ODP, it is characterized in that: described scale-of-two is translated in stack manipulation control module, when decoding information instruction present instruction is that scale-of-two translates the centering instruction of stack manipulation assisted instruction and stack checking crosses the border, this scale-of-two is translated stack manipulation control module and is generated the write-back control information of link register and storehouse and to cross the border transfer control information, and indicates scale-of-two to translate stack manipulation data processing unit to complete the calculating of link register write-back value and storehouse and to cross the border the calculating of transfer address.
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