CN104425030A - Nonvolatile memory system and method of generating bias voltage therein - Google Patents
Nonvolatile memory system and method of generating bias voltage therein Download PDFInfo
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- CN104425030A CN104425030A CN201310364202.XA CN201310364202A CN104425030A CN 104425030 A CN104425030 A CN 104425030A CN 201310364202 A CN201310364202 A CN 201310364202A CN 104425030 A CN104425030 A CN 104425030A
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Abstract
The invention discloses a nonvolatile memory system and method of generating a bias voltage therein. The nonvolatile memory system comprises a memory unit array and a bias circuit being coupled thereto. The bias circuit includes a controller and a bias voltage generator. The controller is used for erasing determining action to the memory unit array after an erasing period, wherein when at least a part of the memory unit array is not subjected to the erasing determining action, the controller generates a control signal and sends the control signal to the bias voltage generator. The bias voltage generator provides a first voltage to the memory unit array until the control signal transmitted from the controller is received. When the bias voltage generator receives the control signal from the controller, the bias voltage generator adds the first voltage, provided to the memory unit array, to a second voltage according to the control signal.
Description
Technical field
The invention relates to a kind of method of accumulator system and bias voltage storer, and relate to a kind of method of Nonvolatile memory system and bias voltage nonvolatile memory especially.
Background technology
Non-volatile memory device (as flash memory) is used in multiple electronic application widely.Generally speaking, nonvolatile memory should guarantee 100, the sequencing of 000 time or more and erase period.After repeatedly sequencing and erase period, the designated blocks of nonvolatile memory is by by the degeneration of tunnel oxide (Tunnel Oxide Degradation) abrasion, and it produces the storage unit of low transduction (Transconductance, gm) value.Determine that in order to erase the storage unit of (Erase Verify) these low transduction values is to target Critical voltage V
t, need more erase pulses, it causes storage unit too can erase (over-erased).
In order to be down to minimum by the storage unit of too erasing, non-volatile memory device can perform a pre-programmed action before erasing, and after erasing perform one erase after sequencing (Post Program) action.After erasing after erasing sequencing action by the storage unit recovering too to erase to positive critical voltage V
tscope.But, if by the storage unit of too erasing far beyond sequencing ability after erasing, after erasing, sequencing action then may be failed.
To simplify along with technology and the size of block of erasing increases, by turn unit (bit-by-bit, BbB) erase after sequencing action be introduced into, it allows lower grid voltage Vg and normal drain voltage Vd.But, even if after adopting unit (BbB) by turn to erase during sequencing action, if the excessive and high bit line electric leakage of critical voltage window exists.Along with sequencing and erase period can increase, how to improve programmed functions after there is the erasing of different bias voltage mechanism and become one of each side's research emphasis.
Summary of the invention
The invention provides a kind of Nonvolatile memory system, and a kind of method of bias voltage nonvolatile memory.
Nonvolatile memory system of the present invention, comprises memory cell array and bias circuit.Memory cell array comprises multiple bit line, multiple character line and multiple storage unit being coupled to bit line and character line.Bias circuit is coupled to memory cell array.Bias circuit comprises controller and bias generator.The action of controller control store cell array, and controller more in order to carry out to memory cell array confirmation action of erasing after an erase period.Wherein, when memory cell array at least one part not by erase confirmation action time, controller produce a control signal and transfer control signal to bias generator.Bias generator and controller couple.Bias generator provides one first voltage to memory cell array, till receiving until bias generator the control signal transmitted from controller.When bias generator receives the control signal from controller, bias generator, according to control signal, increases the first voltage to one second voltage being provided to memory cell array.
Bias voltage of the present invention comprises the method for the nonvolatile memory of memory cell array, comprises the following steps.After an erase period of nonvolatile memory, by using controller, initialization one address counter value and the fail count value in the bias circuit of nonvolatile memory.Then, confirmation action of erasing is carried out to memory cell array.When memory cell array at least one part not by erase confirmation action time, produce a control signal and transfer control signal to the bias generator in bias circuit.Then, provide one first voltage to memory cell array, till bias generator receives this control signal.When bias generator receives the control signal from controller, according to control signal, increase the first voltage to one second voltage being provided to memory cell array.
Based on above-mentioned, according to the abovementioned embodiments of the present invention, the Nonvolatile memory system of the present invention and the method for bias voltage nonvolatile memory adopt different bias voltage mechanism, to tighten the leakage current confirming voltage level and reduce bit line, thus can avoid sequencing failure, and extend the life-span of nonvolatile memory.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Figure 1A is the schematic diagram of the critical voltage distribution window of brand-new memory cell in traditional, nonvolatile memories.
Figure 1B is the schematic diagram of the critical voltage distribution window of memory cell after several erase period in traditional, nonvolatile memories.
Fig. 2 is the schematic diagram of the Nonvolatile memory system according to one embodiment of the invention.
Fig. 3 is the schematic diagram of the Nonvolatile memory system according to one embodiment of the invention.
Fig. 4 is the schematic diagram of the sensing amplifier of Nonvolatile memory system according to one embodiment of the invention.
Fig. 5 A is the schematic diagram of the critical voltage distribution window of memory cell after several erase period in traditional, nonvolatile memories.
Fig. 5 B is the schematic diagram of the critical voltage distribution window of memory cell in the Nonvolatile memory system according to one embodiment of the invention.
Fig. 6 is the process flow diagram of the method for bias voltage nonvolatile memory according to one embodiment of the invention.
Wherein, description of reference numerals is as follows:
200,300: Nonvolatile memory system
210: bias circuit
220: controller
230: bias generator
240: memory cell array
311: processor
312: specify transistor
313: memory cell
321: bit line bias generator
322: character line bias generator
400: sensing amplifier
410: the first loads
420: the second loads
430: formant
440: reference unit
CTRL: control signal
FC: fail count value
I: formant electric current
I ': reference cell current
V
t: critical voltage
WL: share character line
S610 ~ S690: each step of the method for bias voltage nonvolatile memory
Embodiment
With detailed reference to the one exemplary embodiment of the present invention, the example of described one exemplary embodiment is described in the accompanying drawings.In addition, all may part, in graphic and embodiment, use the identical or similar portions of the element/component/symbology of identical label.
Figure 1A is the schematic diagram of the critical voltage distribution window of brand-new memory cell in traditional, nonvolatile memories.Please refer to Figure 1A, transverse axis represents critical voltage (Threshold Voltage, the V of multiple memory cell in traditional, nonvolatile memories
t), and the longitudinal axis represents the quantity of memory cell.In addition, dashed curve represents the critical voltage V in an erase period background storage unit
tdistribution window (DistributionWindow), after block curve is shown in an erase period tradition erase after the critical voltage V that causes of sequencing action
tdistribution window, and two solid vertical line represent critical voltage V
tthe lower bound of distribution window.Figure 1B is the schematic diagram of the critical voltage distribution window of memory cell after several erase period in traditional, nonvolatile memories.As shown in Figure 1B, compared to Figure 1A, due to the storage unit of low transduction value (gm), become wider through the dashed curve represented by several erase period background storage unit.In addition, due to the high bit line electric leakage in traditional, nonvolatile memories, after erasing after several erase period, Programming times also becomes longer.Therefore, if because of grid low-voltage or drain electrode low-voltage and causing erase after the insufficiency of function of sequencing, the memory cell in nonvolatile memory just cannot reach target Critical voltage V
t.
As shown in Figure 1A and Figure 1B, after sequencing action after erasing, the critical voltage V between Figure 1A (brand-new storage unit) and Figure 1B (after circulation)
tthe actual lower bound of distribution window is identical, and extra parasitic problems then can occur in traditional, nonvolatile memories.But compared to Figure 1A, more memory cells in traditional, nonvolatile memories are distributed near the lower bound of Figure 1B.Therefore, in traditional, nonvolatile memories, the cut-off current (Off Current) in non-specified memory cells will increase after cycling.When sequencing nonvolatile memory, owing to being coupled to the generation of the bit line electric leakage of the nonvolatile memory of floating grid, cut-off current is called as drain electrode On current (DrainTurn-On Current).Accordingly, along with the increase of erase period, confirmation voltage level should be tightened, so as to reduce leakage current to avoid erase after sequencing failure after sequencing action, and critical voltage VT distributes, window can become close to the brand-new memory cell state shown in Figure 1A.
Fig. 2 is the schematic diagram of the Nonvolatile memory system according to one embodiment of the invention.Please refer to Fig. 2, the Nonvolatile memory system 200 according to one embodiment of the invention comprises bias circuit 210 and memory cell array 240.Bias circuit 210 comprises controller 220 and bias generator 230.Memory cell array 240 can comprise multiple bit line, multiple character line and multiple nonvolatile storage unit being coupled to bit line and character line.For the sake of clarity, other components of Nonvolatile memory system 200, such as row/column control circuit, state machine and instruction circuit are not illustrated in figure.In the present embodiment, controller 220 is applicable to the action of control store cell array 240.In addition, controller 220 in order to carry out to memory cell array 240 confirmation action of erasing after an erase period, wherein when memory cell array 240 at least one part not by erase confirmation action time, controller 220 produce a control signal CTRL and transfer control signal CTRL to bias generator 230.Bias generator 230 and controller 220 couple.Bias generator 230 provides the first voltage to memory cell array 240, till receiving until bias generator 230 the control signal CTRL reception transmitted from controller 220.And when bias generator 230 receives the control signal CTRL of controller 220, bias generator 230, according to control signal CTRL, increases the first voltage to one second voltage being provided to memory cell array 240.
Fig. 3 is the schematic diagram of the Nonvolatile memory system according to one embodiment of the invention.Please refer to Fig. 3, in the Nonvolatile memory system 300 of the present embodiment, controller 220 can comprise processor 311 and Storage Media (not illustrating).Processor 311 according to the procedure code of Storage Media being stored in controller 220, can be applicable to the method performing bias voltage Nonvolatile memory system 300.In addition, although in other embodiments of the invention, bias generator 230 only may have bit line bias generator 321 or character line bias generator 322, but bias generator 230 can comprise bit line bias generator 321 and character line bias generator 322.In the present embodiment, bit line bias generator 321 couples with at least one bit line of memory cell array 240.When rear sequencing, bit line bias generator 321, according to control signal CTRL, provides the second voltage to this at least one bit line (such as, specifying transistor 312) of memory cell array 240.Character line bias generator 322 couples with at least one character line of memory cell array 240.Character line bias generator 322, according to control signal CTRL, provides the second voltage to this at least one character line (such as, memory cell 313) of memory cell array 240.In one embodiment of this invention, within each cycle, the part of memory cell array 240 not by erase confirmation action time, a fail count value (FailCount (FC)) promoted respectively by processor 311 in controller 220, the internal count value (not illustrating) that such as processor 311 produces, and processor 311 produces control signal CTRL according to fail count value FC.
Fig. 4 is the schematic diagram of the sensing amplifier of Nonvolatile memory system according to one embodiment of the invention.Please refer to Fig. 4, the sensing amplifier 400 of the present embodiment is coupled between the first load 410 and the second load 420.Wherein, the first load 410 and the second load 420 couple with the formant 430 of memory cell array 240 and reference unit 440 respectively.In the present embodiment, according to fail count value FC, adjust the load ratio of the first load 410 to the second load 420.By adjusting the load of sensing amplifier 400, the confirmation voltage level of memory cell array 240 can be tightened, and bit line leakage current can be reduced.In an illustrative example (as shown in Figure 4), during supposing that sequencing confirms read action after erasing, the second load 420 is the half of the first load 410, and formant 430 and reference unit 440 will have shared character line WL.Along with rear sequencing number of times increases, formant electric current I increases the half of reference cell current I '.Therefore, when character line voltage increases, the electric current of formant 430 needed for during confirming read action is less than reference unit 440, and it causes pushes V
tthe lower bound of distribution window, higher than brand-new memory cell, is illustrated in Fig. 5 B.Compared to Fig. 5 A(, it is the critical voltage V of memory cell after several erase period in traditional, nonvolatile memories
tthe schematic diagram of distribution window), Fig. 5 B demonstrates critical voltage V
tthe lower bound of distribution window is obviously higher after sequencing action after the erasing of the present embodiment.
With reference to above-mentioned explanation, the bias method of the nonvolatile memory comprising memory cell array can be obtained.Fig. 6 is the process flow diagram of the method for bias voltage nonvolatile memory according to one embodiment of the invention.For example, the method described by Fig. 6 can be performed by the processor 311 be illustrated in the controller 220 of Fig. 3.Wherein, the procedure code implementing the method for Fig. 6 can be stored in the Storage Media of controller 220.Please refer to Fig. 6, in step S610, after the erase period of nonvolatile memory (such as, the Nonvolatile memory system 300 of Fig. 3), by using controller, initialization one address counter value and the fail count value in the bias circuit of nonvolatile memory.In step S630, confirmation action (after such as, erasing, sequencing confirms action) of erasing is carried out to memory cell array.If memory cell array confirms action by sequencing after the erasing of step S630, then judge whether this address counter value is maximal value (step S640).In step S620, when address counter value is not for maximal value, promotes this address counter value and reset (Reset) fail count value.On the other hand, when address counter value is maximal value, stop the method for bias voltage nonvolatile memory.If at least one part of memory cell array by the confirmation action of erasing of step S630, does not then proceed step S650.That is, within each cycle, the part of memory cell array not by step S630 erase confirmation action time, promote fail count value respectively.As shown in step S660 to step S680, depend on whether fail count value (is represented by X, Y and Z) between different parameters value, bias generator applies different voltage Vg on the character line and/or bit line of memory cell array, and then tries to achieve the load ratio of sensing amplifier.The sensing amplifier of memory cell array can be coupled between the first load and the second load, and the first load and the second load couple with the formant of memory cell array and reference unit respectively.If fail count value is lower than the first parameter value X(step S660), the voltage Vg of at least one bit line and/or character line that put on memory array will be set as the first voltage (such as, be maintained at a predeterminated voltage), and in step S665, adjustment load ratio is the first load ratio (such as, is maintained at one and presets load ratio).If fail count value is between the first parameter value X and the second parameter value Y (step S670), the voltage Vg of at least one bit line and/or character line that put on memory array will be set as the second voltage (such as, increase this predeterminated voltage), and in step S675, adjustment load ratio is the second load ratio.If fail count value is between the second parameter value Y and the 3rd parameter value Z (step S680), the voltage Vg of at least one bit line and/or character line that put on memory array will be set as tertiary voltage (such as, increase this predeterminated voltage), and to adjust load ratio be the 3rd load ratio.It is noted that in the present embodiment, parameter value X, Y, Z can set according to an actual operation condition, the required life-span of such as nonvolatile memory.Subsequently, according to load ratio and voltage Vg, sequencing pulse after this memory cell array applying one is erased, and be back to step S630.
In sum, according to embodiments of the invention, the method of Nonvolatile memory system of the present invention and bias voltage nonvolatile memory adopts different bias voltage mechanism, to tighten the leakage current confirming voltage level and reduce bit line, thus can avoid sequencing failure, and extend the life-span of nonvolatile memory.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (13)
1. a Nonvolatile memory system, comprising:
One memory cell array, comprises multiple bit line, multiple character line and multiple nonvolatile storage unit being coupled to described multiple bit line and described multiple character line; And
One bias circuit, is coupled to this memory cell array, comprises:
One controller, control the action of this memory cell array, this controller in order to carry out to this memory cell array confirmation action of erasing after an erase period, wherein when this memory cell array at least one part not by this erase confirmation action time, this controller produces a control signal and transmits this and controls signal to a bias generator; And
This bias generator, be coupled to this controller, wherein this bias generator provides one first voltage to this memory cell array, till receiving until bias generator this control signal transmitted from this controller, and when this bias generator receives this control signal from this controller, this bias generator, according to this control signal, increases this first voltage to one second voltage being provided to this memory cell array.
2. Nonvolatile memory system as claimed in claim 1, wherein this bias generator comprises:
One bit line bias generator, is coupled at least one bit line of this memory cell array, and wherein this bit line bias generator is according to this control signal, provides this second voltage to this at least one bit line of this memory cell array.
3. Nonvolatile memory system as claimed in claim 1, wherein this bias generator comprises:
One character line bias generator, is coupled at least one character line of this memory cell array, and wherein this character line bias generator is according to this control signal, provides this second voltage to this at least one character line of this memory cell array.
4. Nonvolatile memory system as claimed in claim 1, wherein within each cycle, this part of this memory cell array not by this erase confirmation action time, a fail count value promoted respectively by this controller, and according to this fail count value, produce this control signal by this controller.
5. Nonvolatile memory system as claimed in claim 4, also comprises:
One sensing amplifier, is coupled between one first load and one second load, and wherein this first load and this second load couple with a formant of this memory cell array and a reference unit respectively.
6. Nonvolatile memory system as claimed in claim 5, wherein
The load ratio of this first load to this second load is adjusted according to this fail count value.
7. bias voltage comprises a method for a nonvolatile memory of a memory cell array, and the method comprises:
After an erase period of this nonvolatile memory, by using the controller in a bias circuit of this nonvolatile memory, initialization one address counter value and a fail count value;
Confirmation action of erasing is carried out to this memory cell array;
When this memory cell array at least one part not by this erase confirmation action time, produce a control signal and transmit this and control signal to a bias generator in this bias circuit; And
There is provided one first voltage to this memory cell array, till this bias generator receives this control signal, and when this bias generator receives this control signal from this controller, according to this control signal, increase this first voltage to one second voltage being provided to this memory cell array.
8. the method for bias voltage nonvolatile memory as claimed in claim 7, the step being wherein provided to this first voltage to one second voltage of this memory cell array according to this control signal increase also comprises:
According to this control signal, provide this second voltage at least one bit line of this memory cell array.
9. the method for bias voltage nonvolatile memory as claimed in claim 7, the step being wherein provided to this first voltage to one second voltage of this memory cell array according to this control signal increase also comprises:
According to this control signal, provide this second voltage at least one character line of this memory cell array.
10. the method for bias voltage nonvolatile memory as claimed in claim 7, wherein this step of erasing confirmation action is carried out to this memory cell array and also comprise:
Within each cycle, this part of this memory cell array not by this erase confirmation action time, promote this fail count value respectively, wherein according to this fail count value, produce this control signal.
The method of 11. bias voltage nonvolatile memories as claimed in claim 10, wherein the method also comprises:
Couple a sensing amplifier of this memory cell array between one first load and one second load, and couple this first load and this second formant and reference unit being loaded to this memory cell array respectively.
The method of 12. bias voltage nonvolatile memories as claimed in claim 11, wherein the method also comprises:
According to this fail count value, adjust the load ratio of this first load to this second load.
The method of 13. bias voltage nonvolatile memories as claimed in claim 7, wherein the method also comprises:
When this address counter value is not for maximal value, promote this address counter value; And
When this address counter value is for maximal value, stop this nonvolatile memory of bias voltage.
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Cited By (1)
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| CN106445404A (en) * | 2015-08-13 | 2017-02-22 | 群联电子股份有限公司 | Memory programming method, memory control circuit unit and memory storage device |
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| US6269025B1 (en) * | 2000-02-09 | 2001-07-31 | Advanced Micro Devices, Inc. | Memory system having a program and erase voltage modifier |
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