CN104393019A - Display base plate and preparation method thereof, and display device - Google Patents
Display base plate and preparation method thereof, and display device Download PDFInfo
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- CN104393019A CN104393019A CN201410643149.1A CN201410643149A CN104393019A CN 104393019 A CN104393019 A CN 104393019A CN 201410643149 A CN201410643149 A CN 201410643149A CN 104393019 A CN104393019 A CN 104393019A
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Abstract
The invention discloses a display base plate, a preparation method of the display base plate, and a display device. The display base plate comprises a substrate base plate, a grid line and a data wire, wherein the grid line and the data wire are positioned on the substrate base plate and used for limiting a pixel unit, wherein the pixel unit comprises a thin film transistor and a pixel electrode; the thin film transistor comprises a grid electrode, an active layer and a source/ drain electrode; an assisting layer is also arranged on the substrate base plate; a first groove is arranged in the assisting layer; the grid electrode and the grid line are both positioned into the first groove. With the adoption of the display base plate, that the coverage characteristic of a grid insulating layer at the sidewall is lowered down as the thickness of the grid electrode layer increases and even the risk of wrinkling or breaking occurs can be reduced; moreover, a thin grid insulating layer can be adopted although a thick grid electrode layer is put into use because of the protection of the assisting layer, and therefore, the ON-state current of the thin film transistor can be improved.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of display base plate and preparation method thereof, display unit.
Background technology
For large scale, high-frequency AMOLED display screen, in order to reduce RC delay effect (RC delay), need the grid layer adopting thickness higher, when the enlarged in thickness of grid layer, the thickness of gate insulation layer also needs to strengthen, thus realize covering preferably to sidewall (side wall) place of grid line, ensure the evenness of the upper surface of gate insulation layer simultaneously.But the thickness increase of grid layer can cause the coverage property of sidewall (side wall) place's gate insulation layer to be deteriorated and even occur fold or fracture.
Summary of the invention
For solving the problem, the invention provides a kind of display base plate and preparation method thereof, display unit, the thickness increase for solving grid layer in prior art causes the coverage property of side-walls gate insulation layer to be deteriorated and even occurs the problem of fold or fracture.
For this reason, the invention provides a kind of display base plate, the grid line comprising underlay substrate and be positioned on described underlay substrate and data wire, described grid line and described data wire limit pixel cell, described pixel cell comprises thin-film transistor and pixel electrode, and described thin-film transistor comprises grid, active layer and source-drain electrode; Described underlay substrate is also provided with auxiliary layer, described auxiliary layer is provided with the first groove, described grid and described grid line are positioned at described first groove.
Optionally, the material of described auxiliary layer is resin or polyimides.
Optionally, the thickness of described grid and described grid line is greater than the degree of depth of described first groove.
Optionally, the thickness of described grid and described grid line is 1.25 times of the degree of depth of described first groove.
Optionally, the thickness range of described grid and described grid line is 400-1500nm, and the depth bounds of described first groove is 320-1200nm.
Optionally, the width at the top of described grid and described grid line is greater than the width at the top of described first groove.
Optionally, the width at the top of described grid and described grid line 0.5-3 μm larger than the width at the top of described first groove.
Optionally, the width at the top of described grid and described grid line 1-2 μm larger than the width at the top of described first groove.
The present invention also provides a kind of display unit, comprises above-mentioned arbitrary display base plate.
The present invention also provides a kind of preparation method of display base plate, comprising: on underlay substrate, form auxiliary layer, described auxiliary layer is provided with the first groove; Grid and grid line is formed in described first groove; Active layer is formed above described grid; Above described underlay substrate, form source-drain electrode and data wire, described source-drain electrode is positioned at described active layer; Pixel electrode is formed above described underlay substrate.
The present invention has following beneficial effect:
In display base plate provided by the invention and preparation method thereof, display unit, described thin-film transistor comprises grid, active layer and source-drain electrode, described underlay substrate is also provided with auxiliary layer, described auxiliary layer is provided with the first groove, described grid and described grid line are positioned at described first groove, and the thickness increase that can reduce due to grid layer causes the coverage property of side-walls gate insulation layer variation even to occur the risk of fold or fracture.In addition, due to the protection of described auxiliary layer, even if adopt the grid layer that thickness is larger, also can adopt the gate insulation layer that thickness is less, thus the ON state current of thin-film transistor can be improved.
Accompanying drawing explanation
The structural representation of a kind of display base plate that Fig. 1 provides for the embodiment of the present invention one;
The flow chart of the manufacture method of a kind of display base plate that Fig. 2 provides for the embodiment of the present invention three;
Fig. 3 is the schematic diagram forming auxiliary layer in embodiment three;
Fig. 4 is the schematic diagram forming grid and grid line in embodiment three.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with accompanying drawing, display base plate provided by the invention and preparation method thereof, display unit are described in detail.
Embodiment one
The structural representation of a kind of display base plate that Fig. 1 provides for the embodiment of the present invention one.As shown in Figure 1, described display base plate comprises underlay substrate 101 and the grid line be positioned on described underlay substrate 101 and data wire, and described grid line and described data wire limit pixel cell, and described pixel cell comprises thin-film transistor and pixel electrode.Described thin-film transistor comprises grid, active layer 104, source electrode 105 and drain electrode 106.Also be provided with auxiliary layer 102 on described underlay substrate 101, described auxiliary layer 102 is provided with the first groove, described grid and described grid line are positioned at described first groove.In the present embodiment, described grid and described grid line are referred to as gate patterns 103, described gate patterns 103 is positioned at described first groove, and the thickness increase that can reduce due to grid layer causes the coverage property of side-walls gate insulation layer variation even to occur the risk of fold or fracture.In addition, due to the protection of described auxiliary layer, even if adopt the grid layer that thickness is larger, also can adopt the gate insulation layer that thickness is less, thus the ON state current of thin-film transistor can be improved.
In the present embodiment, described auxiliary layer 102 is also provided with the second groove, in described second groove, is provided with gate metal 107.Described auxiliary layer 102 is provided with gate insulation layer 108, and described active layer 104 is arranged on described gate insulation layer 108, and described active layer 104 is provided with etching barrier layer 109.Described source electrode 105 and described drain electrode 106 are arranged on described etching barrier layer 109, and described drain electrode 106 is connected with described gate metal 107 by the first via hole 201.Described source electrode 105 and described drain electrode 106 are also provided with passivation layer 202, described passivation layer 202 is provided with pixel electrode 203, described pixel electrode 203 is connected with described drain electrode 106 by the second via hole 204.
Optionally, the material of described auxiliary layer 102 is resin or polyimides.Described gate patterns 103 is just in time limited in, in the first groove of described resin or polyimides formation, can playing the effect of planarization.And, when the auxiliary layer that described resin or polyimides are formed is applied to flexible display panels, can pliability be increased, thus reduce the risk of grid line fracture.
In the present embodiment, the thickness of described gate patterns 103 is greater than the degree of depth of described first groove.Preferably, the thickness of described gate patterns 103 is 1.25 times of the degree of depth of described first groove.Preferred, the thickness range of described gate patterns 103 is 400-1500nm, and the depth bounds of described first groove is 320-1200nm.The thickness of described gate patterns 103 is greater than the degree of depth of described first groove, thus avoids better damaging grid line due to bending.
In the present embodiment, the thickness of described gate metal 107 is greater than the degree of depth of described second groove.Preferably, the thickness of described gate metal 107 is 1.25 times of the degree of depth of described second groove.Preferred, the thickness range of described gate metal 107 is 400-1500nm, and the depth bounds of described second groove is 320-1200nm.The thickness of described gate metal 107 is greater than the degree of depth of described second groove, thus avoids better damaging grid line due to bending.
In the present embodiment, the width at the top of described gate patterns 103 is greater than the width at the top of described first groove.Preferably, the width at the top of described gate patterns 103 0.5-3 μm larger than the width at the top of described first groove.Preferred, the width 1-2 μm larger than the width at the top of described first groove at the top of described gate patterns 103.The width at the top of described gate patterns 103 is greater than the width at the top of described first groove, thus avoids better damaging grid line due to bending.
In the present embodiment, the width at the top of described gate metal 107 is greater than the width at the top of described second groove.Preferably, the width at the top of described gate metal 107 0.5-3 μm larger than the width at the top of described second groove.Preferred, the width 1-2 μm larger than the width at the top of described second groove at the top of described gate metal 107.The width at the top of described gate metal 107 is greater than the width at the top of described second groove, thus avoids better damaging grid line due to bending.
In the display base plate that the present embodiment provides, described thin-film transistor comprises grid, active layer and source-drain electrode, described underlay substrate is also provided with auxiliary layer, described auxiliary layer is provided with the first groove, described grid and described grid line are positioned at described first groove, and the thickness increase that can reduce due to grid layer causes the coverage property of side-walls gate insulation layer variation even to occur the risk of fold or fracture.In addition, due to the protection of described auxiliary layer, even if adopt the grid layer that thickness is larger, also can adopt the gate insulation layer that thickness is less, thus the ON state current of thin-film transistor can be improved.
Embodiment two
Present embodiments provide a kind of display unit, comprise the display base plate that embodiment one provides, particular content can refer to the description in above-described embodiment one, repeats no more herein.
In the display unit that the present embodiment provides, described thin-film transistor comprises grid, active layer and source-drain electrode, described underlay substrate is also provided with auxiliary layer, described auxiliary layer is provided with the first groove, described grid and described grid line are positioned at described first groove, and the thickness increase that can reduce due to grid layer causes the coverage property of side-walls gate insulation layer variation even to occur the risk of fold or fracture.In addition, due to the protection of described auxiliary layer, even if adopt the grid layer that thickness is larger, also can adopt the gate insulation layer that thickness is less, thus the ON state current of thin-film transistor can be improved.
Embodiment three
The flow chart of the manufacture method of a kind of display base plate that Fig. 2 provides for the embodiment of the present invention three.As shown in Figure 2, the manufacture method of described display base plate comprises:
Step 2001, on underlay substrate, form auxiliary layer, described auxiliary layer is provided with the first groove.
Fig. 3 is the schematic diagram forming auxiliary layer in embodiment three.As shown in Figure 3, underlay substrate 101 forms auxiliary layer 102, described auxiliary layer 102 is provided with the first groove 205.Optionally, described auxiliary layer 102 is also provided with the second groove 206.
Step 2002, in described first groove, form grid and grid line.
Fig. 4 is the schematic diagram forming grid and grid line in embodiment three.As shown in Figure 4, in described first groove 205, grid and grid line is formed.Optionally, in described second groove 206, gate metal 107 is formed.In the present embodiment, described grid and described grid line are referred to as gate patterns 103, described gate patterns 103 is positioned at described first groove, and the thickness increase that can reduce due to grid layer causes the coverage property of side-walls gate insulation layer variation even to occur the risk of fold or fracture.In addition, due to the protection of described auxiliary layer, even if adopt the grid layer that thickness is larger, also can adopt the gate insulation layer that thickness is less, thus the ON state current of thin-film transistor can be improved.
Step 2003, above described grid, be formed with active layer.
In the present embodiment, on described grid, form gate insulation layer 108, described gate insulation layer 108 is formed with active layer 104.
Step 2004, above described underlay substrate, form source-drain electrode and data wire, described source-drain electrode is positioned at described active layer.
In the present embodiment, form etching barrier layer 109 and the first via hole 201 on described active layer 104, described first via hole 201 runs through described gate insulation layer 108 and described etching barrier layer 109.On described etching barrier layer 109, form source electrode 105 and drain electrode 106, described drain electrode 106 is connected with described gate metal 107 by described first via hole 201.
Step 2005, above described underlay substrate, form pixel electrode.
In the present embodiment, on described source electrode 105 and described drain electrode 106, form passivation layer 202 and the second via hole 204.On described passivation layer 202, form pixel electrode 203, described pixel electrode 203 is connected with described drain electrode 106 by described second via hole 204.
In the preparation method of the display base plate that the present embodiment provides, described thin-film transistor comprises grid, active layer and source-drain electrode, described underlay substrate is also provided with auxiliary layer, described auxiliary layer is provided with the first groove, described grid and described grid line are positioned at described first groove, and the thickness increase that can reduce due to grid layer causes the coverage property of side-walls gate insulation layer variation even to occur the risk of fold or fracture.In addition, due to the protection of described auxiliary layer, even if adopt the grid layer that thickness is larger, also can adopt the gate insulation layer that thickness is less, thus the ON state current of thin-film transistor can be improved.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (10)
1. a display base plate, it is characterized in that, the grid line comprising underlay substrate and be positioned on described underlay substrate and data wire, described grid line and described data wire limit pixel cell, described pixel cell comprises thin-film transistor and pixel electrode, and described thin-film transistor comprises grid, active layer and source-drain electrode;
Described underlay substrate is also provided with auxiliary layer, described auxiliary layer is provided with the first groove, described grid and described grid line are positioned at described first groove.
2. display base plate according to claim 1, is characterized in that, the material of described auxiliary layer is resin or polyimides.
3. display base plate according to claim 1, is characterized in that, the thickness of described grid and described grid line is greater than the degree of depth of described first groove.
4. display base plate according to claim 3, is characterized in that, the thickness of described grid and described grid line is 1.25 times of the degree of depth of described first groove.
5. display base plate according to claim 4, is characterized in that, the thickness range of described grid and described grid line is 400-1500nm, and the depth bounds of described first groove is 320-1200nm.
6. display base plate according to claim 1, is characterized in that, the width at the top of described grid and described grid line is greater than the width at the top of described first groove.
7. display base plate according to claim 6, is characterized in that, the width 0.5-3 μm larger than the width at the top of described first groove at the top of described grid and described grid line.
8. display base plate according to claim 7, is characterized in that, the width 1-2 μm larger than the width at the top of described first groove at the top of described grid and described grid line.
9. a display unit, is characterized in that, comprises the arbitrary described display base plate of claim 1 to 8.
10. a preparation method for display base plate, is characterized in that, comprising:
Underlay substrate forms auxiliary layer, described auxiliary layer is provided with the first groove;
Grid and grid line is formed in described first groove;
Active layer is formed above described grid;
Above described underlay substrate, form source-drain electrode and data wire, described source-drain electrode is positioned at described active layer;
Pixel electrode is formed above described underlay substrate.
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| CN201410643149.1A CN104393019B (en) | 2014-11-07 | 2014-11-07 | A kind of display base plate and preparation method thereof, display device |
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| CN201410643149.1A CN104393019B (en) | 2014-11-07 | 2014-11-07 | A kind of display base plate and preparation method thereof, display device |
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