CN104375954B - 基于工作负载实施对高速缓存的动态启用和禁用的方法和计算机系统 - Google Patents
基于工作负载实施对高速缓存的动态启用和禁用的方法和计算机系统 Download PDFInfo
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- CN104375954B CN104375954B CN201410383754.XA CN201410383754A CN104375954B CN 104375954 B CN104375954 B CN 104375954B CN 201410383754 A CN201410383754 A CN 201410383754A CN 104375954 B CN104375954 B CN 104375954B
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- Prior art keywords
- cache
- predefined
- workload
- memory controller
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/50—Control mechanisms for virtual memory, cache or TLB
- G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/964,365 | 2013-08-12 | ||
US13/964,365 US9235517B2 (en) | 2013-08-12 | 2013-08-12 | Implementing dynamic cache enabling and disabling based upon workload |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104375954A CN104375954A (zh) | 2015-02-25 |
CN104375954B true CN104375954B (zh) | 2018-03-27 |
Family
ID=52449625
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410383754.XA Expired - Fee Related CN104375954B (zh) | 2013-08-12 | 2014-08-06 | 基于工作负载实施对高速缓存的动态启用和禁用的方法和计算机系统 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9235517B2 (zh) |
CN (1) | CN104375954B (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9170943B2 (en) * | 2013-08-29 | 2015-10-27 | Globalfoundries U.S. 2 Llc | Selectively enabling write caching in a storage system based on performance metrics |
US9575897B2 (en) * | 2015-07-09 | 2017-02-21 | Centipede Semi Ltd. | Processor with efficient processing of recurring load instructions from nearby memory addresses |
US10185561B2 (en) | 2015-07-09 | 2019-01-22 | Centipede Semi Ltd. | Processor with efficient memory access |
US9940255B2 (en) | 2015-11-09 | 2018-04-10 | International Business Machines Corporation | Implementing hardware accelerator for storage write cache management for identification of data age in storage write cache |
US10152421B2 (en) * | 2015-11-23 | 2018-12-11 | Intel Corporation | Instruction and logic for cache control operations |
KR101887741B1 (ko) * | 2016-04-11 | 2018-09-11 | 전자부품연구원 | 적응적 블록 캐시 운용 방법 및 이를 적용한 dbms |
US10078591B2 (en) | 2016-09-27 | 2018-09-18 | International Business Machines Corporation | Data storage cache management |
US10802976B2 (en) * | 2018-04-24 | 2020-10-13 | SK Hynix Inc. | Storage device and method of operating the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4942518A (en) * | 1984-06-20 | 1990-07-17 | Convex Computer Corporation | Cache store bypass for computer |
US5625793A (en) * | 1991-04-15 | 1997-04-29 | International Business Machines Corporation | Automatic cache bypass for instructions exhibiting poor cache hit ratio |
US5729713A (en) * | 1995-03-27 | 1998-03-17 | Texas Instruments Incorporated | Data processing with first level cache bypassing after a data transfer becomes excessively long |
US6128717A (en) * | 1998-01-20 | 2000-10-03 | Quantum Corporation | Method and apparatus for storage application programming interface for digital mass storage and retrieval based upon data object type or size and characteristics of the data storage device |
US7461230B1 (en) * | 2005-03-31 | 2008-12-02 | Symantec Operating Corporation | Maintaining spatial locality of write operations |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5163142A (en) * | 1988-10-28 | 1992-11-10 | Hewlett-Packard Company | Efficient cache write technique through deferred tag modification |
US6345341B1 (en) | 1999-06-24 | 2002-02-05 | International Business Machines Corporation | Method of cache management for dynamically disabling O state memory-consistent data |
US20030033593A1 (en) | 2001-08-08 | 2003-02-13 | Evelyn Duesterwald | Dynamic execution layer interface for explicitly or transparently executing application or system binaries |
US6981112B2 (en) | 2002-08-26 | 2005-12-27 | International Business Machines Corporation | Dynamic cache disable |
US6922754B2 (en) * | 2002-12-09 | 2005-07-26 | Infabric Technologies, Inc. | Data-aware data flow manager |
JP4313068B2 (ja) * | 2003-03-28 | 2009-08-12 | 株式会社日立製作所 | 記憶装置のキャッシュ管理方法 |
US8161240B2 (en) * | 2007-10-10 | 2012-04-17 | Apple Inc. | Cache management |
US8312181B1 (en) | 2009-12-11 | 2012-11-13 | Netapp, Inc. | Initiation of read-ahead requests |
US8924645B2 (en) * | 2010-03-08 | 2014-12-30 | Hewlett-Packard Development Company, L. P. | Data storage apparatus and methods |
US8566521B2 (en) | 2010-09-01 | 2013-10-22 | International Business Machines Corporation | Implementing cache offloading |
US9552301B2 (en) * | 2013-07-15 | 2017-01-24 | Advanced Micro Devices, Inc. | Method and apparatus related to cache memory |
-
2013
- 2013-08-12 US US13/964,365 patent/US9235517B2/en not_active Expired - Fee Related
-
2014
- 2014-08-06 CN CN201410383754.XA patent/CN104375954B/zh not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4942518A (en) * | 1984-06-20 | 1990-07-17 | Convex Computer Corporation | Cache store bypass for computer |
US5625793A (en) * | 1991-04-15 | 1997-04-29 | International Business Machines Corporation | Automatic cache bypass for instructions exhibiting poor cache hit ratio |
US5729713A (en) * | 1995-03-27 | 1998-03-17 | Texas Instruments Incorporated | Data processing with first level cache bypassing after a data transfer becomes excessively long |
US6128717A (en) * | 1998-01-20 | 2000-10-03 | Quantum Corporation | Method and apparatus for storage application programming interface for digital mass storage and retrieval based upon data object type or size and characteristics of the data storage device |
US7461230B1 (en) * | 2005-03-31 | 2008-12-02 | Symantec Operating Corporation | Maintaining spatial locality of write operations |
Non-Patent Citations (3)
Title |
---|
Improving Cache Performance by Selective Cache Bypass;CH-Hung Chi 等;《Hawaii International Conference on System Sciences》;IEEE;19890106;第277-285页 * |
Optimal Bypass Monitor for High Performance Last-level Caches;Lingda Li 等;《International conference on Parallel architectures and compilation techniques》;ACM;20120923;第315-324页 * |
Run-time Adaptive Cache Hierarchy Management Via Reference Analysis;Teresa L.Johnson 等;《International Symposium on Computer Architecture》;ACM;19970604;第315-326页 * |
Also Published As
Publication number | Publication date |
---|---|
US20150046648A1 (en) | 2015-02-12 |
US9235517B2 (en) | 2016-01-12 |
CN104375954A (zh) | 2015-02-25 |
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Effective date of registration: 20171122 Address after: Grand Cayman, Cayman Islands Applicant after: GLOBALFOUNDRIES INC. Address before: American New York Applicant before: Core USA second LLC Effective date of registration: 20171122 Address after: American New York Applicant after: Core USA second LLC Address before: New York grams of Armand Applicant before: International Business Machines Corp. |
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