CN1043696C

CN1043696C - Memory array device

Info

Publication number: CN1043696C
Application number: CN94115285A
Authority: CN
Inventors: 邓永佳
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 1994-09-16
Filing date: 1994-09-16
Publication date: 1999-06-16
Anticipated expiration: 2014-09-16
Also published as: CN1122043A

Abstract

The present invention relates to a storage queue device which comprises a shift register for storing input data, a multi-path selector for selecting any output end on the shift register as the position of output data, a counter for counting data digits stored in the shift register so as to control the selection of the multi-path selector for the position of data output on the shift register and a detection circuit for receiving data outputted by the counter so as to detect a data state in the shift register, wherein when the data is stacked in the shift register, an overflow signal is sent; when the data in the shift register is read, a zero signal is sent. The present invention can access the data in time.

Description

Memory array device

The present invention relates to a kind of memory array (queue) device, it is with the mode access data of first in first out (FirstIn First Out).

Know in the technology, storehouse (stack) is access data device commonly used with memory array.The mode that its difference is storehouse then is that the data that deposit in earlier can be removed earlier in memory array for the data of putting into after can be removed (promptly last in, first out, Last In First Out) earlier.The memory array of knowing with the shift register composition, as shown in Figure 1, when being pressed into signal (push) or ejecting signal (pop) for high level, the data in registers at different levels just can move on in the next stage register.Also just therefore, the disadvantage that this memory array device of knowing has for when the length (being the progression of shift register) of the data bits that be pressed into and formation not simultaneously, then must supply the figure place or the time clock of data, just can read correct data, the speed of the data access that so will slow down.

In view of this, in order to improve the shortcoming of knowing memory array device, purpose of the present invention promptly is to propose a kind of memory array device of novelty, and its arbitrary output terminal that can select on the shift register is its outgoing position, thereby reaches the requirement of immediate access data.

Memory array device of the present invention comprises:

One shift register is in order to store the data of input;

One MUX is in order to select arbitrary output terminal on the described shift register as the position of output data; And

One counter is present in data bits in the described shift register in order to counting, and controls the selection of described MUX to the data outgoing position on the described shift register in view of the above.

Method of the present invention is to utilize a MUX to select outgoing position on the shift register, utilize a counter to control aforementioned MUX simultaneously, and the action of aforementioned counter is to increase progressively when being pressed into data, and successively decreases when ejecting data.

In order more to clearly reveal structure of the present invention, method and characteristics, below conjunction with figs. is elaborated to a preferred embodiment.

Brief Description Of Drawings

Fig. 1 is a circuit diagram of knowing memory array device;

Fig. 2 is the circuit diagram of memory array device of the present invention.

See also Fig. 2, a preferred embodiment of memory array device of the present invention comprises: the shift register 10 of a n level, in order to storage data; One MUX 20 is the position of output data in order to select the arbitrary output terminal on the aforementioned shift register 10; And a counter 30, aforementioned counter 30 can be carried out the counting of increasing or decreasing, is present in data bits in the shift register 10 that advances in order to counting, and if counter 30 is output as the m position, then must satisfy 2 ^mThe condition of-1 〉=n.In addition, also comprise in the present invention by one with door (AND gate) 31 and one rejection gate (NOR gate) 32 testing circuits that constituted 33, in order to detect the data mode in the aforementioned shift register 10, if data have been read and have finished, then export a zero-signal (Zero), if data have piled with shift register, then export a spill over (Over).

The operating type of aforementioned memory array device of the present invention is as described below: please consult Fig. 2 again, similarly, being pressed into being pressed into of signal (PUSH) control data, and to eject the ejection of signal (POP) control data.At first, when being pressed into signal (PUSH) for high level, promptly represent data are pressed in the next stage shift register, and counter 30 is added 1 and the data of counter 30 itself are reached MUX 20, make MUX 20 can select first shift register to be output, same mode, after being pressed into the X bit data, MUX 20 is subjected to the control of counter 30 and selects X shift register to be output as output.Then, when ejection signal (POP) is high level, promptly indicate data are ejected from shift register, this moment, shift register 10 was failure to actuate, but counter 30 subtracts 1 after receiving the high level that ejects signal (POP), so bulged-in at first data are read, MUX 20 just changes into and selects its previous stage shift register to be output as output simultaneously.From the above, the output terminal of memory array device of the present invention is the data of writing and then not being read the earliest forever.

In Fig. 2, also can find out the effect of testing circuit 33, promptly when the m bit data of counter 30 outputs is logical one, be output as high level with door 31, represent that promptly shift register 10 overflows, similarly, if when the m bit data of counter 30 output is logical zero, rejection gate 32 output high level have been read with the data in the expression shift register 10 and have finished.As for the zero setting signal (Reset) among the figure is in order to removing the data in the shift register, promptly when counter 30 receives the zero setting signal after, and just auto zero, MUX 20 is just selected input end I at this moment _oBe its output.

Claims

1. memory array device comprises:

One shift register is in order to store the data of input;

It is characterized in that described memory array device also comprises

2. memory array device as claimed in claim 1, it is characterized in that described counter can carry out increasing or decreasing counting, when being pressed into data to the described shift register the time, described counter is carried out and is increased progressively counting, and when ejecting data from described shift register, described counter is carried out countdown.

3. memory array device as claimed in claim 1, it is characterized in that also comprising a testing circuit, in order to receive the data of described counter output, and detect data mode in the described shift register in view of the above, when being piled with data in the described shift register, spread out of a spill over, and spread out of a zero-signal when the interior data of described shift register are read to finish.

4. memory array device as claimed in claim 3, it is characterized in that described testing circuit comprise one with the door and a rejection gate.