CN104362988A - Circuit for linearization of power amplifier - Google Patents
Circuit for linearization of power amplifier Download PDFInfo
- Publication number
- CN104362988A CN104362988A CN201410427087.0A CN201410427087A CN104362988A CN 104362988 A CN104362988 A CN 104362988A CN 201410427087 A CN201410427087 A CN 201410427087A CN 104362988 A CN104362988 A CN 104362988A
- Authority
- CN
- China
- Prior art keywords
- circuit
- electric capacity
- pmos
- grid
- power amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
Abstract
The invention relates to a circuit for linearization of a power amplifier, is mainly applied to linearization application of a radio frequency power amplifier, and belongs to the design field of radio frequency integrated circuits. The circuit adopts the structure that a PMOS is connected in parallel with the grid end of an NMOS according to the characteristic that the grid capacitance of the NMOS and that of the PMOS are complimentary along with the grid voltage variation; the grid capacitance of the NMOS is compensated by that of the PMOS, so that the input terminal capacitance of the circuit is a constant during grid voltage variation. Therefore, when the input amplitude of the circuit changes under a large signal work mode of the circuit of the power amplifier, the input terminal capacitance of the circuit is a constant; nonlinearity caused by grid capacitance variation of the NMOS is eliminated; the degree of linearity of the power amplifier is improved. Moreover, when the design of the power amplifier adopts PMOS, the PMOS can be compensated through the NMOS to realize linearization of the power amplifier.
Description
Technical field
The present invention relates to the circuit that a kind of power amplifier linearization compensates, be mainly used in the linearisation application of radio-frequency power amplifier, belong to field of radio frequency circuit design.
Background technology
Power amplifier is the important module in radio-frequency transmissions path, its major function is that the amplification that transmits is transferred to antenna, power amplifier is operated in large-scale condition, very large on the linearity impact of emission system, especially adopt at the same time in the communications applications of amplitude, phase-modulation, power amplifier is larger on the impact of system linear degree.Therefore power amplifier often has higher linearity, should analyze the source of causing non-linearity of power amplifier, improve the linearity by linearization technique in design.
Adopt amplitude and phase-modulation application scenario at the same time, in order to take into account the power of power amplifier, efficiency and the linearity, power amplifier is generally operational in AB class or category-A, and under large signal operation state, the transistor gate terminal voltage of common source configuration changes with input signal.NMOS and PMOS device grid source electric capacity are with grid voltage nonlinear change, and in the power amplifiers, along with the change of input signal, NMOS or PMOS device gate source voltage change, and gate capacitance also changes thereupon, cause phase place and the amplitude distortion of signal.In order to improve the linearity of power amplifier, need in design to adopt linearization technique to eliminate the non-linear impact caused of grid end electric capacity.
NMOS and PMOS device gate capacitance are made up of grid source electric capacity and gate leakage capacitance, and wherein gate leakage capacitance is substantially constant with grid voltage, and when analysis device gate capacitance is with capacitance variations relation, we only need consider grid source capacitance with voltage variation relation.Analysis shows, NMOS and PMOS device grid source electric capacity just complementary with gate source voltage variation tendency, if NMOS and PMOS grid end is in parallel, under choosing suitable device size situation, can make input end capacitor with grid voltage change substantially remain unchanged, close to constant.
Summary of the invention
This circuit structure is mainly applied in Class A or AB class Linear Power Amplifier, by the mode that NMOS and PMOS gate capacitance compensates, gate capacitance is made to be constant, thus when signal input range changes, input capacitance perseverance is constant, it is non-linear that elimination causes because gate capacitance change, improves the linearity of power amplifier.
In order to solve above technical requirement, the circuit structure that the present invention proposes as shown in Figure 1.
Wherein, NMOS tube M1, resistance R1, inductance L 1 and electric capacity C1, C2 form power amplification circuit 110.The inner annexation of power amplification circuit 110 is: one end of C1 inputs as signal, and one end connects the grid of M1 in addition; Resistance R1 one end is as the input of M1 bias voltage Vg, and the other end connects M1 grid; Inductance one end connects the power vd D1 of power amplifier, and the other end connects the drain electrode of M1; The source ground of NMOS tube M1; Electric capacity C2 one end connects the drain electrode of M1, and the other end is then connected to match circuit 120 as output.
Match circuit 120 is made up of transmission line, electric capacity, inductance or resistance, mainly plays impedance transformation.The output of match circuit 120 connects equivalent load Rload, and equivalent load material object can be antenna etc.
PMOS M2, resistance R2 and electric capacity C3 form compensating circuit 130.The source electrode of PMOS, drain electrode short circuit, and be connected respectively to one end of resistance R2 and electric capacity C3; The resistance R2 other end connects the power vd D2 of compensating circuit; The other end then ground connection or certain fixed level of electric capacity C3.
The annexation of power amplification circuit 110, match circuit 120 and compensating circuit 130 is: the grid of the NMOS tube M1 of power power amplification circuit 110 is connected with compensating circuit 130 grid; The output of power amplification circuit 110 i.e. one end of C2 are connected to match circuit 120.
Operation principle is: nmos device is power amplifying device, is operated in AB class or category-A state, realizes power amplification at signal path; As compensation of PMOS device, grid end parallel connection access nmos device grid end, drain terminal and source short circuit, connect power circuit; The power circuit of nmos device and PMOS device and power source deoupling circuit.Because NMOS and PMOS device gate capacitance are with the complementation of change in voltage, make under arbitrary grid voltage, input end capacitor is close to constant.When circuit input end has signal to input, NMOS and PMOS device grid terminal voltage are simultaneously with signal intensity, and along with signal intensity, grid end electric capacity is always constant, thus eliminate gate capacitance and change the distorted signals caused.
Based on the structure that this circuit realizes, its advantage is:
(1) by reasonably selecting size and the supply power voltage of PMOS device, the non-linear of nmos device gate capacitance is compensated;
(2) amplifying path input capacitance after compensating is constant, improves the non-linear of circuit;
(3) compare other pre-distortion technologies, structure is simple, successful.
Accompanying drawing explanation
Fig. 1 is nmos device grid terminal type non-linear capacitor compensating circuit
Embodiment
The embodiment of Fig. 1 graphic extension circuit is as follows:
Wherein, NMOS tube M1, resistance R1, inductance L 1 and electric capacity C1, C2 form power amplification circuit 110.The inner annexation of power amplification circuit 110 is: one end of C1 inputs as signal, and one end connects the grid of M1 in addition; Resistance R1 one end is as the input of M1 bias voltage Vg, and the other end connects M1 grid; Inductance one end connects the power vd D1 of power amplifier, and the other end connects the drain electrode of M1; The source ground of NMOS tube M1; Electric capacity C2 one end connects the drain electrode of M1, and the other end is then connected to match circuit 120 as output.
Match circuit 120 is made up of transmission line, electric capacity, inductance or resistance, mainly plays impedance transformation.The output of match circuit 120 connects equivalent load Rload, and equivalent load material object can be antenna etc.
PMOS M2, resistance R2 and electric capacity C3 form compensating circuit 130.The source electrode of PMOS, drain electrode short circuit, and be connected respectively to one end of resistance R2 and electric capacity C3; The resistance R2 other end connects the power vd D2 of compensating circuit; The other end then ground connection or certain fixed level of electric capacity C3.
The annexation of power amplification circuit 110, match circuit 120 and compensating circuit 130 is: the grid of the NMOS tube M1 of power power amplification circuit 110 is connected with compensating circuit 130 grid; The output of power amplification circuit 110 i.e. one end of C2 are connected to match circuit 120.
Power amplifier amplifier tube M1 (NMOS) is in signal and amplifies in path, with power supply circuits R1, L1 and block isolating circuit C1, C2; M2 (PMOS) is connected in parallel on M1 device gate end as compensating circuit, and M2 device is with biasing circuit R2 and decoupling circuit C3.According to size and the operating state of amplifier tube M1 pipe, M2 device and drain-source bias voltage is chosen by suitable, make viewed from input, to enter circuit direction electric capacity with grid voltage change close to constant, thus reduce to change by gate capacitance the distorted signals caused, improve the linearity of circuit.In figure, R1, R2, L1 represent the power supply circuits of M1 and M2.
If adopt PMOS device as power amplifier tube, the mode of NMOS in parallel can be adopted equally to carry out capacitance compensation.
The optimized circuit of the above this patent implements structure, and all equalizations done according to the application's the scope of the claims change and modify, and all should belong to the covering scope of this patent.
Claims (6)
1. for a circuit for power amplifier linearization, be applied in power amplifier, it is characterized in that the grid terminal type non-linear electric capacity by pmos compensation NMOS tube, circuit comprises power amplification circuit, match circuit and compensating circuit, wherein:
Power amplification circuit is made up of NMOS tube M1, resistance R1, inductance L 1 and electric capacity C1, electric capacity C2;
Compensating circuit is made up of PMOS M2, resistance R2 and electric capacity C3;
Match circuit is made up of transmission line, electric capacity, inductance or resistance, mainly plays impedance transformation;
The NMOS tube M1 grid of power amplification circuit is connected with the PMOS M2 grid of compensating circuit; The output of power amplification circuit i.e. one end of electric capacity C2 are connected to match circuit.
2. circuit as claimed in claim 1, it is characterized in that when circuit input end has signal to input, with signal intensity while of NMOS tube and gate pmos terminal voltage, along with signal intensity, grid end electric capacity is always constant, thus eliminates gate capacitance and change the distorted signals caused.
3. circuit as claimed in claim 1, is characterized in that the source electrode of compensating circuit PMOS M2, drain electrode short circuit, and is connected respectively to one end of resistance R2 and electric capacity C3; The resistance R2 other end connects the power vd D2 of compensating circuit, the other end then ground connection or the fixed level of electric capacity C3.
4. circuit as claimed in claim 1, is characterized in that one end of power amplification circuit electric capacity C1 inputs as signal, and one end connects the grid of NMOS tube M1 in addition; Resistance R1 one end is as the input of M1 bias voltage Vg, and the other end connects NMOS tube M1 grid; Inductance L 1 one end connects the power vd D1 of power amplification circuit, and the other end connects the drain electrode of M1; The source ground of NMOS tube M1; Electric capacity C2 one end connects the drain electrode of M1, and the other end is then connected to match circuit as output.
5. circuit as claimed in claim 1, it is characterized in that the output of match circuit connects equivalent load Rload, equivalent load Rload material object can be antenna.
6. circuit as claimed in claim 1, is characterized in that if adopt PMOS as the power amplifier tube in power amplification circuit, and the mode of the gate pmos end in parallel of the NMOS tube in compensating circuit can be adopted equally to carry out capacitance compensation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410427087.0A CN104362988A (en) | 2014-08-27 | 2014-08-27 | Circuit for linearization of power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410427087.0A CN104362988A (en) | 2014-08-27 | 2014-08-27 | Circuit for linearization of power amplifier |
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| CN104362988A true CN104362988A (en) | 2015-02-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410427087.0A Pending CN104362988A (en) | 2014-08-27 | 2014-08-27 | Circuit for linearization of power amplifier |
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| CN (1) | CN104362988A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899271A (en) * | 2017-01-10 | 2017-06-27 | 锐迪科微电子（上海）有限公司 | A kind of complementary power amplifier |
| CN106961254A (en) * | 2016-01-08 | 2017-07-18 | 康希通信科技（上海）有限公司 | High linearity radio-frequency power amplifier |
| CN106961253A (en) * | 2016-01-08 | 2017-07-18 | 康希通信科技（上海）有限公司 | High linearity radio-frequency power amplifier |
| CN108322193A (en) * | 2017-01-16 | 2018-07-24 | 天津大学（青岛）海洋工程研究院有限公司 | A kind of power amplifier of high linearity high-output power |
| CN110719077A (en) * | 2019-10-23 | 2020-01-21 | 广州慧智微电子有限公司 | Power amplifier and electronic equipment |
| CN110736872A (en) * | 2019-10-31 | 2020-01-31 | 北京无线电测量研究所 | kinds of power detection circuit and power detector |
| WO2021120728A1 (en) * | 2019-12-19 | 2021-06-24 | 广州慧智微电子有限公司 | Gain compression compensation circuit of radio frequency power amplifier |
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| US20030193371A1 (en) * | 2002-04-12 | 2003-10-16 | Larry Larson | CMOS class AB power amplifier with cancellation of nonlinearity due to change in gate capacitance of a NMOS input transistor with switching |
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| CN102474227A (en) * | 2009-08-14 | 2012-05-23 | 高通股份有限公司 | Amplifier with variable matching circuit to improve linearity |
| CN103684268A (en) * | 2012-09-18 | 2014-03-26 | 北京中电华大电子设计有限责任公司 | Low power consumption and high linearity gain controllable active orthogonal frequency mixer |
| CN103916084A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | Gain adjustable low noise amplifier circuit |
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| CN102474227A (en) * | 2009-08-14 | 2012-05-23 | 高通股份有限公司 | Amplifier with variable matching circuit to improve linearity |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106961254A (en) * | 2016-01-08 | 2017-07-18 | 康希通信科技（上海）有限公司 | High linearity radio-frequency power amplifier |
| CN106961253A (en) * | 2016-01-08 | 2017-07-18 | 康希通信科技（上海）有限公司 | High linearity radio-frequency power amplifier |
| CN106899271A (en) * | 2017-01-10 | 2017-06-27 | 锐迪科微电子（上海）有限公司 | A kind of complementary power amplifier |
| CN106899271B (en) * | 2017-01-10 | 2020-03-31 | 锐迪科微电子（上海）有限公司 | Complementary power amplifier |
| CN108322193A (en) * | 2017-01-16 | 2018-07-24 | 天津大学（青岛）海洋工程研究院有限公司 | A kind of power amplifier of high linearity high-output power |
| CN110719077A (en) * | 2019-10-23 | 2020-01-21 | 广州慧智微电子有限公司 | Power amplifier and electronic equipment |
| WO2021077594A1 (en) * | 2019-10-23 | 2021-04-29 | 广州慧智微电子有限公司 | Power amplifier and electronic device |
| CN110719077B (en) * | 2019-10-23 | 2022-08-16 | 广州慧智微电子股份有限公司 | Power amplifier and electronic equipment |
| CN110736872A (en) * | 2019-10-31 | 2020-01-31 | 北京无线电测量研究所 | kinds of power detection circuit and power detector |
| CN110736872B (en) * | 2019-10-31 | 2021-09-10 | 北京无线电测量研究所 | Power detection circuit and power detector |
| WO2021120728A1 (en) * | 2019-12-19 | 2021-06-24 | 广州慧智微电子有限公司 | Gain compression compensation circuit of radio frequency power amplifier |
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Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Applicant after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Applicant before: Beijing CEC Huada Electronic Design Co., Ltd. |
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Application publication date: 20150218 |
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