CN104362163B - The pixel structure and its manufacture method of CMOS - Google Patents
The pixel structure and its manufacture method of CMOS Download PDFInfo
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- CN104362163B CN104362163B CN201410635650.3A CN201410635650A CN104362163B CN 104362163 B CN104362163 B CN 104362163B CN 201410635650 A CN201410635650 A CN 201410635650A CN 104362163 B CN104362163 B CN 104362163B
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Abstract
The invention discloses a kind of pixel structure of CMOS and its manufacture method, the pixel structure is located on reading circuit or process circuit, the film layer that multilayer p-type, n type material make homogeneity adulterate by the contact structures of heavy doping links together, thick depletion layer can be formed using small voltage, beneficial to light absorbs；On the other hand, many PN junction structures are made to have irregular surface topography using metal dummy pattern, so as to expand the area of light absorbs；Meanwhile, adding thin metallic reflector can reflex to the light of transmission in pixel absorbed layer, further lift light absorbs.Using the pixel structure of the present invention, the optical sensitivity and definition of whole CMOS can be improved, the Performance And Reliability of chip is improved.
Description
Technical field
The present invention relates to the pixel knot of the manufacturing technology field of semiconductor devices, more particularly to a kind of CMOS
Structure and its manufacture method.
Background technology
CMOS due to its it is compatible with CMOS technology the characteristics of, so as to be rapidly developed.Relative to CCD works
Skill, its technique is completely compatible with CMOS technology, and it by being produced on silicon substrate together by photodiode and CMOS process circuits
On, cost is considerably reduced on the basis of performance is ensured, while integrated level can be increased substantially, manufacture pixel is higher
Product.
Conventional CMOS image sensor uses the method that front lighting shines, by photodiode and CMOS process circuits structure one
Rise to make and realized on a silicon substrate using same level, and chip interconnection is then manufactured on CMOS process circuit structures, it is photosensitive
Pass through the arrangement without being interconnected line on diode for light；So whole wiring density is all concentrated at CMOS
Circuit structure part is managed, and photodiode accounts for silicon area and is greater than CMOS process circuit structures, so needs higher cloth
Line level realizes function, but higher wiring level can cause the loss of light, cause the decline of performance；In addition, CMOS works
Make voltage all than relatively low, how in the case where keeping low voltage condition increase depletion layer volume be improve one of image sensor it is important
Problem；In the recent period it has been proposed that using backlight illuminated technology, silicon chip back side is thinned, light is set to be irradiated to by silicon chip back side photosensitive
On diode, so that improving performance, but whole technique is extremely complex, brings very high process complexity and cost.
Publication No. CN102226996A Chinese patent application provides a kind of CMOS and its manufacturer
Method, the image sensor arranges CMOS process circuit structures on substrate, and is arranged in CMOS process circuit structures
Pass through photodiode PN junction formed by the first conduction type amorphous silicon material and the contact of the second conduction type amorphous silicon material.
However, it is similar with above-mentioned application it is all in the prior art, the pixel region of CMOS generally only makes
With a PN junction, thus its depletion width, thickness are relatively small, if widened depletion width, thickness by high voltage,
The problems such as so high voltage can bring power consumption, technique etc. again.
How the pixel structure and its manufacture method of a kind of CMOS are provided, under small voltage just can be formed compared with
Thick depletion layer, to improve light absorbs, so as to improve device performance, be those skilled in the art's technical problem urgently to be resolved hurrily it
One.
The content of the invention
It is an object of the invention to make up above-mentioned the deficiencies in the prior art, there is provided a kind of pixel knot of CMOS
Structure and its manufacture method, can just produce thick depletion layer under small voltage, beneficial to light absorbs, improve device performance.
To achieve the above object, the present invention provides a kind of pixel structure of CMOS, and it is made in reading electricity
On the top layer of road or process circuit, the top layer of the reading circuit or process circuit includes each of dielectric layer and dielectric layer both sides
One through hole, the pixel structure includes：
Metallic reflector, on the dielectric layer；
Metal dummy pattern, on the metallic reflector；
Metal connects figure, including the N-type metal connection figure and p-type metal that are located at respectively on two through holes connect
Map interlinking shape；
Multilayer PN junction structure, by P-type material and n type material staggered floor be superimposed on the metallic reflector, metal dummy pattern and
On metal connection figure；
Contact structures, including positioned at N-type metal connect figure on longitudinal N-type contact structures and positioned at p-type metal
Longitudinal p-type contact structures on figure are connected, to cause every layer of n type material to be connected by N-type contact structures with N-type metal
Figure is electrically connected, and every layer of P-type material is connected figure with p-type metal by p-type contact structures and electrically connected.
Further, the metal dummy pattern forms at least one raised, described multilayer PN junction knot on metallic reflector
It is raised that each layer of P-type material and n type material in structure also form at least one in corresponding position.
Further, the ion doping concentration of the contact structures is higher than the ion doping concentration of multilayer PN junction structure.
Further, metallic reflector and the metal dummy pattern is not connected figure with metal and is in contact, the multilayer
P-type material is not connected that figure is in contact, n type material is not connected figure with p-type metal and is in contact with N-type metal in PN junction structure.
Wherein, the bottom in the multilayer PN junction structure is P-type material or n type material.
Further, the metallic reflector, metal dummy pattern and metal connection figure be selected from Al, Ti, TiN, Ta, TaN,
Co or Cu.
The present invention also provides a kind of manufacture method of the pixel structure of CMOS, and the pixel structure is made in
On the top layer of reading circuit or process circuit, the top layer of the reading circuit or process circuit includes dielectric layer and dielectric layer two
The through hole on side, the manufacture method comprises the following steps：
Step S01, the first metal layer is deposited on the reading circuit or process circuit topsheet surface, and graphically, with
Formation be connected figure and p-type metal with the N-type metal that two through holes are in contact and connects figure and positioned at being given an account of respectively
Metal dummy pattern on matter layer；
Step S02, depositing second metal layer, to form the metallic reflector on the dielectric layer, and it is anti-to remove metal
The metal level penetrated between layer and N-type, p-type metal connection figure, to form the isolation between metal；
Step S03, deposited n-type material, and the n type material on the p-type metal connection figure is removed, so that n type material
Figure is not connected with p-type metal to be in contact；Or deposition P-type material, and remove the P-type material on N-type metal connection figure,
It is in contact so that P-type material is not connected figure with N-type metal；
Step S04, is sequentially depositing P-type material or n type material, to form the multilayer of n type material and the superposition of P-type material staggered floor
PN junction structure, and at the multilayer PN junction structure that the N-type metal connects above figure and p-type metal connection figure, difference shape
Into the N-type contact structures and p-type contact structures of longitudinal direction, to cause every layer of n type material to connect by N-type contact structures and N-type metal
Map interlinking shape is electrically connected, and every layer of P-type material is connected figure with p-type metal by p-type contact structures and electrically connected.
Further, step S03 and S04 is using the CVD deposition deposit polycrystalline silicon of doping in situ or the p-type of non-crystalline silicon
Material and n type material.
Further, step S03 and S04 also include using laser annealing or microwave annealing make P-type material and n type material it
Between form the PN junction structure of polycrystalline or monocrystalline.
Further, step S04 is included in after multilayer PN junction structure formed, and passes through ion implanting or diffusion technique distinguishes shape
Into p-type contact structures and N-type contact structures；Or step S04 is included in after each layer of n type material or P-type material deposition, just passes through
Ion implanting or diffusion technique form the N-type contact structures or p-type contact structures of this layer, wherein, the N-type contact structures and P
The ion doping concentration of type contact structures is higher than the ion doping concentration of multilayer PN junction structure.
Further, metal dummy pattern is formed on metallic reflector at least one projection, step S04 in step S02
It is raised that each layer of P-type material and n type material in the multilayer PN junction structure of formation also form at least one in corresponding position.
Further, the second metal layer is thinner than the first metal layer, and the second metal layer thickness is
The first metal layer thickness isThe first metal layer and second metal layer be selected from Al, Ti, TiN, Ta,
TaN, Co or Cu.
The pixel structure and its manufacture method for the CMOS that the present invention is provided, the pixel structure, which is located at, to be read
On circuit or process circuit, the film layer that multilayer p-type, n type material make homogeneity adulterate by the contact structures of heavy doping is connected to
Together, thick depletion layer can be formed using small voltage, beneficial to light absorbs；On the other hand, many PN junction knots are made using metal dummy pattern
Structure has irregular surface topography, so as to expand the area of light absorbs；Meanwhile, adding thin metallic reflector will can transmit
Light reflex in pixel absorbed layer, further lift light absorbs.Using the pixel structure of the present invention, whole CMOS can be improved
The optical sensitivity and definition of image sensor, improve the Performance And Reliability of chip.
Brief description of the drawings
For that can become apparent from understanding purpose, feature and advantage of the present invention, below with reference to preferable reality of the accompanying drawing to the present invention
Example is applied to be described in detail, wherein：
Fig. 1 is the diagrammatic cross-section of the pixel structure of CMOS of the present invention；
Fig. 2 is the manufacture method flow chart of the pixel structure of CMOS of the present invention.
Embodiment
Referring to Fig. 1, the pixel structure of the CMOS of the present embodiment, it is made in the top layer of reading circuit 1
On, the top layer of reading circuit 1 includes dielectric layer 12 and each through hole 11 on the both sides of dielectric layer 12, and this pixel structure includes：
Metallic reflector 21, on dielectric layer 12；
Metal dummy pattern 22, on metallic reflector 21；
Metal connects figure, including is located at N-type metal connection figure 231 and p-type metal on two through holes 11 respectively
Connect figure 232；
Multilayer PN junction structure, metallic reflector 21, metal dummy pattern are superimposed on by P-type material 25 and the staggered floor of n type material 24
22 and metal connection figure on；
Contact structures, including positioned at N-type metal connect figure 231 on longitudinal N-type contact structures 26 and positioned at p-type
Longitudinal p-type contact structures 27 on metal connection figure 232, to cause every layer of n type material 24 to pass through N-type contact structures 26
Figure 231 is connected with N-type metal to electrically connect, and every layer of P-type material 25 is connected figure by p-type contact structures 27 with p-type metal
232 electrical connections.
In the present embodiment, the film layer that multilayer P-type material and n type material make homogeneity adulterate by the contact structures at two ends is connected
Together, the thickness of depletion layer is added, the absorption of thick depletion layer, more conducively light can be formed under small voltage；Metal vacation figure
Shape forms two projections on metallic reflector so that each layer of P-type material and n type material also formed in corresponding position two it is convex
Rise so that many PN junction structures have irregular surface topography, so as to expand the area of light absorbs；Metallic reflector then may be used
So that the light of transmission is reflexed in pixel absorbed layer, light absorbs are further lifted.
In the present embodiment, N-type contact structures and p-type contact structures are heavy doping, and its ion doping concentration is higher than PN junction knot
The ion doping concentration of n type material and P-type material in structure, to realize that low resistance is connected.Meanwhile, the ion doping in PN junction structure
Concentration should be more relatively low than contact structures, and depletion width can be made to become big, be conducive to light absorbs, but concentration also should not mistake
It is low, it is too low to cause high resistance and bring dead resistance.
In the present embodiment, metallic reflector 21 and metal dummy pattern 22 are not connected figure with the metal on both sides and are in contact,
P-type material 25 is not connected that figure 231 is in contact, n type material 24 is not connected with p-type metal with N-type metal in multilayer PN junction structure
Figure 232 is in contact.
In practical application, the bottom in multilayer PN junction structure is P-type material or n type material；Metallic reflector, metal are false
Figure and metal connection figure can be selected from Al, Ti, TiN, Ta, TaN, Co or Cu.
Please then simultaneously refering to Fig. 2, by taking the pixel structure of above-mentioned CMOS as an example, the manufacturer of the present embodiment
Method comprises the following steps：
Step S01, is previously-completed the FEOL (preceding road) and BEOL (rear road) process of CMOS reading circuits 1, in reading circuit 1
A layer thickness is deposited in topsheet surface isThe first metal layer, and graphically, with formed respectively with two phases of through hole 11
The N-type metal connection figure 231 and p-type metal connection figure 232 and the metal dummy pattern on dielectric layer 12 of contact
22。
Step S02, depositing a layer thickness isSecond metal layer, to form the metallic reflection on dielectric layer 12
Layer 21, and remove the metal level between metallic reflector 21 and N-type, p-type metal connection figure 231,232, with formed metal it
Between isolation.Wherein, the metal layer thickness of this step deposition is thinner than previous step, and the metallic reflector of generation is in order to which light is anti-
Penetrate, it is too thick that silicon chip surface graphic limit region step can be caused too high, it is unfavorable for subsequent technique.
Step S03, using the CVD deposition deposited n-type material 24 of original position doping, and removes p-type metal connection figure
N type material on 232, is in contact so that n type material 24 is not connected figure 232 with p-type metal.Wherein, the n type material 24 of formation
Surface also has concavo-convex pattern with metal dummy pattern.
Step S04, is sequentially depositing P-type material and n type material, to form N-type material using the CVD deposition of original position doping
The multilayer PN junction structure that material and P-type material staggered floor are superimposed, and connected in N-type metal above figure and p-type metal connection figure
At multilayer PN junction structure, longitudinal N-type contact structures and p-type contact structures are formed respectively, to cause every layer of n type material to pass through N
Type contact structures are connected figure electrical connection with N-type metal, and every layer of P-type material passes through p-type contact structures and p-type metal connection figure
Shape is electrically connected.
In this step, it is preferable that after the completion of multilayer P-type material and n type material deposition, then using laser annealing or microwave
Annealing makes the PN junction structure that polycrystalline or monocrystalline are formed between P-type material and n type material.
In this step, N-type contact structures and p-type contact structures can have following two forming methods, and be with second
It is good：
A. after multilayer PN junction structure is formed, p-type contact structures and N-type are formed by ion implanting or diffusion technique respectively
Contact structures；
B. after each layer of n type material or P-type material deposition, the N of this layer is just formed by ion implanting or diffusion technique
Type contact structures or p-type contact structures.
Wherein, in the present invention n type material, P-type material, N-type contact structures, p-type contact structures are normal using this area
The ion doping concentration of element doping, such as B, P, As, N-type contact structures and p-type contact structures is higher than n type material and P
The ion doping concentration of section bar material.N type material, the P-type material of formation can be polysilicon or non-crystalline silicon.
Claims (10)
1. a kind of pixel structure of CMOS, it is made on the top layer of reading circuit or process circuit, described
The top layer of reading circuit or process circuit includes dielectric layer and each through hole on dielectric layer both sides, and the pixel structure includes：
Metallic reflector, on the dielectric layer；
Metal dummy pattern, on the metallic reflector；
Metal connects figure, including is located at N-type metal connection figure and p-type metal connection figure on two through holes respectively
Shape；
Multilayer PN junction structure, the metallic reflector, metal dummy pattern and metal are superimposed on by P-type material and n type material staggered floor
Connect on figure；
Contact structures, including positioned at N-type metal connect figure on longitudinal N-type contact structures and positioned at p-type metal connection
Longitudinal p-type contact structures on figure, to cause every layer of n type material to be connected figure with N-type metal by N-type contact structures
Electrical connection, and every layer of P-type material is connected figure with p-type metal by p-type contact structures and electrically connected.
2. the pixel structure of CMOS according to claim 1, it is characterised in that：The metal dummy pattern exists
At least one is formed on metallic reflector raised, each layer of P-type material and n type material in the multilayer PN junction structure are in correspondence
It is raised that place also forms at least one.
3. the pixel structure of CMOS according to claim 1, it is characterised in that：The contact structures from
Sub- doping concentration is higher than the ion doping concentration of multilayer PN junction structure.
4. the pixel structure of CMOS according to claim 3, it is characterised in that：The metallic reflector and
Metal dummy pattern is not connected figure with metal and is in contact, in the multilayer PN junction structure P-type material not with N-type metal connection figure
Shape is in contact, n type material is not connected figure with p-type metal and is in contact.
5. a kind of manufacture method of the pixel structure of CMOS, the pixel structure is made in reading circuit or processing
On the top layer of circuit, the top layer of the reading circuit or process circuit includes dielectric layer and each one of dielectric layer both sides leads to
Hole, it is characterised in that the manufacture method comprises the following steps：
Step S01, the first metal layer is deposited on the reading circuit or process circuit topsheet surface, and graphically, to be formed
Figure and p-type metal connection figure are connected with the N-type metal that two through holes are in contact respectively and positioned at the dielectric layer
On metal dummy pattern；
Step S02, depositing second metal layer to form the metallic reflector on the dielectric layer, and removes metallic reflector
The metal level between figure is connected with N-type, p-type metal, to form the isolation between metal；
Step S03, deposited n-type material, and remove the n type material on p-type metal connection figure so that n type material not with P
Type metal connection figure is in contact；Or deposition P-type material, and the P-type material on the N-type metal connection figure is removed, so that P
Section bar material is not connected figure with N-type metal and is in contact；
Step S04, is sequentially depositing P-type material or n type material, to form the multilayer PN junction of n type material and the superposition of P-type material staggered floor
Structure, and at the multilayer PN junction structure that the N-type metal connects above figure and p-type metal connection figure, formed respectively vertical
To N-type contact structures and p-type contact structures, to cause every layer of n type material to pass through N-type contact structures and N-type metal connection figure
Shape is electrically connected, and every layer of P-type material is connected figure with p-type metal by p-type contact structures and electrically connected.
6. the manufacture method of the pixel structure of CMOS according to claim 5, it is characterised in that：Step
S03 and S04 is using the CVD deposition deposit polycrystalline silicon of doping in situ or the P-type material and n type material of non-crystalline silicon.
7. the manufacture method of the pixel structure of CMOS according to claim 6, it is characterised in that：Step
S03 and S04 also include making the PN of formation polycrystalline or monocrystalline between P-type material and n type material using laser annealing or microwave annealing
Junction structure.
8. the manufacture method of the pixel structure of CMOS according to claim 5, it is characterised in that：Step
S04 is included in after multilayer PN junction structure formed, and forms p-type contact structures respectively by ion implanting or diffusion technique and N-type connects
Touch structure；Or step S04 is included in after each layer of n type material or P-type material deposition, just passes through ion implanting or diffusion technique shape
Into the N-type contact structures or p-type contact structures of this layer, wherein, the ion doping of the N-type contact structures and p-type contact structures
Concentration is higher than the ion doping concentration of multilayer PN junction structure.
9. the manufacture method of the pixel structure of the CMOS according to any one of claim 5 to 8, its feature exists
In：Metal dummy pattern forms at least one raised, multilayer PN junction formed in step S04 on metallic reflector in step S02
It is raised that each layer of P-type material and n type material in structure also form at least one in corresponding position.
10. the manufacture method of the pixel structure of the CMOS according to any one of claim 5 to 8, its feature
It is：The second metal layer is thinner than the first metal layer, and the second metal layer thickness isFirst metal
Thickness degree isThe first metal layer and second metal layer are selected from Al, Ti, TiN, Ta, TaN, Co or Cu.
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| CN201410635650.3A CN104362163B (en) | 2014-11-12 | 2014-11-12 | The pixel structure and its manufacture method of CMOS |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024755A (en) * | 2009-09-18 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Cmos image sensor and forming method thereof |
| CN102664185A (en) * | 2012-06-01 | 2012-09-12 | 上海中科高等研究院 | CMOS (Complementary Metal Oxide Semiconductor) image sensor and production method thereof |
| CN103151365A (en) * | 2013-03-28 | 2013-06-12 | 北京思比科微电子技术股份有限公司 | Complementary metal oxide semiconductor (CMOS) image sensor and manufacturing method thereof |
| CN103311260A (en) * | 2013-06-08 | 2013-09-18 | 上海集成电路研发中心有限公司 | CMOS (complementary metal oxide semiconductor) image sensor, pixel unit of CMOS image sensor, and production method of pixel unit |
-
2014
- 2014-11-12 CN CN201410635650.3A patent/CN104362163B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024755A (en) * | 2009-09-18 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Cmos image sensor and forming method thereof |
| CN102664185A (en) * | 2012-06-01 | 2012-09-12 | 上海中科高等研究院 | CMOS (Complementary Metal Oxide Semiconductor) image sensor and production method thereof |
| CN103151365A (en) * | 2013-03-28 | 2013-06-12 | 北京思比科微电子技术股份有限公司 | Complementary metal oxide semiconductor (CMOS) image sensor and manufacturing method thereof |
| CN103311260A (en) * | 2013-06-08 | 2013-09-18 | 上海集成电路研发中心有限公司 | CMOS (complementary metal oxide semiconductor) image sensor, pixel unit of CMOS image sensor, and production method of pixel unit |
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