CN104361155B - Relay protection fault analysis method based on vector graphics and analytical equipment - Google Patents
Relay protection fault analysis method based on vector graphics and analytical equipment Download PDFInfo
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Abstract
A kind of relay protection fault analysis method and analytical equipment based on vector graphics, this method comprises the following steps:Recorded wave file and the corresponding standard logic map of such recorded wave file are called from protective relaying device；The recorder data of the recorded wave file is read, and recording oscillogram is shown according to the recorder data；The corresponding standard logic map of such recorded wave file is loaded, and shows the standard logic map of the load；The standard logic map is deduced according to the recorder data of waveform record dynamic, obtains the deduction result comprising logical time delay pel and line chart member of returning；When the deduction result is consistent with the recorder data of the recorded wave file, the deduction result is shown on the display screen.The dynamic with logical time delay pel and line chart member of returning, which can be formed, using the present invention deduces logic chart.
Description
Technical field
The present invention relates to a kind of smart electric grid system failure analysis techniques, especially a kind of to be based on vector graphics (such as CIM/G
Figure) relay protection fault analysis method and analytical equipment.
Background technology
Relay protection fault analysis acts correct dependent on fault oscillograph or device analysis protective relaying device
Property.Generally, for host equipment break down, protective relaying device protection act abnormal behavior even tripping when, operation
Personnel more wonder logic behavior and abnormal behaviour reason inside protective relaying device.And the relay that producer provides at present
The miscellaneous function of protective device makes it difficult for operations staff to be completely independent the abnormal behaviour reason for analyzing protective relaying device.
For the above situation, the also perfect recording function of part protective relaying device manufacturer increases key logic
The flag information of contact simplifies the difficulty of accident analysis, but there are still following some problems：
(1) the logic chart format standard disunity of relay protection fault analysis, each producer are reached using respective logical diagram
Mode, so as to cause current diagnostic tool disunity, cannot across producer analysis, lack versatility；
(2) the delay mark in logic chart cannot be indicated；
(3) line that returns in logic chart cannot be indicated；
(4) complex fault analysis relies on protective relaying device producer, and protection process analysis procedure analysis lacks the transparency；
(5) the logic chart version of relay protection fault analysis often changes, the logic charts of different editions and recorded wave file without
Method is compatible with；
(6) logic chart of relay protection fault analysis can not obtain online.
Invention content
In view of the foregoing, the present invention proposes a kind of relay protection fault analysis method based on vector graphics and analysis dress
It sets, the elements such as association, logical relation, delay outlet, connecting line is inputted by standardized definition, standardized relay is formed and protects
Protect the logic relation picture of accident analysis, and the recorded wave file of matching standard, by waveform crucial digital quantity channel with patrol
Collect the association of figure channel.
The relay protection fault analysis method based on vector graphics includes：
Data call step, and recorded wave file and such record are called from the protective relaying device communicated to connect with analytical equipment
The corresponding standard logic map of wave file, the standard logic map are vector graphics；
Graphical display step 1 reads the recorder data of the recorded wave file, and shows recording according to the recorder data
Oscillogram is on the display screen of the analytical equipment；
Graphical display step 2 loads the corresponding standard logic map of such recorded wave file, and shows that the standard of the load is patrolled
Collect figure on the display screen, the standard logic map includes：Logical channel pel, logic gate pel, logical time delay pel,
And connecting line pel；
Figure deduces step 1, is deduced on the display screen according to the recorder data of waveform record dynamic
The standard logic map of display obtains deduction result, and the standard logic map that the dynamic is deduced includes logical time delay pel, described to patrol
It collects delay pel record and shows the delay time of logic export；
Figure deduces step 2, and the deduction result is compared with the recorder data of the recorded wave file；And
Figure is deduced step 3 and is pushed away described when the deduction result is consistent with the recorder data of the recorded wave file
Result is drilled to show on the display screen；When the recorder data of the deduction result and the recorded wave file is inconsistent, then export
In miscue to the display screen.
The analytical equipment includes：
Data call module, for from protective relaying device communicate to connect with the analytical equipment calling recorded wave file and
The corresponding standard logic map of such recorded wave file, the standard logic map are vector graphics；
Image display module, the recorder data for reading the recorded wave file, and shown and recorded according to the recorder data
On the display screen of the analytical equipment, the standard logic map includes wave oscillogram：Logical channel pel, logic gate figure
Member, logical time delay pel and connecting line pel；
The image display module is additionally operable to load the corresponding standard logic map of such recorded wave file, and shows the load
Standard logic map on the display screen；
Graphics deduction module, for deducing the display screen according to the recorder data dynamic of the waveform record
The standard logic map of upper display obtains deduction result, and the standard logic map that the dynamic is deduced includes logical time delay pel, described
Logical time delay pel records and shows the delay time of logic export；
The graphics deduction module is additionally operable to compare the recorder data of the deduction result and the recorded wave file
It is right；And
The graphics deduction module is additionally operable to when the deduction result is consistent with the recorder data of the recorded wave file,
The deduction result is shown on the display screen；When the recorder data of the deduction result and the recorded wave file is inconsistent
When, then output error is prompted to the display screen.
Compared to the prior art, relay protection fault analysis method and analysis dress of the present invention based on vector graphics
It sets, the elements such as association, logical relation, delay outlet, connecting line is inputted by standardized definition, standardized relay is formed and protects
Protect the logic relation picture of accident analysis, and the recorded wave file of matching standard, by waveform crucial digital quantity channel with patrol
The association of figure channel is collected, to reappear protection act flow, clearly solves existing logic chart format standard disunity, relay protection event
Hinder the opaque problem of analysis tool disunity, protection process, initiates and solve electric relay protection logic chart delay mark and return
Also line problem.In conjunction with the logic chart naming method definition of relay protection fault analysis, file network communications, to solve to patrol
Collect figure edition compatibility and online the problem of obtaining.
Description of the drawings
Fig. 1 is the applied environment figure of the relay protection fault analysis system the present invention is based on vector graphics；
Fig. 2 is the functional block diagram of the relay protection fault analysis system the present invention is based on vector graphics；
Fig. 3 is the logic chart composite structural diagram of the relay protection fault analysis of the present invention；
Fig. 4 is that the logic chart of the relay protection fault analysis of the present invention defines exemplary plot；
Fig. 5 is the overall flow figure of the relay protection fault analysis method the present invention is based on vector graphics；
Fig. 6 is the logic chart visioning procedure figure of the present invention；
Fig. 7 is that the logic chart of the present invention deduces flow chart.
Specific implementation mode
As shown in Figure 1, being the applied environment figure of the relay protection fault analysis system the present invention is based on vector graphics.At this
In embodiment, the 26 (hereinafter also referred to as " relay protection fault of relay protection fault analysis system based on vector graphics
Analysis system 26 ") it is applied in analytical equipment 2, which can carry display screen 20 and input equipment 22, for example,
The analytical equipment 2 can be computer.The display screen 20 can be LCD (Liquid Crystal Display) display screen,
The input equipment 22 can be the input units such as keyboard.The analytical equipment 2 further includes being connected by data line or signal wire
Memory 24 and processor 28.It should be noted that Fig. 1 is the signal to analytical equipment 2 software configuration and hardware configuration
Property explanation, analytical equipment 2 further includes other necessary electronic components and system software, and this is no longer going to repeat them.
The relay protection fault analysis system 26 is stored in the memory 24 of analytical equipment 2, is used for from relay protection
Standard logic map, the recorded wave file of matching standard, by digital quantity channel crucial in recording oscillogram and mark are read in device 4
Recording channel association in quasi- logic chart, to reappear the protection act flow of protective relaying device 4, specific method flow is refering to figure
2 to Fig. 7 description.
In the present embodiment, the relay protection fault analysis system 26 can provide one or more modules, and described one
A or multiple modules are stored in the memory 24 of the analytical equipment 2 and are configured to by one or more processors (this
Embodiment is a processor 28) it executes, to complete the present invention.For example, as shown in fig.2, the relay protection fault is analyzed
System 26 includes data calling module 260, image display module 262, graphics deduction module 264 and figure creation module 265.This
It is to complete the computer program code segments of a specific function to invent so-called module, than program more suitable for describing software in a computer
Implementation procedure, about each module concrete function refering to Fig. 3 to Fig. 7 description.
The present invention is relay protection fault analysis system and method based on vector graphics, in the present embodiment, with
It is illustrated for CIM/G figures.
Wherein, CIM refers to common information model (Common Information Model), is used for power system resource
(Power System Resource) is described as object class, attribute and the relationship between them.In the present embodiment, G is
Refer to G language, i.e. electric system figure Description standard (Graphic Description Specification for Electric
Power System, hereinafter referred to as " G language ").
G language is for the common graphics based on SVG (Scalable Vector Graphics, scalable vector graphics)
Exchange format can not directly express the deficiencies of electric system figure and model integration, in figures of the IEC 61970-453 based on CIM
A kind of novel picture description language that shape grows up on the basis of exchanging, applied to electric system.G language is to graphically
The relevant information of power equipment and power grid is expressed, supports efficiently to access electric power graphs and model interaction data, supports not homology
The exchange of electric power graphs and model interaction data between system.G language is a kind of plain text for following XML standards based on label
Language, the basic drawing formats of compatible SVG.
As shown in figure 3, G language is made of two large divisions：Graphic definition and figure reference.Graphic definition is mainly convenient to make
User is freely combined element figure element and (referred to as " basic element ") forms self-defined pel according to demand comprising figure is aobvious
Show definition and the pel definition of attribute.Figure reference is graphic plotting, and main contents include reference and the base of self-defined pel
The use of this graphic element.G language defines primary graphic element：Point, line, circle, rectangle, text etc., self-defined pel use
Primary graphic element combines to form new pel definition.
Figure reference is the direct presentation (image is shown) of image, is passed through<xxx></xxx>(xxx is to need to quote to mode
Element term, such as<g></g>) directly quote basic element or self-defined pel in G language, you can complete image is in
It is existing, wherein self-defined pel need using field " devref " come specify the metafile name quoted and pel hereof
id.As shown in figure 3, the logic chart that the present invention defines inherits the structure of G language completely, expand logic on self-defining image meta template
Channel pel, logic gate pel, logical time delay pel, connecting line pel can completely show logic chart and good logical
With property and scalability.
As shown in figure 4, defining example for logic chart in the present invention, the pel in the logic chart includes, but are not limited to：It patrols
Collect channel pel, logic gate pel (with pel or pel, non-pel etc.), logical time delay pel and connecting line pel.
Logical channel pel defines the internal node information of protective relaying device 4, is Boolean type variable, internal node information
It is stored in the digital information of recorded wave file.
Logic gate pel defines input quantity (such as " external start failure protection open into " input quantity and " corresponding to open into normal " input
Amount) between logical relation, and export result.Logic gate pel includes and pel or pel and non-pel etc..Logic gate expression
Logical relation of each digital quantity in protective program internal operation.
Logical time delay pel defines the delay of logic export, in the present embodiment, logical time delay pel for record and
The delay time of display logic outlet.
Connecting line pel defines the connection relation between pel, and in the present embodiment, connecting line pel includes the first kind
Type connecting line (such as generic connectivity line) and Second Type connecting line (such as return line) two classes.
The logical value that line chart member of returning defines current sample time (such as or is patrolled as some logic gate of next sampling instant
Volume door) input.
In the present embodiment, the component and attribute definition of logical channel pel include mainly five aspects：Pel
ID, status number, terminal, polygon frame, text.Wherein, pel ID is used for unique mark pel, and status number indicates that pel is possessed
State, be about set to two states 0 and 1.Terminal table diagram member outputs and inputs tie point, and polygon frame and text are used for table
Show primitive shapes and content.In order to reach display image, the purpose of Dynamic Display logic chart, it is necessary to by logical channel pel with
The recording channel of recorded wave file associates, therefore agreed upon logical channel pel ID is equal to associated recording tunnel name, and patrols
It collects channel pel and corresponds to recording channel file (i.e. recording configuration file：.cfg file) the recording channel (present embodiment that defines
In be digital quantity channel).Therefore, the parsing from recording channel file (.cfg) by recording channel is needed before creating logic chart
The recording channel template of the protective relaying device 4 is out saved as, then according to the channel rendering logic in the template of recording channel
Figure, therefore the logic chart that drafting is completed all has completed channel correspondence.
Node name of the logical channel pel in G language is defined as：" LogicChannel ", different logical channels are formed
Different logical channel pels is distinguished and is associated with using " id=logical channels name ", and component includes being patrolled for showing
The polygon element of channel shape is collected, the text element of display logic tunnel name is used for, is used for the end of display channel tie point
Daughter element.Logical channel pel component and attribute are shown in Table 1:
1 logical channel pel component of table and attribute
One example of logical channel pel is as follows：
Wherein, LogicChannel is logical channel pel node name, and w indicates that pel is wide, and h indicates that pel is high, and id is indicated
The unique mark of pel, agreement uses recording tunnel name in present embodiment, for being associated with recording channel." state " is defined
Two states that pel possesses,<Layer></Layer>Indicate figure layer, all pels defined in present embodiment are in a figure layer
In.<polygon>Expression polygon,<Text>Expression text,<pin>Indicate terminal." sta " in each element indicates element
Affiliated state, " fc " indicate that Fill Color, content are rgb value, and " ts " is that text shows that content, " index " indicate terminal sequence
Number, for identifying the entire terminal defined in pel.
Node name of the logic gate pel in G language is defined as：" LogicGate ", pel component include rectangle frame,
Text etc..Pel composition attribute has essential attribute such as：Id, extended attribute have input terminal number：inputNum.Present embodiment
It is middle to distinguish Different Logic door pel using id, it can be defined as follows logic gate types：With logic gate types, id=AND；Or it patrols
Collect door type, id=OR；NOT logic door type, id=NO；NAND Logic door type, id=NAND；Or logic door type, id
=NOR；XOR logic door type, id=XOR；Same or logic gate types, id=NXOR.
In order to which that distinguishes logic gate pel outputs and inputs connection, according to logic gate pel there are two or multiple input end
The characteristics of son, leading-out terminal, agreement terminal index=0 are the output end of logic gate pel, and input terminal is then from index=1
Start to add up.Logic gate pel component and attribute are shown in Table 2:
2 logic gate pel component of table and attribute
One example of logic gate pel is as follows, wherein LogicGate indicates logic gate pel node name：
Connection medium of the connecting line pel as logic graph structure, it is believed that be the container of terminal, continue to use in G language specification
Node name " ConnectLine ".The object that connecting line first and last end is connected is logical channel pel, logic gate pel or connection
Line itself.The element that connecting line pel includes mainly in G language specification is broken line, and attribute includes record connection relation
link.For the application in adaptation logic figure, the type fields of connecting line type are indicated connecting line attribute extension, type the
One attribute value (such as 0) indicates common connecting line (first kind connecting line), and special connection is indicated for the second attribute value (such as 1)
Line-" return line " (Second Type connecting line).Further, in other embodiments, other kinds of expansion can also be supported
It fills, such as type is that third value indicates third type connecting line.
In the present embodiment, in order to distinguish the input terminal and output end of connecting line, according to connecting line, only there are one inputs
The characteristics of terminal, one or more leading-out terminal, agreement terminal index=0 are the input terminal of connecting line pel, output end then from
Index=1 starts to add up.Connecting line pel component and attribute are as shown in table 3：
3 connecting line pel component of table and attribute
One example of connecting line pel is as follows, wherein and ConnectLine indicates connecting line pel nodename,
Type is extended field, indicates that connecting line type, d indicate connecting line path：
<ConnectLine id=" 3011 " type=" 1 " ... d=" 750,160 750,210 580,210 580,
190 600,190 " link=" 0,0,2030；1,1,2001"/>
Node name of the logical time delay pel in G language is defined as：" LogicDelay ", component include Rectangular Element
Element：For display logic delay primitive shapes and region, text element：For the content of display logic delay pel, terminal
Element：For positioning pel tie point, straight line：For forming the marking pattern that is delayed.The delay of logical time delay pel tracer signal goes out
Mouthful, delay time is recorded using extended field time, unit is defaulted as ms.Logical time delay pel component and attribute are shown in Table
4:
4 logical time delay pel component of table and attribute
One example of logical time delay pel is as follows, wherein LogicDelay indicates delay pel nodename, time tables
Show that delay time, unit are millisecond (ms), delay 20ms is indicated in the example：
As shown in figure 5, being the overall flow figure of the relay protection fault analysis method the present invention is based on vector graphics.
Step S10, data call module 260 from protective relaying device 4 call (replicating Copy) recorded wave file and such
The corresponding standard logic map of recorded wave file.In the present embodiment, the standard logic map is general CIM/G picture description languages
Normal vector figure (shown in Fig. 3), about create standard logic map method refering to shown in Fig. 6.
Step S11, image display module 262 read the recorder data of the recorded wave file, and according to the recorder data
Show recording oscillogram on display screen 20.
Step S12, image display module 262 loads the corresponding standard logic map of such recorded wave file, and shows the load
Standard logic map display screen 20 on.
Step S13, graphics deduction module 264 are deduced described aobvious according to the recorder data dynamic of the waveform record
The standard logic map shown on display screen curtain 20 obtains deduction result.The deduction function of logic chart can dynamically react failure
Change procedure can also react the correctness of fault actions result, and the specific method about logic chart deduction is refering to described in Fig. 7.
Step S14, graphics deduction module 264 compare the recorder data of the deduction result and the recorded wave file
It is right, and judge whether the deduction result is consistent with the recorder data of the recorded wave file.
Step S15, if the deduction result is consistent with the recorder data of the recorded wave file, graphics deduction module
264 judgement recorder datas are correct (i.e. the result of the action of 4 recording of protective relaying device complies fully with action logic), and are pushed away described
Result is drilled to be shown on display screen 20.
Step S16, if the recorder data of the deduction result and the recorded wave file is inconsistent, graphics deduction module
264 judgement recorder data mistakes, and output error is prompted to display screen 20.
As shown in fig. 6, being the logic chart visioning procedure figure of the present invention.
Step S101, figure creation module 265 judge whether to have created the recording channel template of the recorded wave file, example
Such as, judge the recording channel template with the presence or absence of the recorded wave file in memory 24.
Step S102, if not creating the recording channel template of the recorded wave file, the selection of figure creation module 265 should
The recording channel file (i.e. recording configuration file .cfg) of recorded wave file, according to the recording channel document creation recorded wave file pair
The recording channel template answered, is then back to step S101.
Step S103, if having created the recording channel template of the recorded wave file, figure creation module 265 imports should
The recording channel template of recorded wave file, and according to the recording channel template rendering logic figure of the importing.
Step S104, it is standard logic map that figure creation module 265, which preserves the logic chart completed, such as general CIM/G
Graphical format.
As shown in fig. 7, being the logic chart deduction flow chart of the present invention.Following steps are executed by graphics deduction module 264
It completes.
Step S201, in the structured data to the memory of analytical equipment 2 for initializing the standard logic map, and using default
Type data structure stores the structured data.The structured data includes, but are not limited to the logic in the standard logic map
The logical relation of pel (such as logical channel pel) and each logic pel.In the present invention, using two kinds of data structure
Store the structured data.
In the first embodiment, the preset kind data structure be directed acyclic graph, the directed acyclic graph it is all defeated
It is the node that 0 out-degree is 1 that enter channel, which be in-degree, and logic gate node is the node that in-degree is more than that 2 out-degree are 1, as a result channel be into
Degree is the node that 1 out-degree is 0.
In a second embodiment, the preset kind data structure is tree structure, and in the tree structure, division result is logical
Outside road node, all input channels are the leaf node of tree, and logic gate node is the node with son, and root node is to export
As a result, and node is logic gate before root node, root node only has a size child node.
Step S202 obtains the recorder data of a sampled point and the sampled point in recording oscillogram, and from the sampling
The value that all recording channels at sampled point current time are obtained in the recorder data of point (is digital quantity channel in present embodiment
Value), obtain sampled value.
Step S203 changes the recording channel of the logical channel pel in the standard logic map according to the sampled value
Value, and change the color of the logical channel pel.For example, if the sampled value is 1, and patrolling in the standard logic map
The recording channel value for collecting channel pel is 0, then the recording channel value is changed to 1.
In the present embodiment, if the recording channel value of the logical channel pel is the first numerical value, described in change
The color of logical channel pel is the first color；If the recording channel value of the logical channel pel is second value, more
The color for changing the logical channel pel is the second color.For example, if the recording channel value of the logical channel pel
It is 1, then the color of the logical channel pel is changed to red, if the recording channel value of the logical channel pel is 0,
The color of the logical channel pel is then changed to grey.
Step S204, the logic of recording channel value and standard logic map after being changed according to the logical channel pel
Door calculates the value after the connecting line change of standard logic map, and changes the color of the connecting line.For example, if described patrol
It is 1 and 0 to collect the recording channel value after the change of channel pel, and the logic gate is to be with door (AND), the then value after connecting line is changed
0。
In the present embodiment, if the value of the connecting line is the first numerical value, the color for changing the connecting line is
First color；If the value of the connecting line is second value, the color for changing the connecting line is the second color.Citing and
The color of the connecting line is changed to red, if the value of the connecting line is by speech if the value of the connecting line is 1
0, then the value of the connecting line is changed to grey.
Step S205 calculates other pels in the standard logic map successively according to the connection relation of the connecting line
Value, the value until calculating the last one pel.It is described last if the preset kind data structure is directed acyclic graph
One pel is the destination node of the directed acyclic graph；It is described if the preset kind data structure is tree structure
The last one pel is the root node of the tree structure.
Step S206, by the value of the value of the last one pel recorder data corresponding with the pel, (i.e. digital quantity is logical
The value in road) it is compared, and judge whether the value of the value recorder data corresponding with the pel of the last one pel is equal.
Step S207, if the value of the value of the last one pel recorder data corresponding with the pel is unequal,
Mistake is prompted on display screen 20.
Step S208, if the value of the last one pel value of recorder data corresponding with the pel is equal,
The standard logic map restained is shown on display screen 20.
In conclusion the present invention is obstructed for relay protective scheme bitmap-format in current protective relaying device malfunction analysis procedure
With the non-type problem of storage format, it is proposed that the storage of the general relay protection logic flow file based on CIM/G figures
Format solves the problems, such as that the diagnostic tool of current generally existing lacks and standardizes, is unitized.Solve existing relay simultaneously
The indeterminable protection exit delay of relay protective scheme figure, line problem of returning.Certainly, in other embodiments, the logic chart
It may include logical time delay pel, do not include line chart member of returning, to solve protection exit latency issue, or only include the line that returns
Pel does not include logical time delay pel, to solve the problems, such as the line that returns.
The invention has the advantages that：The logic chart format standard for proposing relay protective scheme solves the failure point of different manufacturers
The compatibling problem of analysis tool realizes that the diagnostic tool of different manufacturers supports across producer analytic function, there is good versatility
And scalability；Simplify protection process analysis procedure analysis, makes protection transparent procedures；Guarantor cannot be shown by solving existing relay protection logic diagram
The problem of shield delay outlet；Solve the problems, such as that existing relay protection logic diagram cannot consider the line that returns；Solve patrolling for different editions
Collecting figure can not compatibling problem with recorded wave file；Relay protective scheme figure can online be obtained by network from protective relaying device.
The above content is combining, specific preferred embodiment is made for the present invention to be described in detail, and it cannot be said that specific real
It applies and is confined to these explanations.For person of an ordinary skill in the technical field, before not departing from present inventive concept
It puts, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to protection scope of the present invention.
Claims (10)
1. a kind of relay protection fault analysis method based on vector graphics is applied to analytical equipment, which is characterized in that this method
Including：
Data call step, and recorded wave file and such recording are called from the protective relaying device communicated to connect with the analytical equipment
The corresponding standard logic map of file, the standard logic map are vector graphics；
Graphical display step 1 reads the recorder data of the recorded wave file, and shows recording waveform according to the recorder data
Figure is on the display screen of the analytical equipment；
Graphical display step 2 loads the corresponding standard logic map of such recorded wave file, and shows the standard logic map of the load
On the display screen, the standard logic map includes logical channel pel, logic gate pel, logical time delay pel and connects
Wiring pel；
Figure deduces step, obtains the recorder data of a sampled point and the sampled point in recording oscillogram, and from the sampling
The value that all recording channels at sampled point current time are obtained in the recorder data of point changes the mark according to the sampled value
The recording channel value of logical channel pel in quasi- logic chart, and the color of the logical channel pel is changed, it is patrolled according to described
The logic gate for collecting recording channel value and standard logic map after the change of channel pel, calculates the connecting line of standard logic map more
Value after changing, and the color of the connecting line is changed, according to the connection relation of the connecting line, the standard logic is calculated successively
The value of other pels in figure, the value until calculating the last one pel, by the value of the last one pel and the pel pair
The value for the recorder data answered is compared, and judges the value of the value recorder data corresponding with the pel of the last one pel
It is whether consistent, when consistent, then the standard logic map restained is shown on the display screen；When inconsistent, then mistake is exported
Accidentally on prompt to the display screen.
2. the relay protection fault analysis method according to claim 1 based on vector graphics, it is characterised in that：
The logical channel pel defines the internal node information of protective relaying device, is Boolean type variable, the internal node
Information is stored in the digital information of recorded wave file；
The logic gate pel defines the logical relation between input quantity, and exports result, wherein logic gate indicates each number
Measure the logical relation in relay protection program internal operation；
The logical time delay pel is used to record and the delay time of display logic outlet；And
The connecting line pel defines the connection relation between pel.
3. the relay protection fault analysis method according to claim 2 based on vector graphics, which is characterized in that described to patrol
The component and attribute definition of volume channel pel include：Pel ID, status number, terminal, polygon frame, text, channel association
Field, wherein the pel ID is used for unique mark logical channel pel, and the status number indicates the state that pel is possessed,
The terminal table diagram member outputs and inputs tie point, and the polygon frame and text are used for indicating primitive shapes and content,
The channel associate field indicates being associated between the logical channel pel and the recording channel of recording channel document definition, and
The pel ID of the logical channel is equal to associated recording tunnel name.
4. the relay protection fault analysis method according to claim 2 based on vector graphics, it is characterised in that：
The component of the logic gate pel includes rectangle frame and text, and the composition attribute of the logic gate pel includes basic
Attribute pel ID and extended attribute input terminal number, wherein the pel ID is for distinguishing Different Logic door pel；And
According to logic gate pel, there are two or more input terminals, the attribute of leading-out terminal, setting terminal index=0
For the output end of logic gate pel, input terminal then adds up since index=1, to distinguish outputting and inputting for logic gate pel
Connection.
5. the relay protection fault analysis method according to claim 2 based on vector graphics, which is characterized in that described to patrol
The attribute for collecting delay pel includes the extended field for recording delay time；The component of the logical time delay pel includes：Square
Shape element, display logic be delayed the rectangular element in primitive shapes and region, the text element of display logic delay pel content,
Position the terminal element of pel tie point and the vertical element of composition delay marking pattern.
6. the relay protection fault analysis method according to claim 2 based on vector graphics, it is characterised in that：
The object that the first and last end of the connecting line pel is connected is logical channel pel, logic gate pel or connecting line pel sheet
Body, and the connecting line pel includes broken line element；And
According to connecting line there are an input terminal, the attribute of one or more leading-out terminals, terminal index=0 is set to connect
The input terminal of wiring pel, output end then add up since index=1, to distinguish the input terminal and output end of connecting line.
7. the relay protection fault analysis method according to claim 6 based on vector graphics, which is characterized in that the company
Wiring pel includes first kind connecting line and Second Type connecting line, the first kind connecting line first property value table
Show, the Second Type connecting line is indicated with the second attribute value.
8. the relay protection fault analysis method according to claim 7 based on vector graphics, which is characterized in that described
One type connecting line is generic connectivity line, and the Second Type connecting line is the line that returns, and the line definition dynamic of returning was deduced
Input of the logical value of current sample time as the logic gate of next sampling instant in journey.
9. a kind of analytical equipment, which is characterized in that the analytical equipment includes：
Data call module, for from protective relaying device communicate to connect with the analytical equipment calling recorded wave file and such
The corresponding standard logic map of recorded wave file, the standard logic map are vector graphics；
Image display module, the recorder data for reading the recorded wave file, and recording wave is shown according to the recorder data
Shape figure is on the display screen of the analytical equipment；
The image display module is additionally operable to load the corresponding standard logic map of such recorded wave file, and shows the mark of the load
On the display screen, the standard logic map includes logical channel pel, logic gate pel, logical time delay figure to quasi- logic chart
Member and connecting line pel；
Graphics deduction module, the recorder data for obtaining a sampled point and the sampled point in recording oscillogram, and from this
The value that all recording channels at the sampled point current time are obtained in the recorder data of sampled point changes institute according to the sampled value
The recording channel value of the logical channel pel in standard logic map is stated, and changes the color of the logical channel pel, according to institute
The logic gate for stating recording channel value and standard logic map after logical channel pel change, calculates the connection of standard logic map
Value after line change, and the color of the connecting line is changed, according to the connection relation of the connecting line, the standard is calculated successively
The value of other pels in logic chart, the value until calculating the last one pel, by the value of the last one pel and the figure
The value of the corresponding recorder data of member is compared, and judges the value recorder data corresponding with the pel of the last one pel
Value it is whether consistent, when consistent, then show the standard logic map restained on the display screen；It is when inconsistent, then defeated
It makes mistake on prompt to the display screen.
10. analytical equipment according to claim 9, it is characterised in that：
The logical channel pel defines the internal node information of protective relaying device, is Boolean type variable, the internal node
Information is stored in the digital information of recorded wave file；
The logic gate pel defines the logical relation between input quantity, and exports result, wherein logic gate indicates each number
Measure the logical relation in relay protection program internal operation；
The logical time delay pel is used to record and the delay time of display logic outlet；And
The connecting line pel defines the connection relation between pel.
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| CN112018736B (en) * | 2020-10-19 | 2021-03-02 | 国网江西省电力有限公司电力科学研究院 | Relay protection and control logic fault positioning method and device |
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Effective date of registration: 20190924 Address after: No. 47, Xu Dong Street, Hongshan District, Wuhan, Hubei Patentee after: State Grid Center China Grid Company Limited Address before: 430000 No. 47 Xu Dong Road, Wuchang District, Hubei, Wuhan Co-patentee before: CYG Sunri Automation Co., Ltd. Patentee before: Huazhong Electric Power Network Co., Ltd. |