CN104360668B - Control method of Ethernet controller of digital substation - Google Patents
Control method of Ethernet controller of digital substation Download PDFInfo
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- CN104360668B CN104360668B CN201410705443.0A CN201410705443A CN104360668B CN 104360668 B CN104360668 B CN 104360668B CN 201410705443 A CN201410705443 A CN 201410705443A CN 104360668 B CN104360668 B CN 104360668B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
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Abstract
The invention provides a control method of an Ethernet controller of a digital substation. According to the control method, a read-write command is generated, a virtual address is output according to the read-write command, the virtual address is sent through a first FSL data bus, the virtual address is received at an Ethernet controller end, a read-write zone bit, a register starting address and the data length are analyzed out from the virtual address, a selected register is selected according to the register starting address, and write operation is carried out on the selected register according to the data length, or read operation is carried out on the selected register through a second FSL data bus. The first FSL data bus is used for transmitting the virtual address, the register is selected according to the virtual address, the selected register is subjected to the write operation through the first FSL data bus or read operation through the second FSL data bus, the high-speed transmission characteristic of the FSL data buses can be used for achieving the purpose of address-oriented control, and the control method can meet the requirement for large-flow data transmission of the digital substation.
Description
Technical field
The application is related to technical field of electric power, more particularly, it relates to a kind of ethernet controller of digital transformer substation
Control method.
Background technology
Micorblaze is 32 RISC soft-core processors of the employing Harvard structure that Xilinx companies release.It is mainly used in
The FPGA of Xilinx companies realizes that SOPC is designed.In the IP storehouses that Xilinx companies provide, have and PLB is based on based on the total line cores of AXI
The ethernet controller of bus, as AXI buses and PLB buses are the versabus from architecture design many towards many masters, at that time
Sequence is complicated, and bus communication speed is slow.
In the secondary device of digital transformer substation, multiple ethernet controllers, the stream of each ethernet controller are needed
Amount is all than larger.Microblaze systems can easily extend multiple ethernet controllers, but using based on AXI buses and
The controller speed of PLB buses is slower, it is impossible to meet the data transfer needs of the big flow of digital transformer substation.
The content of the invention
In view of this, the application provides a kind of control method of the ethernet controller of digital transformer substation, for meeting
The data transfer of the big flow of digital transformer substation needs.
To achieve these goals, it is proposed that scheme it is as follows：
A kind of control method of the ethernet controller of digital transformer substation, comprises the steps：
Send read/write command；
Virtual address is sent according to the read/write command, the virtual address includes reading and writing flag bit, depositor first address
And data length；
The virtual address is sent by a FSL buses；
Receive the virtual address；
The virtual address is parsed, the read-write flag bit, the depositor first address and the number is parsed
According to length；
Chosen depositor is selected from the depositor group of the ethernet controller according to the depositor first address；
Write operation is carried out to the chosen depositor by the attribute of the read-write flag bit, or it is total by the 2nd FSL
Line carries out read operation by the data length.
Preferably, the virtual address includes two 32 data；
The read-write flag bit is the 1st data of the one 32 data in described two 32 data；
2～32 data of the one 32 data are the depositor first address；
The 2nd 32 data in described two 32 data are the data length.
Preferably, the 1st data are 1 expression write operation；1st data are 0 expression read operation.
From above-mentioned technical proposal as can be seen that a kind of this application provides control of the ethernet controller of digital transformer substation
There is read write command first in method processed, the method；Virtual address is exported according to read write command；Sent out using a FSL data/address bus
Give the virtual address；Then the virtual address is received at ethernet controller end；Read-write mark is parsed from the virtual address
Position, depositor first address and data length；Chosen depositor is selected according to the depositor first address；By data length to selected
Determining depositor carries out write operation or carries out read operation to chosen depositor by the 2nd FSL data/address bus.In the application first
Using a FSL bus transfer virtual addresses, then depositor is selected using virtual address, and it is chosen to what is selected
Depositor carries out write operation by a FSL data/address bus or carries out read operation by the 2nd FSL buses, can thus utilize
The high-speed transfer characteristic of FSL data/address bus completes the control purpose towards address, also just can be used in meeting digital transformer substation
Big flow data transfer need.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of application, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
A kind of flow process of the control method of the ethernet controller of digital transformer substation that Fig. 1 is provided for the embodiment of the present application
Figure；
A kind of schematic diagram of the read procedure of ethernet controller that Fig. 2 is provided for the application；
A kind of schematic diagram for writing process of ethernet controller that Fig. 3 is provided for the application.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only some embodiments of the present application, rather than the embodiment of whole.It is based on
Embodiment in the application, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of the application protection.
A kind of flow process of the control method of the ethernet controller of digital transformer substation that Fig. 1 is provided for the embodiment of the present application
Figure.
As shown in figure 1, the control method of the ethernet controller of the present embodiment offer comprises the steps：
S101：Send read write command.
According to data transfer need send read command or write order, write order is to the corresponding of ethernet controller
Depositor output data message, read command are from the corresponding depositor of ethernet controller to read data message.
S102：Output virtual address.
The application is to be written and read operation using the high-speed transfer characteristic of FSL buses, meets digital transformer substation with this
Massive dataflow transmission needs, but FSL buses are a kind of buses of Data Flow Oriented, rather than towards the total of address control
Line, therefore here transfer of virtual address first, are addressed to depositor using virtual address.
FSL buses transmit 32 data within a clock cycle, therefore first send two 32 using 2 clock cycle
The virtual address of data, the virtual address include read-write flag bit, depositor first address and data length.From two 32 digits
According to the one 32 data the 1st be as read-write flag bit, representing when which is 1 carries out write operation to ethernet controller,
Read operation is carried out if 0 expression；In one 32 data, 2～32 data are used as depositor first address；Two 32 digits
According to the 2nd 32 data as data length.
S103：Virtual address is sent by a FSL data/address bus.
Read or write is carried out using two FSL data/address bus in the present embodiment, here by a FSL data/address bus
The virtual address is sent to ethernet controller.
S104：Receive the virtual address.
Or the virtual address is received by a FSL buses.
S105：Virtual address is parsed.
Virtual address is parsed, the read-write flag bit that includes in parsing the virtual address, depositor first address and
Data length.
S106：Selected depositor.
After parsing the depositor first address in virtual address, phase is selected from depositor group according to the depositor first address
The depositor answered is used as chosen depositor.
S107：Carry out read operation or write operation
The depositor of ethernet controller is operated according to the attribute of read-write flag bit.
When read-write flag bit is 1, write operation is carried out to ethernet controller, data length is pressed to chosen depositor at this moment
Write operation is carried out, when write operation is carried out still using a FSL data/address bus FSL0 to ethernet controller output data report
Text, writes process as shown in Figure 2.
When read-write flag bit is 0, read operation is carried out to ethernet controller, data length is pressed to chosen depositor at this moment
Read operation is carried out, when read operation is carried out, is to read datagram from ethernet controller using the 2nd FSL data/address bus FSL1
Text.Read procedure is as shown in Figure 3.
From above-mentioned technical proposal as can be seen that present embodiments providing a kind of ethernet controller of digital transformer substation
There is read write command first in control method, the method；Virtual address is exported according to read write command；Using a FSL data/address bus
Send the virtual address；Then the virtual address is received at ethernet controller end；Read-write mark is parsed from the virtual address
Will position, depositor first address and data length；Chosen depositor is selected according to the depositor first address；By data length to quilt
Selected depositor carries out write operation or carries out read operation to chosen depositor by the 2nd FSL data/address bus.It is first in the application
First with a FSL bus transfer virtual addresses, then depositor is selected using virtual address, and it is selected to what is selected
Determining depositor carries out write operation by a FSL data/address bus or carries out read operation by the 2nd FSL buses, thus can be with profit
The control purpose towards address is completed with the high-speed transfer characteristic of FSL data/address bus, also just can be used in meeting Digitized transformation
The data transfer needs of the big flow stood.
In this specification, each embodiment is described by the way of progressive, and what each embodiment was stressed is and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.To the upper of the disclosed embodiments
State bright, professional and technical personnel in the field is realized or is used the application.To various modifications of these embodiments to ability
Will be apparent for the professional and technical personnel in domain, generic principles defined herein can be without departing from the application's
In the case of spirit or scope, realize in other embodiments.Therefore, the application be not intended to be limited to it is shown in this article these
Embodiment, and it is to fit to the most wide scope consistent with principles disclosed herein and features of novelty.
Claims (3)
1. a kind of control method of the ethernet controller of digital transformer substation, it is characterised in that comprise the steps：
Send read/write command；
Virtual address is sent according to the read/write command, the virtual address includes reading and writing flag bit, depositor first address sum
According to length；
The virtual address is sent by a FSL buses；
Receive the virtual address；
The virtual address is parsed, the read-write flag bit, the depositor first address and the data is parsed long
Degree；
Chosen depositor is selected from the depositor group of the ethernet controller according to the depositor first address；
Write operation is carried out to the chosen depositor by the attribute of the read-write flag bit, or is pressed by the 2nd FSL buses
The data length carries out read operation.
2. control method as claimed in claim 1, it is characterised in that the virtual address includes two 32 data；
The read-write flag bit is the 1st data of the one 32 data in described two 32 data；
2～32 data of the one 32 data are the depositor first address；
The 2nd 32 data in described two 32 data are the data length.
3. control method as claimed in claim 2, it is characterised in that the 1st data are 1 to represent write operation；Described 1st
Position data are 0 expression read operation.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410705443.0A CN104360668B (en) | 2014-11-28 | 2014-11-28 | Control method of Ethernet controller of digital substation |
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| CN201410705443.0A CN104360668B (en) | 2014-11-28 | 2014-11-28 | Control method of Ethernet controller of digital substation |
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| CN104360668A CN104360668A (en) | 2015-02-18 |
| CN104360668B true CN104360668B (en) | 2017-05-03 |
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| FR2755523B1 (en) * | 1996-11-05 | 1998-12-04 | Bull Sa | ELECTRIC CIRCUIT FOR EXCHANGING DATA BETWEEN A MICROPROCESSOR AND A MEMORY AND COMPUTER COMPRISING SUCH A CIRCUIT |
| CN1261883C (en) * | 2002-11-29 | 2006-06-28 | 上海奇码数字信息有限公司 | Storing structure and addressing method for internal data and digital signal processor |
| CN101895397A (en) * | 2010-07-09 | 2010-11-24 | 安徽科大鲁能智能电网技术有限公司 | Digital signal processor (DSP)-based industrial Ethernet serial server and control method thereof |
| CN102937939B (en) * | 2012-10-10 | 2015-12-16 | 无锡众志和达数据计算股份有限公司 | Based on the DMA address of SATA controller to pre-reading method |
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