CN104360166B

CN104360166B - Digital demodulation system phase error elimination method for bioimpedance measurement

Info

Publication number: CN104360166B
Application number: CN201410719931.7A
Authority: CN
Inventors: 费智胜; 徐现红; 高松; 戴涛; 向飞; 蒲洋; 卜力宁
Original assignee: SILAN TECHNOLOGY (CHENGDU) Co Ltd
Current assignee: SILAN TECHNOLOGY (CHENGDU) Co Ltd
Priority date: 2014-12-02
Filing date: 2014-12-02
Publication date: 2020-01-07
Anticipated expiration: 2034-12-02
Also published as: CN104360166A

Abstract

The invention belongs to the technical field of bioimpedance measurement, and particularly discloses a digital demodulation system phase error elimination method suitable for bioimpedance measurement. The method comprises the following specific steps: initialChanging the system condition variable and the cycle length of the input signal; judging whether the system is started; starting a period timer and an ADC (analog-to-digital converter) at the same time; to ADC converter at T_2n‑1Carrying out periodic time delay on the digital signal obtained by conversion in the time period; and detecting and judging whether the number of the cycles is an even number or not, and outputting a digital signal. Therefore, the invention carries out the periodic delay on the sampling time of two groups of periodic signals in a periodic delay mode, so that the initial phases of the two groups of same periodic signal samples are in the same value, the interval of starting sampling the two groups of signals by the ADC in the digital demodulation process is integral multiple of the period of the input analog signal, the problem of phase error caused by different phases of the two groups of signals acquired by the ADC is solved, and the aim of improving the accuracy of the operation of the acquired data is fulfilled.

Description

Digital demodulation system phase error elimination method for bioimpedance measurement

Technical Field

The invention belongs to the technical field of bioimpedance measurement, and particularly relates to a phase error elimination method of a digital demodulation system suitable for bioimpedance measurement.

Background

In the bio-impedance measurement, the impedance of a measured body is usually measured by adding an excitation current to measure the voltage of the measured tissue, and two sets of signals are often measured in the actual measurement: voltage signals and current signals of the tissue to be measured. The impedance of the measured tissue is obtained through ohm's law R ═ U/I, and if digital demodulation is adopted, the ADC may acquire non-uniform acquisition intervals when acquiring the two groups of signals, so that phase errors exist in the two groups of acquired signals.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method for eliminating the phase error of a digital demodulation system for measuring the bio-impedance, which has the advantages of low cost, accurate operation, uniform acquisition interval of two groups of signals by an ADC in the digital demodulation process and solves the problem of the phase error of the two groups of signals acquired by the ADC due to different phases.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a digital demodulation system phase error elimination method for bioimpedance measurement comprises the following specific steps:

initializing system condition variables and input signal period length, wherein the period length is T, and the number of periods is n, and the system comprises a period timer and an ADC (analog-to-digital converter);

step two, judging whether the system is started; if started, wait for a timer T_2nWhen the value is less than the preset period value nT, the period timer is in a waiting timing state; while waiting for the timing time T_2nWhen the value is not less than the preset period value nT, the next step is carried out; if the system is not started, directly switching to the next step three;

step three, simultaneously starting the period timer and the ADC, wherein the conversion completion time of the analog signal collected by the ADC is T_2n-1；

Step four, the ADC converter is subjected to T_2n-1Carrying out periodic time delay on the digital signal obtained by conversion in the time period, and directly entering the next step five after time delay;

step five, detecting and judging whether the number n of the periods is an even number, wherein when the number n of the detected periods is equal to the even number, the digital signal P after the period delay processing in the step four is output, the period timer is closed and the system is finished; and when the number n of the detection periods is an odd number, outputting the digital signal Q subjected to the period delay processing in the fourth step, automatically accumulating 1 for the number n of the periods, and returning to the second step.

In an embodiment of the present invention, in the third step, when the transition is completed for a time T_2n-1When the period length is less than T, the ADC converter is in waiting for converting ADC acquisition data; when the conversion is completed for time T_2n-1And when the period length is more than or equal to the period length T, the acquired data is converted in the ADC, and the next step is carried out.

In an embodiment of the present invention, the signal P and the signal Q are two different signals, and they are respectively a current signal or a voltage signal.

In an embodiment of the present invention, the number n of cycles is an integer.

In an embodiment of the present invention, the period delay time in the fourth step may be 1/4T, 1/2T or nT.

After adopting the structure, compared with the prior art, the invention has the beneficial effects that: the invention carries out the periodic time delay on the time of sampling two groups of periodic signals in a periodic time delay mode, so that the initial phases of the two groups of same periodic signal samples are in the same value, the ADC acquires the two groups of signals at uniform intervals in the digital demodulation process, the problem of phase errors caused by the fact that the two groups of signals acquired by the ADC are different in phase is solved, and the aim of improving the accuracy of the acquired data operation is fulfilled.

Drawings

The invention is further illustrated with reference to the following figures and examples.

Fig. 1 is a flow chart of a phase error elimination method of a digital demodulation system according to the invention.

Fig. 2 is a control timing diagram of the input signal Vin' before sampling by the ADC according to the method of the present invention.

Fig. 3 is a timing diagram of the control of the output signal Vin sampled by the ADC according to the method of the present invention.

Detailed Description

The following description is only a preferred embodiment of the present invention, and does not limit the scope of the present invention.

As shown in fig. 1, the present invention provides a phase error cancellation method for a digital demodulation system for bio-impedance measurement, which comprises the following specific steps:

the method comprises the steps of initializing system condition variables and input signal period length, wherein the period length is T, the period number is n, and n is an integer, the system is a digital demodulation phase error elimination system and comprises a period timer and an ADC (analog to digital converter), the period timer is used for finishing continuous timing with the period length of T, and the ADC is used for sampling sine and cosine signal data in n periods of T, namely the ADC converts an input signal into an analog signal into a digital signal. In the embodiment of the invention, the period length T is consistent with the sampling length of the ADC.

Step two, judging whether the system is started; if started, wait for a timer T_2nWhen the value is less than the preset period value nT, the period timer is in a waiting timing state; while waiting for the timing time T_2nWhen the value is not less than the preset period value nT, closing the period timer and turning to the next step III; if the system is not started, directly turning to the next step three.

Step three, simultaneously starting the period timer and the ADC, wherein the conversion completion time of the analog signal collected by the ADC is T_2n-1(ii) a Wherein, when the conversion is completed for time T_2n-1When the period length is less than T, the ADC converter is in waiting for converting ADC acquisition data; when the conversion is completed for time T_2n-1And when the period length is more than or equal to the period length T, the acquired data is converted in the ADC, and the next step is carried out. After the period timer is started, the operating mode is in a continuous timing mode, and a signal of CNT _ complete 1 is generated once when the timing is finished; after which a new cycle of cycle timing is started.

Step four, the ADC converter is subjected to T_2n-1And (4) carrying out periodic time delay on the digital signal obtained by conversion in the time period, and directly entering the next step five after time delay. To ensure at T_2n-1There is enough time to wait for the next start of the periodic timer after the conversion of the collected signal is completed in the time period, and the period delay time can be 1/4T, 1/2T or nT.

The signal P and the signal Q are two signals with different properties, and the signals are respectively current signals or voltage signals. Therefore, the signal P and the signal Q are acquired and converted by the ADC in sequence, and the cost of the ADC is high, so that the operation cost is greatly reduced compared with the prior art that a plurality of ADC converters are adopted to acquire a plurality of groups of signals simultaneously.

The embodiments are specifically explained below according to the above-mentioned technical solution of the invention, and refer to fig. 2 and 3.

In this embodiment, taking the initial value of the number n of cycles as 1, the system condition variables and the initial values thereof are initialized as follows: the FLAG bit (TIME _ START _ FLAG) for starting the cycle timer for the first TIME is 0, the timer completion FLAG bit (CNT _ complete) for the cycle timer is 0, the ADC conversion completion FLAG bit (ADC _ complete) is 0, and the signal selection count FLAG bit (SIG _ select) is 0. Wherein TIME _ START _ FLAG equal to 0 indicates that the cycle timer is not started, CNT _ complete is 0 to indicate that the cycle timer timing is not completed, ADC _ complete is 0 to indicate that the ADC acquisition conversion is not completed, and SIG _ select is 0 to indicate that no signal acquisition is performed.

Judging whether the system is started for the first time according to the timing value of the preset period timer, if so, simultaneously starting the period timer and the ADC, and at the moment, the acquisition and conversion completion time of the system is T₁. If the system is not started for the first time, the timing time T of the periodic timer is judged₂If it is done, T if it is done₂Equal to T or integral multiple of T, and starting the next ADC converter to start conversion, wherein the acquisition conversion completion time of the ADC is T₃Simultaneously closing the timer; if not, waiting for the cycle timer to finish, T₂Not equal to T or an integer multiple of T. Thus, the invention passes through T₂The data latency is adjusted to be equal to T or an integer multiple of T so that the phases of the two acquired signals are the same without changing the input signal Vin.

Specifically, after the system is started, namely the period timer is started, the FLAG bit TIME _ START _ FLAG of the first TIME period timer is set to 1; after the counting of the period timer is completed, that is, the timing of the period timer is completed, the timing completion flag bit CNT _ complete of the period timer is set to 1; when the timing is finished and the CNT _ complete is detected to be 1, the CNT _ complete is set to 0.

And after the ADC is started, waiting for the completion of the conversion of the ADC, wherein the completion of the conversion of the ADC represents that the signal data of one period is acquired. Specifically, after the ADC is started, the ADC conversion completion flag ADC _ complete will be set to 0. And waiting for the completion of the acquisition and conversion of the ADC, and completing the acquisition, wherein the ADC conversion completion identification bit ADC _ complete is set to be 1.

If the conversion is complete 1/4 cycle delay module is executed, wherein the purpose of the cycle delay of 1/4T is T₁After the acquisition conversion is completed within the time, there is enough time to wait for the next start of the cycle timer. Judging whether the number n of the signal selection periods is an even number or not after the time delay 1/4 periods, and when the acquired signal is T₁During the time period, if the number n of the periods is odd, 1 is automatically accumulated and the next conversion is started by skipping; when the collected signal is T₃And in the time period, if the number n of the periods is an even number, closing the period timer and then ending the system. In the embodiment of the invention, the signal selection count SIG _ select is accumulated, and the signal selection count SIG _ select equals to 1 to represent T₁The acquisition conversion is completed, SIG _ select is 2 to represent T₃And finishing acquisition conversion.

As shown in FIG. 2, the input analog signal in the embodiment of the present invention is an input continuous sinusoidal signal Vin' at T₁'collecting the voltage analog signal P' of the tested tissue at any moment₃The current analog signal Q' of the tested tissue is acquired at the moment T due to the switching of different analog signals₁' and T₃There is an indeterminate data processing latency T between₂' the collected voltage signal and current signal have unfixed phase errors, which causes errors in operation.

As shown in fig. 3, after the technical solution of the present invention, the system obtains the voltage digital signal P and the current digital signal Q after the conversion and the period delay of the ADC converter, where T is the voltage digital signal P and the current digital signal Q₁The voltage analog signal P of the tested tissue is collected at the moment T₃The current analog signal Q of the tested tissue is acquired at any time, and T is obtained according to the technical scheme of the invention and can be known by the technical personnel in the field₁' equal to T₁Or the period length T, T₃' equal to T₃The period length T; but T₂Is not equal to T₂', but is equal to T₁Or T₃Or an integer multiple of the period length T.

In summary, the invention performs the periodic delay on the sampling time of two groups of periodic analog signals by the periodic delay way, so that the initial phases of the two groups of same periodic analog signal samples are at the same value, and the interval of starting sampling the two groups of signals by the ADC in the digital demodulation process is the integral multiple of the period of the input analog signal and the real-time acquisition delay, thereby achieving the purpose of eliminating the phase error of the two groups of signals acquired by the ADC due to different phases, and improving the accuracy of the data acquisition operation.

The foregoing is only a preferred embodiment of the invention, and the scope of the invention is not to be interpreted as limiting, since the invention will be apparent to those skilled in the art from this disclosure and can be modified in various ways.

Claims

1. A digital demodulation system phase error elimination method for bioimpedance measurement comprises the following specific steps:

Step four, the ADC converter is subjected to T_2n-1The digital signal obtained by conversion in the time period is subjected to periodic time delay and delayedDirectly entering the next step five;

2. The method for removing phase error of digital demodulation system as claimed in claim 1, wherein in step three, when the conversion is completed for time T_2n-1When the period length is less than T, the ADC converter is in waiting for converting ADC acquisition data; when the conversion is completed for time T_2n-1And when the period length is more than or equal to the period length T, the acquired data is converted in the ADC, and the next step is carried out.

3. The method for eliminating phase error of digital demodulation system as claimed in claim 1, wherein said digital signal P and said digital signal Q are two different signals with different properties, and they are current signal or voltage signal respectively.

4. The method of claim 1, wherein the number n of periods is an integer.

5. The method as claimed in claim 1, wherein the period delay time in the fourth step is 1/4T, 1/2T or nT.