CN104347101B - Data processing method and device - Google Patents
Data processing method and device Download PDFInfo
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- CN104347101B CN104347101B CN201310344081.2A CN201310344081A CN104347101B CN 104347101 B CN104347101 B CN 104347101B CN 201310344081 A CN201310344081 A CN 201310344081A CN 104347101 B CN104347101 B CN 104347101B
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Abstract
The present invention provides a kind of data processing method and device.Methods described comprises the following steps.Described device includes modular converter and control module.Modular converter receives clock signal via pin, and determines according to the time span in the corresponding cycle of clock signal the bit value of the first data.Control module decides whether to carry out bit write operation according to clock signal with the first data, by bit value write-in memory.
Description
Technical field
The invention relates to a kind of electronic installation, and in particular to a kind of data processing method and device.
Background technology
In recent years, with requirement more and more higher of the consumer for multi-medium data quality, multi-medium data coffret
Development it is also increasingly flourishing.When multi-medium data is transmitted by the interface of high-res, high frequency range digital content can be often used
(High-Bandwidth Digital Content Protection, HDCP) is protected to prevent data to be stolen.Work as user
When thinking the data that viewing is protected by HDCP, it is necessary to use the playing device and display device of built-in HDCP keys.Playing device
Being had to pass through with display device both sides could smooth played data after a verification process for intercoursing key.If verification process
In go wrong, the data protected by HDCP play when it is possible that picture resolution reduction, sound quality it is not good or
The problems such as can not playing.One HDCP keys group is typically to be made up of the key of 40 56 bits.Produce board or test machine
Platform can according to an a bit then bit mode, these keys are write into circuit under test（Such as playing device and/or display dress
Put）Memory in.
Tester table can be by multiple pins by data（Such as HDCP keys or other data）Write circuit under test
In memory, to carry out functional test to the circuit under test.For example, Fig. 1 is the tester table and the circuit under test
Between classical signal sequential example schematic.In order to carry out functional test, between the tester table and the circuit under test
The data pins and other relevant control pins for transmitting data DATA1 are configured with, such as transmitting clock signal
CLK1 clock pin etc..The circuit under test receives clock signal clk 1 from clock pin, and receives number from data pins
According to DATA1.The circuit under test can sample according to the sequential of clock signal clk 1/and latch data DATA1 bit value, enters
And produce corresponding data DATA2 in the inside of the circuit under test.In addition to clock signal clk 1 and data DATA1, institute
The programming signal of multiple difference in functionalitys can also be provided by stating tester table（programing signal）Inside the circuit under test
Memory.The control of these programming signals is exported according to the tester table, the circuit under test can be by data DATA2
Write in the memory inside circuit under test.Therefore, except transmitting the pin of clock signal clk 1 and connecing for transmission data DATA1
Plurality of control pin is also configured outside pin, between the tester table and the circuit under test to transmit these programmings
Signal is to the memory inside circuit under test.
On the other hand, the circuit under test（Such as playing device and/or display device）Memory can be any shape
Memory cell/circuit of formula, such as One Time Programmable（One-time programmable,OTP）Memory or other are non-
Volatile storage (non-volatile memory).The bit write operation（These keys are write into otp memory）It is past
Taken considerable time toward needs.When data DATA2 is write into otp memory, tester table often can only be to compare one at a time
Data DATA2 is write otp memory by special mode.When the data DATA2 of otp memory to be write data volume is very huge
When, a HDCP keys group being made up of 40 56 bit keys is for example write into otp memory, or even will be multiple
HDCP keys group writes otp memory, and tester table needs to take a substantial amount of time the data DATA2 write-ins of substantial amounts
Otp memory.In the embodiment shown in fig. 1, the time span in each cycle of clock signal clk 1 is T1.In order to
Ensure each than peculiar enough time to complete bit write operation, therefore the time in each cycle of clock signal clk 1
Length T1 have to be larger than the time rating length of the bit write operation.
The content of the invention
The present invention provides a kind of data processing method and device, can reduce by data from outside transmit to chip when
Between and/or pin.
The data processing method of the present invention includes：Clock signal is received via the pin of integrated circuit；According to clock signal
The time span in corresponding cycle determine the bit value of the first data；And determine to be with the first data according to clock signal
No progress bit write operation, the bit value is write in memory.
The data processing equipment of the present invention includes modular converter and control module.The first end of modular converter receives clock
Signal.Modular converter determines the bit value of the first data according to the time span in the corresponding cycle of clock signal.Control module
Couple modular converter.According to clock signal and the first data, control module decides whether to carry out bit write operation, and this is compared
Paricular value writes memory.
Based on above-mentioned, the data processing method and data processing equipment of the embodiment of the present invention pass through modulation clock signal
The time span in cycle, therefore the time of transmission/processing data can be reduced.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make
Carefully it is described as follows.
Brief description of the drawings
Fig. 1 is the classical signal sequential example schematic between tester table and circuit under test；
Fig. 2 is that one embodiment of the invention illustrates a kind of schematic flow sheet of data processing method；
Fig. 3 is the circuit box schematic diagram that first embodiment of the invention illustrates a kind of data processing equipment；
Fig. 4 is the signal sequence schematic diagram that one embodiment of the invention illustrates data processing equipment shown in Fig. 3；
Fig. 5 is the circuit box schematic diagram that second embodiment of the invention illustrates a kind of data processing equipment；
Fig. 6 is the signal sequence schematic diagram that another embodiment of the present invention illustrates data processing equipment shown in Fig. 5；
Fig. 7 is the circuit box schematic diagram that third embodiment of the invention illustrates a kind of data processing equipment；
Fig. 8 is that fourth embodiment of the invention illustrates a kind of circuit box schematic diagram shown by data processing equipment.
Description of reference numerals：
300、500、700、800：Data processing equipment；
310、510、730：Modular converter；
320、520、740：Control module；
330、530、750：Memory；
540、760：Processor；
720：Modulating unit；
311、511、731：Filter element；
313：Sampling unit；
513、733：Demodulation unit；
710：Arithmetic element；
CLK1、CLK2：Clock signal；
DATA1、DATA2、DATA3、DATA4、DATA5、DATA6：Data；
S201~S205：Step；
T1、T2：The time span in cycle.
Embodiment
Earlier figures 1 illustrate that the time span in each cycle of clock signal clk 1 is T1.It is every in order to ensure
One completes bit write operation, therefore the time span T1 in each cycle of clock signal clk 1 than peculiar enough time
It has to be larger than the time rating length of the bit write operation.Anyway, only when a bit value is the first logical value
（Need the bit value of progress bit write operation）When, the cycle time of this bit value just needs time span T1.When one
Bit value is the second logical value（The bit value of bit write operation need not be carried out）When, for this bit value, have
Time span T1 cycle time is obviously too many, because this bit value need not carry out bit write operation.If can shorten
By the transmission time of the incoming circuit under test of data DATA1, and/or it is that can shorten to treat described in data DATA2 write-ins
The operating time of otp memory in slowdown monitoring circuit, and/or be that can reduce to transmit data and associated control signal to described to treat
Pin count needed for slowdown monitoring circuit, then can effectively save cost.
Fig. 2 is that one embodiment of the invention illustrates a kind of schematic flow sheet of data processing method.Fig. 3 is that the present invention first is real
Apply the circuit box schematic diagram that example illustrates a kind of data processing equipment.Data processing equipment 300 includes modular converter 310, control
Module 320 and memory 330.Fig. 4 is the signal sequence signal that one embodiment of the invention illustrates data processing equipment shown in Fig. 3
Figure.Fig. 2, Fig. 3 and Fig. 4 are refer to, modular converter 310 receives clock signal clk 2 (step S201) via clock pin, and turns
Change the mold block 310 and receive data DATA3 via data pins.This data DATA3 can be the data of any form or any content
Signal, such as data DATA3 can be encryption and decryption key (such as HDCP keys or other encryption and decryption keys).This clock signal
CLK2 and data DATA3 can be that the front stage circuits in data processing equipment 300 are provided or data processing equipment
Circuit outside 300（Such as production board or tester table）There is provided.
Clock signal clk 2 has multiple cycles.Modular converter 310 can be according to the corresponding cycle of clock signal clk 2
Time span carrys out determination data DATA4 bit value (step S203).For example, in the present embodiment, data processing equipment 300 can
With the sequential according to clock signal clk 2（The sequential of such as falling edge）Sampling/latch data DATA3 bit value, Jin Er
The inside of data processing equipment 300 produces corresponding data DATA4.
Control module 320 couples modular converter 310, to receive data DATA4 and other phases that modular converter 310 is exported
Close control/trigger signal（Herein omit and it is not shown）.Control module 320 is determined according to clock signal clk 2 and data DATA4
It is fixed whether to carry out the bit write operation.In the present embodiment, control module 320 can be provided according to modular converter 310
Data DATA4 produce the programming signals of multiple difference in functionalitys to correspond to（programing signal）Sprog is to memory
330.For example, when data DATA4 bit value is the first logical value（The bit value of progress bit write operation is needed, for example
Logic 1）When, control module 320 can be entered by programming signal Sprog setting to some corresponding bit in memory 330
The row bit write operation, so as to by the corresponding bit of the first logical value programming to memory 330.In another example, work as number
It is the second logical value according to DATA4 bit value（The bit value of bit write operation, such as logical zero need not be carried out）When, control
Molding block 320 can make some corresponding bit in memory 330 be maintained at initial state by adjusting this programming signal Sprog
（I.e. without the bit write operation）, to make the corresponding bit of memory 330 be maintained at the second logical value（Initially
State）.Therefore, control module 320 can decide whether to carry out the bit write-in according to clock signal clk 2 and data DATA4
Operation, memory 330 (step S205) is write by data DATA4 bit value.
The memory 330 can be any type of memory element/circuit, such as disposable programmable (One-time
Programmable, OTP) memory or other non-volatility memorizers (non-volatilememory).Otp memory can
With using electrical fuse (E-fuse) or other there is the memory element of similar functions come record data.For example, system can be with
By the programming of electrical fuse（trim）State（The state being blown）Logic value definition be the first logical value（Such as logic 1）,
And by the initial state of electrical fuse（The state not being blown）Logic value definition be the second logical value（Such as logical zero）.At it
In his embodiment, first logical value can be logical zero, and second logical value can be logic 1.Due to blowing electronics
The process of fuse is irreversible, so the information write in otp memory is permanent.
Embodiment illustrated in fig. 4 is referred to Fig. 1 related description and analogizes it.Different from place of embodiment illustrated in fig. 1,
It is modulated in the cycle time of clock signal clk 2 shown in Fig. 4.When data DATA3 bit value is the first logical value（I.e.
Need the bit value of progress bit write operation, such as logic 1）When, the time span in the corresponding cycle of this bit value is T1（Such as
Shown in Fig. 4）, wherein time span T1 have to be larger than the time rating length of the bit write operation.Therefore, control module
320 have time enough length T1 to carry out the bit write operation, so as to by the bit value programming with the first logical value
To memory 330.When data DATA3 bit value is the second logical value（The bit value of bit write operation need not be carried out,
Such as logical zero）When, the time span in the corresponding cycle of this bit value is T2（As shown in Figure 4）, wherein time span T2 is less than institute
The time rating length of bit write operation is stated, because this bit value need not carry out the bit write operation.Due to by when
Time spans of the clock signal CLK2 with bit value in data DATA3 for the corresponding cycle of the second logical value shorten to T2, therefore can
To shorten the transmission time of the incoming modular converters 310 of data DATA3.Further, control module 320 can be according to data
DATA4 bit value and decide whether to carry out memory 330 the bit write operation.For example, when data DATA4 bit
It is worth for the second logical value（The bit value of bit write operation, such as logical zero need not be carried out）When, control module 320 can be with
Reset（reset）The timer of the bit write operation, to terminate current bit write operation ahead of time, and addressing is next
Bit is to prepare next bit write operation.Therefore, data processing equipment 300, which can shorten, deposits data DATA4 write-ins
The operating time of reservoir 330.
Modular converter 310 can realize it in any way.For example, in the embodiment shown in fig. 3, modular converter 310
Include filter element 311 and sampling unit 313.In the present invention, filter element 311 is, for example, high-pass filter, band logical
Wave filter, low pass filter or other filter circuits, and sampling unit 313 be, for example, latch unit, flip-flop or other take
Sample/latch circuit.
The first end of filter element 311 is coupled to the clock pin of modular converter 310 to receive the clock signal of outside
CLK2.Then, filter element 311 can filter the noise in clock signal clk 2.The coupling filter element 311 of sampling unit 313
Second end was to receive the clock signal clk after noise filtering 2.Sampling unit 313 is separately coupled to the data pins of modular converter 310
To receive data-signal（Such as data DATA3）.Sampling unit 313 understands the sequential according to clock signal clk 2 and sampled data is believed
Number DATA3, with obtain and determination data DATA4 logical value, and data DATA4 is transferred to control module 320.
In step S205, after the logical value that control module 320 receives data DATA4, inside control module 320
Timer (or counter) stand-by period can be started counting up, to wait for the bit write operation.Work as data
DATA4 bit value is the first logical value（Need the bit value of progress bit write operation, such as logic 1）When, Zhi Daoji
When stand-by period for being counted of device reach the bit write operation time rating (such as several microseconds) before, control module
320 do not reset（reset）The stand-by period that timer is counted, so that control module 320 can be carried out to this bit value
Bit write operation, that is, by this bit value programming into memory 330.When data DATA4 bit value is the second logic
Value（The bit value of bit write operation, such as logical zero need not be carried out）When, because control module 320 need not be to this ratio
Paricular value carries out bit write operation, therefore the stand-by period that 0 reset timer is counted immediately of control module 32, with ahead of time
Terminate current bit write operation, and the next bit of addressing can prepare to handle next bit so as to control module 320
Value.Therefore, data processing equipment 300 can shorten the operating time that data DATA4 is write to memory 330.
In Fig. 1 institutes demonstration example, need to configure plurality of control between traditional test board and traditional circuit under test
Pin transmits the programming signal of multiple difference in functionalitys（Or one group of bus（bus）Signal）To the memory inside circuit under test.
Traditional test board can control the memory inside circuit under test to go to carry out bit write-in by producing these programming signals
Operation.However, traditional test board needs to take a lot of time to be intended to programming data（Such as test sample（test
pattern））Be converted to programming signal.In Fig. 3 and embodiment illustrated in fig. 4, the front stage circuits of data processing equipment 300（For example
Tester table）Only need to a desire programming data sequential and send modular converter in data DATA3, and by data DATA3
310, modular converter 310 can just produce corresponding data DATA4 to control module 320.Control module 320 can be according to data
DATA4 produces programming signal Sprog to memory 330 to correspond to.That is, the front stage circuits of data processing equipment 300（Example
Such as tester table）These programming signals Sprog need not be produced.Therefore, the present embodiment can reduce front stage circuits（For example test
Board）The quantity of required control pin and saving are converted to test sample the time of correspondence programming signal.In addition, Fig. 3 and Fig. 4
The front stage circuits of data processing equipment 300 in illustrated embodiment（Such as tester table）The test sample data volume produced can be with
The test sample data volume produced less than traditional test board shown in Fig. 1 embodiments.
The implementation of above-mentioned data processing equipment should not be so limited to embodiment illustrated in fig. 3.For example, Fig. 5 is the present invention the
Two embodiments illustrate a kind of circuit box schematic diagram of data processing equipment.Data processing equipment 500 include modular converter 510,
Control module 520, memory 530 and processor 540.Modular converter 510 shown in Fig. 5, control module 520 and memory 530
It is referred to the related description of modular converter 310 shown in Fig. 3, control module 320 and memory 330 and analogizes it.Fig. 2 correlation
Illustrate also to be applicable to embodiment illustrated in fig. 5.Different from place of embodiment illustrated in fig. 3, being that embodiment illustrated in fig. 5 eliminates figure
Data DATA3 shown in 3 and related data pin.
Fig. 6 is the signal sequence schematic diagram that another embodiment of the present invention illustrates data processing equipment shown in Fig. 5.Shown in Fig. 6
Embodiment is referred to Fig. 4 related description and analogizes it.It refer to Fig. 2, Fig. 5 and Fig. 6, in the present embodiment, modular converter
510 include filter element 511 and demodulation unit 513.Wherein, modulated clock signal clk 2 has been loaded with data（Or
Information）.The clock pin of the first end coupling modular converter 510 of filter element 511 (is walked with the clock signal clk 2 for receiving outside
Rapid S201).Filter element 511 can filter the noise in clock signal clk 2.The clock signal clk after noise filtering 2 is crossed via mistake
Second end of filter unit 511 is transferred to demodulation unit 513 (for example：Demodulator).
The first end of demodulation unit 513 is coupled to the second end of filter element 511 to receive the clock after noise filtering
Signal CLK2.Demodulation unit 513 can be demodulated system to clock signal clk 2, to demodulate data from clock signal clk 2
DATA5（Step S203）.The time span for having served as the corresponding cycle of the clock signal clk after noise filtering 2 is more than a reference value
When, demodulation unit 513 is produced and determination data DATA5 bit value (needs to carry out bit write-in behaviour for the first logical value
The bit value of work, such as logic 1).The time span in corresponding cycle of the clock signal clk after noise filtering 2 has been served as less than described
During reference value, demodulation unit 513 is produced and determination data DATA5 bit value (need not be compared for the second logical value
The bit value of special write operation, such as logical zero).For example shown in Fig. 6, according to the cycle time length T1 for being more than the reference value,
Demodulation unit 513 is produced and determination data DATA5 corresponding bit value is logic 1.According to the cycle for being less than the reference value
Time span T2, demodulation unit 513 is produced and determination data DATA5 corresponding bit value is logical zero.
Demodulated from clock signal clk 2 after data DATA5, data DATA5 is transferred to control mould by demodulation unit 513
Block 520.The input of control module 520 is coupled to demodulation unit 513 to receive data DATA5.Control module 520 is to data
DATA5 carries out bit write operation, by data DATA5 bit value programming to memory 530 (step S205).Control module
520 mode of operation is identical with the mode of operation of control module in first embodiment 320, does not repeat herein.
After data DATA5 is write into memory 530, processor 540 just can read from memory 530 and utilize data
DATA5.For example, if data DATA5 includes HDCP keys, processor 540 just can be with usage record in memory 530
HDCP keys go to verify video streaming, encrypted or decrypted.
In other embodiments, data contained in modulated clock signal clk 2（Or information）Encryption can be included
The HDCP keys crossed.The encrypted HDCP keys are to take reversible logic computing in advance by after the encryption of original HDCP keys
It is made.Wherein, the amount of bits for carrying out the bit write operation is needed in the encrypted HDCP keys less than original
The amount of bits of the progress bit write operation is needed in HDCP keys.Demodulation unit 513 is demodulated from clock signal clk 2
The encrypted HDCP keys（Data DATA5）.The encrypted HDCP keys are write into memory in control module 320
During 530, since it is desired that the amount of bits for carrying out the bit write operation has been reduced, therefore it can shorten data
DATA5 writes the operating time of memory 530.Processor 540 is taken out after the encrypted HDCP keys from memory 530,
Processor 540 can carry out the reversible logic computing to encrypted HDCP keys, so as to which the encrypted HDCP is golden
Key is reduced to original HDCP keys.After original HDCP keys are obtained, processor 540 just can use original HDCP keys to go pair
Video streaming is verified, encrypted or decrypted.The reversible logic computing is detailed later.
In Fig. 1 institutes demonstration example, traditional test board is in the otp memory or electricity by data programming inside circuit under test
During sub- fuse, circuit under test is generally required by one group of bus（bus）To receive the programming signal produced by traditional test board
Carry out the progress of control bit write operation.But traditional test board needs to take a lot of time to be intended to programming data（For example survey
Sample sheet（test pattern））Be converted to programming signal.In Fig. 5 and embodiment illustrated in fig. 6, data processing equipment 500
Front stage circuits（Such as tester table）Only need to the desire programming data sequential being loaded in clock signal clk 2, and will be loaded with
The clock signal clk 2 of data sends modular converter 510 to, and modular converter 510 can just be produced with demodulation clock signal CLK2
Corresponding data DATA5 is to control module 520.Control module 520 to correspond to can produce programming signal according to data DATA5
Sprog is to memory 530.That is, the front stage circuits of data processing equipment 500（Such as tester table）This need not be produced
A little programming signal Sprog.Therefore, the present embodiment can reduce front stage circuits（Such as tester table）The quantity of required control pin
Test sample is converted to the time of correspondence programming signal with saving.Other Fig. 5 and data processing equipment in embodiment illustrated in fig. 6
500 front stage circuits（Such as tester table）The test sample data volume produced might be less that traditional shown in Fig. 1 embodiments
The test sample data volume that tester table is produced.Because the controlling bus signal of programming otp memory or electrical fuse has phase
The relation of sequential is closed, therefore conventional practice needs all timing informations to describe in test sample.It is being intended to programming data very
In the case of big, often the data volume of test sample can become very big.Fig. 5 only needs to produce one successively with the practice shown in Fig. 6
The test sample that desire programming data are inserted, the data volume of test sample can be greatly decreased in this.
Fig. 7 is the circuit box schematic diagram that third embodiment of the invention illustrates a kind of data processing equipment.Implement shown in Fig. 7
Example is referred to Fig. 5 and Fig. 6 related description and analogizes it.Data processing equipment 700 includes arithmetic element 710, modulating unit
720th, modular converter 730, control module 740, memory 750 and processor 760.Modular converter 730 includes filter element
731 and demodulation unit 733.Modular converter 730 shown in Fig. 7, filter element 731, demodulation unit 733, control module
740th, memory 750 and processor 760 can respectively refer to modular converter 510 in Fig. 5, filter element 511, demodulation unit
513rd, control module 520, the related description of memory 530 and processor 540 and analogize it.
Fig. 7 is refer to, the input of arithmetic element 710 receives the second data DATA6, and the second data DATA6 is carried out
Reversible logic computing is exported the first data DATA5 to modulating unit 720 with producing the first data DATA5.Wherein, first
Needing the amount of bits for carrying out bit write operation to be less than in the second data DATA6 in data DATA5 needs to carry out bit write-in
The amount of bits of operation.For example, it is assumed that in memory 750 memory cell initial state（The state not being blown）Logical value determine
Justice be logical zero, and in memory 750 memory cell programming（trim）State（The state being blown）Logic value definition to patrol
1 is collected, then the amount of bits of logic 1 is less than the amount of bits of logic 1 in data DATA6 in data DATA5.
The input of modulating unit 720 is coupled to the output end of arithmetic element 710, to receive data DATA5.Modulating unit
720 output end is coupled to the clock pin of modular converter 730, to provide clock signal clk 2 to modular converter 730.Modulation is single
Member 720 defines very first time length T1 and the second time span T2, and wherein very first time length T1 is more than or equal to bit
Value（Such as logic 1）The required time of memory 750 is write, and the second time span T2 is less than very first time length T1.Work as number
When representing to need to carry out the write operation of bit according to DATA5 bit value, modulating unit 720 is by the correspondence in clock signal clk 2
Cycle set is very first time length T1.When data DATA5 bit value represents to carry out the write operation of bit, adjust
Corresponding cycle set in clock signal clk 2 is the second time span T2 by unit 720 processed.Clock signal clk 2 after modulation
It is referred to Fig. 6 related description and analogizes it.
Demodulation unit 733 is received after modulated clock signal clk 2 by filter element 731, can be from clock signal
Data DATA5 is demodulated in CLK2, and data DATA5 is entered into memory 750 via the programming of control module 740.With data DATA6
Compare, because the amount of bits of logic 1 in data DATA5 is reduced, therefore control module 740 can be reduced data
DATA5 programmings enter the operating time of memory 750.After data DATA5 programming operation is completed, processor 760 just can make
Data DATA5 in memory 750.For example, processor 760 can be used and the identical reversible logic of arithmetic element 710
Computing, data DATA6 is reduced to by the data DATA5 in memory 750.Wherein, data DATA6 can be encryption and decryption gold
Key, such as high frequency range digital content protection（HDCP）Key or other encryption and decryption keys.
In the present embodiment, it may include NOT gate in arithmetic element 710（NOT gate）, XOR gate（exclusive OR
gate,XOR gate）, biconditional gate（exclusive NOR gate,XNOR gate）Or other gates, to carry out institute
State reversible logic computing.Arithmetic element 710 illustrated below carries out producing the first number after reversible logic computing to data DATA6
According to DATA5 not be the same as Example.
In certain embodiments, arithmetic element 710 can provide computing key, and can be using XOR gate to data
DATA6 carries out XOR computing with this computing key, to produce data DATA5.For example, it is assumed that data DATA6 is included
" 1100 ", " 1001 " and " 1101 ", and the computing key is " 1101 ", then arithmetic element 710 utilizes the computing key
" 1101 " carry out producing after XOR computing respectively with " 1100 ", " 1001 ", " 1101 " data DATA5 be " 0001 ",
" 0100 " and " 0000 ".The amount of bits of logic 1 is 7 in data DATA6, and the amount of bits of logic 1 is 2 in data DATA5.
Compared with data DATA6, because the amount of bits of logic 1 in data DATA5 is reduced, therefore control module 740 can subtract
Major general's data DATA5 programmings enter the operating time of memory 750.After data DATA5 programming operation is completed, processor 760
It can use and the identical reversible logic computing of arithmetic element 710（XOR computing）, by the data in memory 750
DATA5 is reduced to data DATA6.For example, processor 760 can be by " 0001 ", " 0100 " and " 0000 " in memory 750
（Data DATA5）Respectively with the computing key " 1101 " carry out XOR computing after produce " 1100 ", " 1001 ",
“1101”。
In another example, it is assumed that data DATA6 includes " 10011101 ", " 00010101 ", " 11001111 " and " 10000111 ",
And the computing key be " 10011101 ", then arithmetic element 710 using the computing key " 10011101 " respectively with
" 10011101 ", " 00010101 ", " 11001111 " carry out producing data DATA5 after XOR computing with " 10000111 "
" 00000000 ", " 10001000 ", " 01010010 " and " 00011010 ".The amount of bits of logic 1 is 5+3+ in data DATA6
6+4=18, and the amount of bits of logic 1 is 0+2+3+3=8 in data DATA6.Compared with data DATA6, due to data DATA5
The amount of bits of middle logic 1 is reduced, therefore control module 740 can reduce data DATA5 programmings entering memory 750
Operating time.
In further embodiments, arithmetic element 710, which can merge multiple HDCP keys, carries out the reversible logic fortune
Calculate.For convenience of explaining, it is 4 bits that a HDCP key is it will be assumed herein.Assuming that 8 HDCP keys be respectively " 1001 ",
" 1101 ", " 0001 ", " 0101 ", " 1100 ", " 1111 ", " 1000 " and " 0111 ", and the computing key is
" 1000110100000101 ", then arithmetic element 710 can using the computing key " 1000110100000101 " respectively with
" 1001110100010101 " carry out producing data DATA5 after XOR computing with " 1100111110000111 "
" 0001000000010000 " and " 0100001010000010 ".With data DATA6（I.e. " 1001110100010101 " with
“1100111110000111”）Compare, due to data DATA5（I.e. " 0001000000010000 " with
“0100001010000010”）The amount of bits of middle logic 1 is reduced, therefore control module 740 can be reduced data
DATA5 programmings enter the operating time of memory 750.
In some other embodiments, arithmetic element 710 can provide computing key, and can utilize biconditional gate logarithm
XNOR logical operation is carried out according to DATA6 and this computing key, to produce data DATA5.
In further embodiments, arithmetic element 710 can be according to the amount of bits judgement of logic 1 in data DATA6
It is no to carry out the reversible logic computing.If needing the amount of bits for carrying out bit write operation to be more than a ginseng in data DATA6
Quantity is examined, then arithmetic element 710 can carry out inverted logic computing using non-goalkeeper's data DATA6, to produce data DATA5.
Fig. 8 is the circuit box schematic diagram that fourth embodiment of the invention illustrates a kind of data processing equipment.Implement shown in Fig. 8
Example is referred to Fig. 7 related description and analogizes it.Different from place of embodiment illustrated in fig. 7, being that data processing shown in Fig. 8 is filled
Arithmetic element 710 shown in Fig. 7 are eliminated in putting 800.That is, modulating unit 720 is directly by original data DATA6（Example
Such as original HDCP keys）It is loaded in clock signal clk 2.When demodulation unit 733 receives modulated by filter element 731
After clock signal CLK2, original data DATA6 can be demodulated from clock signal clk 2, and by data DATA6 via control
The programming of module 740 enters memory 750.After data DATA6 programming operation is completed, processor 760 just can be directly used in
Data DATA6 in memory 750 carries out reversible logic computing without extra.
In summary, the data processing method and device that some embodiments of the present invention are provided can utilize clock signal clk
Correspondence the cycle time span come judge bit value whether need carry out write operation, reduce by bit value write memory when
Between.On the other hand, other embodiments of the invention can be reduced using reversible logic computing and need to carry out bit write-in in data
The amount of bits of operation, further to reduce the time that bit value is write to memory.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (24)
1. a kind of data processing method, it is characterised in that comprise the following steps：
A clock signal is received via a pin；
One reversible logic computing is carried out to an initial data, to produce one first data, the wherein initial data is patrolled including first
The bit of value and the bit of the second logical value are collected, first data include the bit and second logical value of first logical value
Bit, the bit of first logical value needs to carry out bit write operation, and the bit of second logical value need not carry out the ratio
Special write operation, the amount of bits of first logical value of first data is less than the ratio of first logical value in the initial data
Special quantity, and first logical value of first data the ratio that is added with the bit number of second logical value of bit number
Special sum is same as the bit number of first logical value of the initial data and the bit number of second logical value is added
Total number of bits；
A bit value of first data is determined according to a time span in a correspondence cycle of the clock signal；
Decide whether to carry out a memory bit write operation according to the clock signal and first data；
A very first time length and one second time span are defined, wherein the very first time length is more than or equal to the bit value
The required time of the memory is write, and second time span is less than the very first time length；
When the bit value of first data represents to need to carry out the bit write operation, by the correspondence week of the clock signal
Phase is set as the very first time length；And
When the bit value of first data represents to carry out the bit write operation, by the correspondence of the clock signal
Cycle set is second time span.
2. data processing method according to claim 1, it is characterised in that wrap the step of the reception clock signal
Include：
Filter the noise in the clock signal.
3. data processing method according to claim 1, it is characterised in that described correspondence week according to the clock signal
The time span of phase and include the step of determine the bit value of first data：
When the time span in the correspondence cycle is more than a reference value, it is one first logical value to determine the bit value；And
When the time span in the correspondence cycle is less than the reference value, it is one second logical value to determine the bit value.
4. data processing method according to claim 1, it is characterised in that described to decide whether to carry out bit write-in behaviour
As the step of include：
A stand-by period is counted, to wait the completion of the bit write operation；
When the bit value of first data is first logical value, the bit write operation is reached until waiting time
Waiting time is not reseted before time rating, to carry out the bit write operation to the bit value；And
When the bit value of first data is second logical value, the bit write operation is not carried out to the bit value and is laid equal stress on
If waiting time, to handle next bit value.
5. data processing method according to claim 1, it is characterised in that the reversible logic computing includes an inverted logic
Computing, an XOR computing or an XNOR logical operation.
6. data processing method according to claim 5, it is characterised in that the XOR computing includes：
The XOR computing is carried out to the initial data and a computing key, to produce first data.
7. data processing method according to claim 5, it is characterised in that the inverted logic computing includes：
If needing the amount of bits for carrying out the bit write operation to refer to quantity more than one in the initial data, by the original number
According to the inverted logic computing is carried out, to produce first data.
8. data processing method according to claim 1, in addition to：
The reversible logic computing is carried out to first data, using by first data convert as the initial data.
9. data processing method according to claim 1, it is characterised in that the initial data is an encryption and decryption key.
10. data processing method according to claim 9, it is characterised in that the encryption and decryption key includes a high frequency range number
Word content protecting key.
11. data processing method according to claim 1, it is characterised in that first data are an encryption and decryption key.
12. data processing method according to claim 11, it is characterised in that the encryption and decryption key includes a high frequency range number
Word content protecting key.
13. a kind of data processing equipment, it is characterised in that including：
One modular converter, one first end receives a clock signal, a corresponding cycle of the modular converter according to the clock signal
A time span and determine a bit value of one first data；
One control module, couples the modular converter, and the control module decides whether according to the clock signal with first data
One bit write operation is carried out to a memory；
One modulating unit, its output end couples the first end of the modular converter to provide the clock signal, wherein the modulation list
Member defines a very first time length and one second time span, and the very first time length is more than or equal to should by bit value write-in
The required time of memory；Second time span is less than the very first time length；When the bit value of first data is represented
When needing to carry out the bit write operation, the correspondence cycle set of the clock signal is that the very first time is long by the modulating unit
Degree；And when the bit value of first data represents to carry out the bit write operation, when the modulating unit is by this
The correspondence cycle set of clock signal is second time span；And
One arithmetic element, its output end is coupled to the input of the modulating unit, and an input of the arithmetic element receives an original
Beginning data, the wherein arithmetic element carry out a reversible logic computing to the initial data, to produce first data to the modulation
The input of unit, the wherein initial data include the bit of the first logical value and the bit of the second logical value, first number
According to the bit including first logical value and the bit of second logical value, the bit of first logical value needs to carry out the bit
Write operation, the bit of second logical value need not carry out the bit write operation, first logical value of first data
Amount of bits be less than the initial data in first logical value amount of bits, and first data first logical value
Bit number first logic of the initial data is same as with the total number of bits that the bit number of second logical value is added
The total number of bits that the bit number of value is added with the bit number of second logical value.
14. data processing equipment according to claim 13, it is characterised in that the modular converter includes：
One filter element, couples the first end of the modular converter to receive the clock signal, the filter element filters the clock
A noise in signal；And
One sampling unit, couples one second end of the modular converter to receive a data-signal, the sampling unit couples the filtering
Unit filters the clock signal after the noise to receive, and the wherein sampling unit samples this according to the sequential of the clock signal
Data-signal, to obtain and determine the logical value of first data.
15. data processing equipment according to claim 13, it is characterised in that the modular converter includes：
One filter element, couples the first end of the modular converter to receive the clock signal, the filter element filters the clock
A noise in signal；And
One demodulation unit, couples the filter element to receive and filters the clock signal after the noise, wherein when the filtering
When the time span in the correspondence cycle of the clock signal after the noise is more than a reference value, the demodulation unit is produced simultaneously
The bit value for determining first data is one first logical value, the correspondence of clock signal after described filtering noise
When the time span in cycle is less than the reference value, the demodulation unit produces and determined that the bit value of first data is one
Second logical value.
16. data processing equipment according to claim 13, it is characterised in that the control module counts a stand-by period,
To wait the completion of the bit write operation；When the bit value of first data is first logical value, the control module
Waiting time is not reseted before waiting time reaches the time rating of the bit write operation, to enter to the bit value
The row bit write operation；And when the bit value of first data is second logical value, the control module is not to this
Bit value carries out the bit write operation and reseted waiting time, to handle next bit value.
17. data processing equipment according to claim 13, it is characterised in that the arithmetic element includes a NOT gate, one different
OR gate and a biconditional gate wherein at least one, to carry out the reversible logic computing.
18. data processing equipment according to claim 17, it is characterised in that the arithmetic element provides a computing key,
And the XOR gate carries out an XOR computing to the initial data and the computing key, to produce first data.
19. data processing equipment according to claim 17, it is characterised in that if needing to carry out the ratio in the initial data
The amount of bits of special write operation refers to quantity more than one, then the initial data is carried out into an inverted logic computing, is somebody's turn to do with producing
First data.
20. data processing equipment according to claim 13, it is characterised in that also include：
One processor, is coupled to the memory to read first data, and carries out the reversible logic computing to first data,
Using by first data convert as the initial data.
21. data processing equipment according to claim 13, it is characterised in that the initial data is an encryption and decryption key.
22. data processing equipment according to claim 21, it is characterised in that the encryption and decryption key includes a high frequency range number
Word content protecting key.
23. data processing equipment according to claim 13, it is characterised in that first data are an encryption and decryption key.
24. data processing equipment according to claim 23, it is characterised in that the encryption and decryption key includes a high frequency range
Digital content protection key.
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|---|---|---|---|
| CN201310344081.2A CN104347101B (en) | 2013-08-08 | 2013-08-08 | Data processing method and device |
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|---|---|---|---|
| CN201310344081.2A CN104347101B (en) | 2013-08-08 | 2013-08-08 | Data processing method and device |
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| CN104347101A CN104347101A (en) | 2015-02-11 |
| CN104347101B true CN104347101B (en) | 2017-10-27 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1279854A (en) * | 1997-10-01 | 2001-01-10 | 罗斯蒙德公司 | FSK demodulator using a super linear integrator |
| CN1592287A (en) * | 2003-09-02 | 2005-03-09 | 三洋电机株式会社 | FSK signal demodulating circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4055103B2 (en) * | 2000-10-02 | 2008-03-05 | 株式会社ルネサステクノロジ | Nonvolatile memory, semiconductor integrated circuit incorporating the same, and method of writing nonvolatile memory |
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2013
- 2013-08-08 CN CN201310344081.2A patent/CN104347101B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1279854A (en) * | 1997-10-01 | 2001-01-10 | 罗斯蒙德公司 | FSK demodulator using a super linear integrator |
| CN1592287A (en) * | 2003-09-02 | 2005-03-09 | 三洋电机株式会社 | FSK signal demodulating circuit |
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| CN104347101A (en) | 2015-02-11 |
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