CN104346243A - System for automatic adjustment of main board testing process and implement method thereof - Google Patents
System for automatic adjustment of main board testing process and implement method thereof Download PDFInfo
- Publication number
- CN104346243A CN104346243A CN201310323438.9A CN201310323438A CN104346243A CN 104346243 A CN104346243 A CN 104346243A CN 201310323438 A CN201310323438 A CN 201310323438A CN 104346243 A CN104346243 A CN 104346243A
- Authority
- CN
- China
- Prior art keywords
- test
- measured
- testing
- individual event
- testing process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a system for automatic adjustment of a main board testing process and an implement method thereof. The testing process is adjusted according to a failure rate of various testing. The implement method of the system for the automatic adjustment of the main board testing process comprises recognizing a to-be-tested single item which a main board needs to test through a recognizing module; reading a testing failure rate of the to-be-tested single item from a database through a reading module; arranging the to-be-tested single items according to testing failure rate from high to low through an adjusting module to form a new testing procedure; testing all the to-be-tested single items according to the new testing procedure by means of a testing tool through the testing module to obtain testing results; storing testing results of the to-be-tested single items into the database through a storing module.
Description
[Ji Intraoperative field]
The present invention relates to a kind of system and method thereof of automatic adjustment mainboard testing process.
[Bei Jing Ji Intraoperative]
In mainboard test, be according to personal experience to arrange the sequencing of different test item at present, and there are some difference the test duration of test item in different mainboard, the situation of test crash is also not quite similar.There are some test item test durations long, also some test items are had due to the easy test crash of a variety of causes, if some easy failed test items are placed on after the low test item of test failure rates, or the test item short test duration is placed on after test duration long test item, often need long event could find the test item of these test crashs, can cause like this finding that the efficiency of hardware deficiency or inspection software mistake is not high in the mainboard development phase, also can cause in mainboard test phase test duration when test failure rates is high long, testing efficiency is not high.
[summary of the invention]
Therefore, object of the present invention is mainly to provide one to overcome above-mentioned technological deficiency, and the height according to test failure rates carries out self-adjusting system and its implementation to the testing process of mainboard.
For achieving the above object, the invention provides a kind of system of automatic adjustment mainboard testing process, this system is made up of identification module, read module, adjusting module, test module and preservation module, and wherein, identification module is for identifying the individual event to be measured that mainboard is tested; Read module is used for the test failure rates of this individual event to be measured of reading test from database; Adjusting module is used for this individual event to be measured to arrange according to test failure rates testing sequence from high to low, forms new testing process; This individual events to be measured all utilize testing tool to test according to new testing process by test module, obtain test result; Preserve module by the test result of this individual event to be measured each stored in database.
The present invention also provides a kind of method of automatic adjustment mainboard testing process, and the method comprises: the individual event to be measured identifying the required test of mainboard; According to identified individual event to be measured, read should the test failure rates of individual event to be measured from database; By each individual event to be measured according to test failure rates testing sequence arrangement from high to low, form new testing process; Utilize testing tool to test according to new testing process this individual events to be measured all, obtain test result; By the test result of this individual event to be measured each stored in database.
Especially, described individual event to be measured comprises CPU, internal memory, hard disk, CD-ROM drive, South Bridge chip group, north bridge chipset, pci bus.
Compared to prior art, the system of automatic adjustment mainboard testing process of the present invention and its implementation, failure rate according to every test adjusts testing process, the test item that preferential test failure rates is high, avoid finding in the mainboard development phase drawback that the efficiency of hardware deficiency or inspection software mistake is not high, improve the efficiency of test.
[accompanying drawing explanation]
Fig. 1 is the connection block diagram that the present invention adjusts the system of mainboard testing process automatically;
Fig. 2 is the process flow diagram that the present invention adjusts the method for mainboard testing process automatically;
Fig. 3 is that the present invention adjusts illustrating of the method for mainboard testing process automatically.
[embodiment]
Below, by reference to the accompanying drawings, specific embodiments of the invention are elaborated:
The invention provides system and its implementation of a kind of automatic adjustment mainboard testing process, failure rate according to every test adjusts testing process, preferential test failure rates height test item, improve testing efficiency, refer to Fig. 1, for the present invention adjusts the connection block diagram of the system of mainboard testing process automatically, as shown in the figure, the system 1 of described automatic adjustment mainboard testing process is by identification module 11, read module 12, adjusting module 13, test module 14 and preservation module 15 form, wherein, described identification module 11 is for identifying the individual event to be measured that mainboard is tested, read module 12 for reading the test failure rates of this individual event to be measured of test from database, adjusting module 13 is for forming new testing process by this individual event to be measured according to test failure rates testing sequence arrangement from high to low, this individual events to be measured all utilize testing tool to test according to new testing process by test module 14, obtain test result, preserve module 15 by the test result of this individual event to be measured each stored in database.
Refer to Fig. 2, automatically adjust the process flow diagram of the method for mainboard testing process for the present invention, as shown in the figure, the method comprises the following steps:
Step 21: the individual event to be measured identifying the required test of mainboard;
Step 22: according to identified individual event to be measured, read the test failure rates of individual event to be measured from database;
Step 23: the testing sequence adjusting individual event to be measured, by individual event to be measured according to test failure rates testing sequence arrangement from high to low, forms new testing process;
Step 24: utilize testing tool to test according to new testing process this individual events to be measured all, obtain test result;
Step 25: by the test result of this individual event to be measured each stored in database;
Step 26: be confirmed whether next mainboard to be measured, if having, then proceeds to step 21 and re-starts test, if not, then terminates test.
In the present embodiment, described test result comprises the test duration and situation is passed through in test, test duration is the mean test time of individual event to be measured, namely test duration=summation/total testing time of each test duration, the test of each individual event to be measured comprise by with not by two kinds of situations, therefore to test by situation by testing number of pass times, test failure number of times forms, test does not add 1 by then test failure number of times, tests and adds 1 by then testing number of pass times.
In the present embodiment, described test failure rates is calculated by situation accumulation by testing, i.e. test failure rates=test failure number of times/total testing time, wherein total testing time=test failure number of times+test number of pass times, after this individual event to be measured completes test, upgrade the test failure rates of this individual event to be measured in described database, and read the test failure rates of this individual event to be measured when next time tests.
In the present embodiment, if the testing sequence of this individual event to be measured can not adjust, then fix this testing sequence, and the individual event to be measured of adjustable testing sequence is inserted in this testing sequence from high to low one by one according to failure rate, form new testing process.
In the present embodiment, described individual event to be measured comprises CPU, internal memory, hard disk, CD-ROM drive, South Bridge chip group, north bridge chipset, pci bus.
Refer to Fig. 3, for the present invention adjusts illustrating of the method for mainboard testing process automatically, as shown in the figure, with each individual event A, B, C, D, E to be measured for a line, test duration of each individual event to be measured, testing attribute, failure rate, former testing sequence and new testing sequence are for lising, wherein new testing sequence is on the basis of former testing sequence, rearranges form according to testing attribute and failure rate.For five individual event A, B, C, D, E to be measured in scheming, wherein A, E can not adjust order, and B, C, D are adjustable test individual event, according to the flow process of the method for above-mentioned automatic adjustment mainboard testing process, the testing sequence of fixing A, E is still 1 and 5, B, C, D are arranged as C, D, E from high to low according to failure rate, insert in A, E one by one, then new testing sequence is A, C, D, B, E.Thus can see, because the failure rate of individual event C to be measured is higher, if conveniently testing sequence, need 16 minutes ability to find fault, and according to new testing sequence, only need just can find fault in 11 minutes.
By reference to the accompanying drawings the specific embodiment of the present invention and embodiment are elaborated above, but the present invention is not limited to the above-described embodiment and examples, in the ken that those skilled in the art possess, can also make a variety of changes without departing from the inventive concept of the premise.
Claims (10)
1. automatically adjust a system for mainboard testing process, it is characterized in that, this system comprises:
Identification module, for identifying the individual event to be measured that mainboard is tested;
Read module, for reading the test failure rates of this individual event to be measured from database;
Adjusting module, by each individual event to be measured according to test failure rates testing sequence arrangement from high to low, forms new testing process;
Test module, utilizes testing tool to test according to new testing process this individual events to be measured all, obtains test result;
Preserve module, by the test result of this individual event to be measured each stored in database.
2. the system of automatic adjustment mainboard testing process according to claim 1, it is characterized in that, described test result comprises the test duration and situation is passed through in test.
3. the system of automatic adjustment mainboard testing process according to claim 1 and 2, it is characterized in that, described test failure rates is calculated by situation by testing, after this individual event to be measured completes test, upgrade the test failure rates of this individual event to be measured in described database, and read this test failure rates when next time tests.
4. the system of automatic adjustment mainboard testing process according to claim 1, it is characterized in that, if the testing sequence of this individual event to be measured can not adjust, then fix this testing sequence, and the individual event to be measured of adjustable testing sequence is inserted in this testing sequence one by one according to failure rate arrangement from high to low, form new testing process.
5. the system of automatic adjustment mainboard testing process according to claim 1, it is characterized in that, described individual event to be measured comprises CPU, internal memory, hard disk, CD-ROM drive, South Bridge chip group, north bridge chipset, pci bus.
6. automatically adjust a method for mainboard testing process, be applicable to the system of above-mentioned automatic adjustment mainboard testing process, it is characterized in that, the method comprises the following steps:
Identify the individual event to be measured of the required test of mainboard;
According to identified individual event to be measured, read should individual event test failure rates to be measured from database;
By each individual event to be measured according to test failure rates testing sequence arrangement from high to low, form new testing process;
Utilize testing tool to test according to new testing process this individual events to be measured all, obtain test result;
By the test result of this individual event to be measured each stored in database.
7. the method for automatic adjustment mainboard testing process according to claim 6, it is characterized in that, described test result comprises the test duration and situation is passed through in test.
8. the method for the automatic adjustment mainboard testing process according to claim 6 or 7, it is characterized in that, described test failure rates is calculated by situation by testing, after this individual event to be measured completes test, upgrade the test failure rates of this individual event to be measured in described database, and read this test failure rates when next time tests.
9. the method for automatic adjustment mainboard testing process according to claim 6, it is characterized in that, if the testing sequence of this individual event to be measured can not adjust, then fix this testing sequence, and the individual event to be measured of adjustable testing sequence is inserted in this testing sequence one by one according to failure rate arrangement from high to low, form new testing process.
10. the method for automatic adjustment mainboard testing process according to claim 6, it is characterized in that, described individual event to be measured comprises CPU, internal memory, hard disk, CD-ROM drive, South Bridge chip group, north bridge chipset, pci bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310323438.9A CN104346243A (en) | 2013-07-30 | 2013-07-30 | System for automatic adjustment of main board testing process and implement method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310323438.9A CN104346243A (en) | 2013-07-30 | 2013-07-30 | System for automatic adjustment of main board testing process and implement method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104346243A true CN104346243A (en) | 2015-02-11 |
Family
ID=52501919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310323438.9A Withdrawn CN104346243A (en) | 2013-07-30 | 2013-07-30 | System for automatic adjustment of main board testing process and implement method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104346243A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105759785A (en) * | 2016-02-16 | 2016-07-13 | 珠海格力电器股份有限公司 | Control method and device of test equipment |
| CN106603789A (en) * | 2016-12-12 | 2017-04-26 | 青岛海信移动通信技术股份有限公司 | Method and system to increase equipment testing efficiency |
| CN108627195A (en) * | 2018-08-17 | 2018-10-09 | 深圳市金邦科技发展有限公司 | A kind of intelligent detecting method and intelligent checking system that memory body module is detected |
| CN109992493A (en) * | 2017-12-29 | 2019-07-09 | 宁波方太厨具有限公司 | A kind of test method excluding gas heater software anomaly |
| CN113268290A (en) * | 2021-06-16 | 2021-08-17 | 中移（杭州）信息技术有限公司 | Software container optimization method, device, equipment and computer program product |
| CN114113987A (en) * | 2022-01-24 | 2022-03-01 | 中大检测(湖南)股份有限公司 | Chip inspection tracking method and system |
-
2013
- 2013-07-30 CN CN201310323438.9A patent/CN104346243A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105759785A (en) * | 2016-02-16 | 2016-07-13 | 珠海格力电器股份有限公司 | Control method and device of test equipment |
| CN106603789A (en) * | 2016-12-12 | 2017-04-26 | 青岛海信移动通信技术股份有限公司 | Method and system to increase equipment testing efficiency |
| CN109992493A (en) * | 2017-12-29 | 2019-07-09 | 宁波方太厨具有限公司 | A kind of test method excluding gas heater software anomaly |
| CN108627195A (en) * | 2018-08-17 | 2018-10-09 | 深圳市金邦科技发展有限公司 | A kind of intelligent detecting method and intelligent checking system that memory body module is detected |
| CN113268290A (en) * | 2021-06-16 | 2021-08-17 | 中移（杭州）信息技术有限公司 | Software container optimization method, device, equipment and computer program product |
| CN114113987A (en) * | 2022-01-24 | 2022-03-01 | 中大检测(湖南)股份有限公司 | Chip inspection tracking method and system |
| CN114113987B (en) * | 2022-01-24 | 2022-04-12 | 中大检测(湖南)股份有限公司 | Chip inspection tracking method and system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104346243A (en) | System for automatic adjustment of main board testing process and implement method thereof | |
| CN103488544B (en) | Detect the treating method and apparatus of slow dish | |
| US9389956B2 (en) | Implementing ECC control for enhanced endurance and data retention of flash memories | |
| CN108694123B (en) | Regression testing method, computer readable storage medium and terminal equipment | |
| CN102354292A (en) | Method and system for checking consistency of records in master and backup databases | |
| CN105511993A (en) | UEFI (unified extensible firmware interface) -based server NVME (network video management entity) hard disk backplane function test method | |
| CN103778050B (en) | A kind of database server High Availabitity performance detecting system | |
| US20120331345A1 (en) | Memory testing system and method of computing device | |
| CN109597763A (en) | A kind of consistency verification method and device that multinomial data are normalized | |
| CN104123212B (en) | The system detection method of USB chips | |
| US20130032633A1 (en) | Chip test system | |
| CN103425580A (en) | Method for automatically and rapidly obtaining and calibrating configuration information of cloud computing device | |
| WO2009086020A3 (en) | Method and apparatus for managing test result data generated by a semiconductor test system | |
| CN104575615A (en) | Device and method for built-in self-test memory | |
| EP3866050A1 (en) | Conversion method, conversion device, and conversion program | |
| CN105528269A (en) | Design method for detecting disorder of hard disks based on Itanium platform | |
| CN105159834A (en) | Software dynamic testing operating data extracting method | |
| CN107957677B (en) | Time equipment time calibration method of vehicle-mounted equipment | |
| US7404121B2 (en) | Method and machine-readable media for inferring relationships between test results | |
| CN105243000A (en) | Cross-numa memory testing method suitable for multi-path server | |
| US20130013962A1 (en) | Computing device and method for analyzing integrality of serial attached scsi signals | |
| BR112018073773A2 (en) | method for determining set of precoding matrices and transmission apparatus | |
| CN106961600B (en) | Set-top box demultiplexer method for testing pressure and system | |
| US9092315B2 (en) | Method and software program product for determining the quality of an information technology system | |
| US20090322376A1 (en) | Smi memory read data capture margin characterization circuits and methods |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C04 | Withdrawal of patent application after publication (patent law 2001) | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20150211 |