CN1043398C - Satellite receiving, dual HF T.V, picture-in-picture telecontrol and digital tuning system - Google Patents
Satellite receiving, dual HF T.V, picture-in-picture telecontrol and digital tuning system Download PDFInfo
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- CN1043398C CN1043398C CN93114642A CN93114642A CN1043398C CN 1043398 C CN1043398 C CN 1043398C CN 93114642 A CN93114642 A CN 93114642A CN 93114642 A CN93114642 A CN 93114642A CN 1043398 C CN1043398 C CN 1043398C
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Abstract
The present invention provides a remote control and digital tuning system of satellite reception, double high frequency television and picture in picture, which comprises a main controller controlled by a single-chip computer with frequency synthesis and voltage synthesis digital tuning video frequency PIP, a control signal recognizing circuit, a main controller initialization control circuit, a complete television power supply hold control circuit, a power supply electrifying position reset control circuit, an external storage data saving control circuit, a translation circuit of frequency synthesis digital tuning F.S1 (PLL1) /F. S2 (PLL2), an accompanying sound subcarrier tuning control circuit received by BS, an AV signal selection switching circuit. The present invention realizes the remote control and the digital tuning of BS reception, double high frequency television and picture in picture by using only one set of single-chip microcomputer control system and a remote controller.
Description
The present invention relates to a kind of remote control and tuner of television receiver.
Broadcasting satellite (has the BS of employing to represent among this paper and the figure, down together) reception enters family rapidly, the additional color television set that picture-in-picture (have the PIP of employing to represent among this paper and the figure, down with) function arranged all can be realized independent assortment main, sprite to any one signal source of ground television broadcasting, broadcasting satellite TV and the external video input 1,2 of VHF and UHF; Can search for other signal source except that key frame, to know relevant image information; The sound accompaniment of available headphone monitor sprite.
Existing pair of high frequency picture-in-picture colour TV, signal promptly main, sprite all can be made high-frequency tuning and be controlled by same remote control system, but the equal more complicated of its control system.
The C31-CBX1 type of HIT, C29-CBX1 type color television set are with satellite television receiver, the control of its system comprises the single-chip microprocessor of control common colour TV and as the single-chip microprocessor of the control satellite television broadcasting receiver of subordinate, promptly adopts two to overlap microcomputer remote control/digital tuning systems.
The VC-BS770/VC-BS570 type color television set of Japan NEC Corporation also is to adopt two microcomputers to realize broadcasting satellite is received and the remote control channel selection of ground TV broadcast reception and the switching of PIP function.And VC-BS550/VC-BS1000 type VCR adopts a slice microcomputer that the 2nd frequency converter of the intermediate frequency of broadcasting satellite is carried out the frequency synthesis digital tuning, and controls with the system of another sheet microcomputer as PIP etc.
New TV " picture king " series: TH-27VS10 (27 inches), TH-29VS10 type (29 inches), TH-43VS10 type two microcomputers of usefulness such as (43 inches) of receiving with satellite of Japanese Matsushita Electric Industrial company carry out remote control and digital tuning to TV tuner and broadcasting satellite receiver, and do not have the PIP function.
KV-34FX2, KV-31FX2, the KV-29FX2 type color television set with broadcasting satellite receiver and PIP function of Sony corporation of Japan can make television program, vision signal and broadcasting satellite receive and all can be presented on the sprite, and the signal of mother and sons' picture can switch mutually.Two microcomputers are used in the remote control of its complete machine, channel selection and system's control, the microcomputerized controller that a slice receives as broadcasting satellite, and another sheet is artificial intelligence (AI) microcomputer, controls as the digital tuning of TV and the system of PIP.
Toshiba Corp adopts the directly remote control mode of switching of broadcasting satellite receiving channels and video input with the up-to-date color television set of 29BS95 type of PIP and broadcasting satellite reception, usually can append 8 broadcasting satellite channels on the television channel, realize the fully directly remote control of 20 channel positions, an available button carries out channel selection, and the button that the video input is selected also is independently.The digital tuning that the 2nd frequency converter that adopts single chip microcomputer TMP47C1638N to realize that tuner and broadcasting satellite to television set receive carries out remote control and frequency synthesis simultaneously.
Above-mentioned control system costs an arm and a leg owing to adopt two cpu modes, does not reach the market effect of expection.
The object of the present invention is to provide the multifunction remote-control and the digital tuning system that adopt a slice single-chip microprocessor to realize broadcasting satellite reception, double high-frequency head TV and picture-in-picture, it has following function: remote control and the digital tuning of realizing broadcasting satellite reception, double high-frequency head television broadcasting reception, picture-in-picture; Only need with a remote controller, can realize the function (for example 3 cover systems of colour TV, video tape recorder and satellite receiver) of former need 3 cover remote control systems and 3 cover remote controllers; Can realize the interfacing of modularization and home-made model colour TV receiver, constitute Multifunction colour TV receiver etc.
The present invention includes single chip microcomputer master controller with frequency synthesis and the synthetic digital tuning video PIP control of voltage, the control signal identification circuit, the master controller initialization control circuit, complete machine power supply retentive control circuit, power connection is put reset control circuit, outer deposit data retentive control circuit, first frequency synthetizing digital tuning (adopts PLL1 to represent among this paper and the figure, down with) and the conversion control circuit of second cover (adopting PLL2 to represent among this paper and the figure, down together) frequency synthesis digital tuning, the sound subcarrier tuner control circuit that broadcasting satellite receives and the selection control switching circuit of AV signal.
The control signal identification circuit comprises two differential circuits and NAND gate.Two differential circuits are connected with the quiet frame pin of sprite with the sprite display switch of the picture-in-picture of master controller respectively, the control signal that the output of differential circuit is exported after NAND gate is sent the master controller initialization control circuit, the differential circuit that input is connected with the sprite display switch pin of the PIP of master controller, the input of the conversion control circuit of first cover and second frequency synthetizing digital tuning is also delivered in its output.
The master controller initialization control circuit comprises inverter, flip-flop circuit, the bidirectional analog switches set, monostable multivibrator, NAND gate, integral delay circuit, the input of inverter and monostable multivibrator are connected with the output of control signal identification circuit respectively, the output one tunnel of inverter is successively through integral delay circuit, deliver to the bidirectional analog switch after the NAND gate, the bidirectional analog switch also is connected with the main power source pin of master controller, another road input of NAND gate is provided by the output of monostable multivibrator, another bidirectional analog switch is arrived again through flip-flop circuit in another road of inverter output, and this bidirectional analog switch is connected with the switch of remote control/digital tuning system plate in addition.The output of monostable multivibrator also is connected with outer deposit data retentive control circuit with complete machine power supply retentive control circuit respectively.
Complete machine power supply retentive control circuit comprises bidirectional analog switch, adder, rectifying and wave-filtering and complete machine power control circuit, the bidirectional analog switch is connected with " key scanning goes out " pin with the output of the monostable multivibrator of master controller initialization control circuit and " key scanning is gone into " of master controller respectively, and the input of adder is connected with the output of the monostable multivibrator of master controller initialization control circuit and the mains switch control pin of master controller respectively.
Power connection is put reset control circuit and is comprised power connection setting circuit, bidirectional analog switches set, RC charge delay circuit, NAND gate and monostable multivibrator, and the switch ends of remote control/digital tuning system plate is sent in the output that power connection is put reset circuit behind the bidirectional analog switch by monostable trigger-action circuit.The output of RC charging delay circuit inserts the power connection holding circuit according to this with+5V power supply behind NAND gate, bidirectional analog switch, monostable multivibrator, said power connection holding circuit is meant that above-mentioned keyboard power connects control circuit, outer deposit data retentive control circuit and complete machine power supply retentive control circuit.
Outer deposit data retentive control circuit comprises inverter, bidirectional analog switch and E
2PROM (Electrically Erasable Read Only Memory), the signal that comes autonomous controller initialization control circuit monostable multivibrator by inverter behind the bidirectional analog switch with E
2Sheet choosing (CS) end of PROM connects; The chip enable of E2PROM (CE) end and master controller E
2The control end of writing of PROM connects E
2The serial clock of PROM (SCL) end, serial data (SDA) end with master controller E
2The communication of PROM is connected with the communication ends of frequency synthesis digital tuning phase-locked loop.The bidirectional analog switch also with the E of master controller
2PROM writes control end and connects.
The conversion control circuit of first cover and second frequency synthetizing digital tuning comprises two-way inverter, emitter follower and bidirectional analog switches set, wherein 1 inverter is delivered in the differential circuit output of the PIP sprite display switch signal of control signal identification circuit, the output one tunnel of inverter is delivered to the keyed end and the remote control/digital tuning system plate of phase-locked loop of phase-locked loop, the master controller of described first frequency synthetizing digital tuning respectively after emitter follower is delivered to 3 bidirectional analog switches respectively.The keyed end and the remote control/digital tuning system plate of phase-locked loop of phase-locked loop, the master controller of described second frequency synthetizing digital tuning delivered in another road output of inverter successively respectively after another inverter, emitter follower also send 3 bidirectional analog switches respectively.
Also be connected with the bidirectional analog switch that the described first frequency synthetizing digital tuning phase-locked loop is connected with the described second frequency synthetizing digital tuning phase-locked loop respectively with the phase-locked loop Enable Pin of master controller;
The sound subcarrier tuner control circuit that broadcasting satellite receives comprises stabilized voltage power supply, broadcasting satellite sound subcarrier tuning voltage initialization circuit, 8 tunnels analogy switches, 4D latch, input control circuit, level-conversion circuit and decoder.The CP end and the D of 4D latch
0-D
2End is connected with master controller NTSC/PAL/SECAM television system switching signal end with the flip-flop circuit Q signal output of master controller initialization control circuit respectively, and the output one tunnel of 4D latch is sent the broadcasting satellite dash receiver successively behind input control circuit, level-conversion circuit, decoder and 8 tunnels analogy switches; Television set television system change-over circuit is sent on another road, and 8 channel data inputs of 8 tunnels analogy switches also are connected with broadcasting satellite sound subcarrier tuning voltage initialization circuit.
The selection control switching circuit of audio frequency and video (AV) signal comprises 4 groups of buffering input stages, 2 lines-4 line decoder and 8 analog switches compositions, 1st, 2 groups of buffering input stages are connected with the PIP sprite display switch end of master controller and the flip-flop circuit Q signal output of master controller initialization control circuit respectively, and the output of buffering input stage is delivered to analog switch respectively respectively behind the 1st, 2 group of 2 lines-line decoder.1st, the input of 2 groups of analog switches is connected with video, the audio signal of broadcasting satellite, double high-frequency head respectively, 1st, the video of the broadcasting satellite of 2 groups of analog switches output and tuner key frame, audio signal with deliver to the 3rd group of analog switch and export main screen video, audio signal without the broadcasting satellite vision signal of the 1st group of analog switch and external vision signal (adopt VTR to represent among this paper and the figure, down with).The input of the 3rd group of buffering input stage is connected with the selecting side, main screen signal source of master controller, and output signal is imported the 3rd group of analog switch behind 2 lines-4 line decoder.Video, audio signal and the external audio frequency signal of the broadcasting satellite vision signal of the 1st group of analog switch output and broadcasting satellite, double high-frequency head are delivered to the 4th group of analog switch and are exported sprite video and audio signal.The 4th group of buffering input stage is connected with the signal source selecting side of sprite master controller, and output signal is imported the 4th group of analog switch behind 2 lines-4 line decoder.
The present invention compares with remote control, the digital tuning system of existing multifunctional colour television set, has following outstanding substantive distinguishing features and significant technological progress.
The present invention utilized an one chip microcomputer do controller promptly form one the cover remote control/digital tuning system, the television broadcasting reception of double high-frequency head and picture-in-picture with phase-locked loop frequency synthesis digital tuning, remote control, are received electricity consumption to broadcasting satellite and are pressed into digital tuning, remote control.And existing technology only can realize digital tuning, remote control to the television broadcasting reception of single tuner and the reception of broadcasting satellite, and all uses two cover remote controls, the digital tuning system of two single-chip microprocessors usually, costs an arm and a leg, and does not reach the market effect of expection.
3 high-frequency TV signals of the cover TV programme that the present invention can receive the two cover TV programme and the broadcasting satellite of ground TV broadcast are simultaneously controlled, only need a remote controller, needing at least in the prior art can realize 2 cover remote control system and 2 functions that remote controller could be realized.Can realize also simultaneously that the control to PIP is that mother and sons' picture switches; The combination of multiple signal source is switched; The screen size of sprite is switched; The switching of sprite position, picture activity and quiet frame control etc.
The present invention adopts with 4 microcomputers of μ PD17053 monolithic supporting, shows at screen that so have Chinese full system type pictorial is selected, analog quantity expansion, two sound accompaniments, stereo, surround sound, advanced controlled function such as external AV interface.
System of the present invention can realize modularization, and realizes interface with the colour TV of existing home-made model, thereby realizes the update of high-grade multi-functional colour TV, and cost is low, and technical value added is higher.
Fig. 1 is a composition block diagram of the present invention.
Fig. 2 is that retentive control circuit, the power connection of the initialization control of control signal identification circuit, single-chip microprocessor μ PD17053-MAF controller and television set complete machine power supply put the conversion control circuit schematic diagram that reset control circuit, outer deposit data are preserved control circuit, described first cover and second frequency synthetizing digital tuning.
The sound subcarrier tuner control circuit schematic diagram that Fig. 3 receives for broadcasting satellite.
Fig. 4 is that audio frequency, video (AV) signal are selected the control switching circuit schematic diagram.
Fig. 5 is that the square of IC4052 is formed and corresponding pin.
Below with reference to accompanying drawing the present invention is done detailed explanation.
As shown in Figure 1, the remote control of satellite reception of the present invention, two high-frequency TV, picture-in-picture and digital tuning system adopt with frequency synthesis and voltage and synthesize μ PD17053 type monolithic 4 bit micro-computers of digital tuning video PIP control as master controller (1).
The control signal identification circuit is to utilize the output signal of the sprite display switch of picture-in-picture of master controller and the quiet frame end of sprite to carry out signal identification to handle, the logic control that is achieved as follows: the initialization of master controller is differentiated, television set complete machine power supply keeps, outer deposit data keeps, the conversion of frequency synthesis and voltage synthetic state, the generation of the selection switching signal of Voice ﹠ Video signal etc.The signal of the sprite display switch of the PIP of master controller and the quiet frame end of sprite exports NAND gate (4) to through differential circuit (2,3) respectively.The input of the conversion control circuit (19) of described first cover and second frequency synthetizing digital tuning is also delivered in the output of differential circuit (2).The output control signal of NAND gate (4) is sent the inverter (5) and the monostable multivibrator (10) of master controller initialization control circuit.Referring to Fig. 2,2 inputs, 4 NAND gate IC
1Sprite display switch (on) signal (through differential circuit) [annotate: " on " signal of representing in each chart in this explanation all refers to this signal] of 4011 pin 1 input PIP, the quiet frame signal of sprite (also through differential circuit) of pin 2 input PIP, then NAND gate output (pin 3) Q=A
*B=(sprite display switch)
*The control signal of (the quiet frame of sprite) [annotate: " Q " signal of representing in this explanation and each chart all refers to this signal].If the sprite display switch signal of PIP is high level " H " (being that the sprite display switch is connected, with " on " expression), the quiet frame signal of the sprite of PIP also for high level " H " (being the quiet frame of sprite), then is output as low level " L ".When sprite display switch signal is " off ", when promptly not having the quiet frame of PIP, i.e. the conversion of the synthetic digital tuning state of the harmonious voltage of the controllable frequency composite number tone of Chinese characters; When sprite display switch signal was " on ", when promptly PIP being arranged, the quiet frame signal of sprite display switch signal and sprite worked separately, thereby realizes that a key is dual-purpose, does not realize multi-functional control so can not increase teleswitch.When the quiet frame signal of sprite was high level (" H ") static state, chip enable end CE became " L " level, then loses PIP.When the CE end rises to " H " level, then be in the PIP state.
In the initialization control circuit of master controller, the input of inverter (5) and monostable multivibrator (10) are connected with NAND gate (4) the output control signal of control signal identification circuit respectively, the output one tunnel of inverter (5) is sent bidirectional analog switch (12) successively after integral delay circuit (9), NAND gate (11), bidirectional analog switch (12) also is connected with main power source (CE) pin of master controller (1).Another road of NAND gate (11) is input as the output signal of monostable multivibrator (10).Another bidirectional analog switch (7) is arrived again through flip-flop circuit (6) in another road of inverter (5) output, and this bidirectional analog switch is connected with the switch (8) of remote control/digital tuning system plate in addition.The output of monostable multivibrator also is connected with the inverter (17) that the bidirectional analog switch (14) of complete machine power supply retentive control circuit, adder (13) and outer deposit data are preserved control circuit respectively.
For master controller initial setting diode be, when frequency synthesis/voltage synthetic state is changed setting (representing with PLL/VS among the figure) for " 0 ", it then is the voltage synthetic state, when it is " 1 ", then be the frequency synthesis state, when picture-in-picture state is set at " 0 ", then do not have the PIP function, when it is " 1 ", then for the PIP function is arranged.The CE pin of master controller is the Enable Pin of chip, i.e. the input of chip select signal.As CE=" H ", during high level, just start this chip, on the contrary CE=" L ", during low level, then this chip is not worked, and the field of described frequency synthesis digital tuning output simultaneously and the output of each data also all are under an embargo and do not work.When CE=" L ", as a CKSTP instruction in the executive program, then clock internal generator and CPU quit work, and memory enters hold mode.When the level of CE during by " L " → " H ", chip will reset, and program will begin to carry out from zero-address.Except that the level variation by the CE pin resets, when power connection or by the power failure measuring ability, all can realize resetting, initialized result makes program begin to carry out from zero-address.
Referring to Fig. 2, work as IC
2When 4011 pin 1,2 was " H " simultaneously, pin 3 was output as " L ", because the V of pin 6
DD=+5V, constant is " H " level, so pin 4 is output as " H " level, it is added to IC
2The pin 3CP of 4027 pairs of JK flip-flop
2End promptly when the quiet frame of PIP, makes IC
2Set, thus make IC
2Pin 1Q
2Output level by " H " → " L ", its output is added to IC
4The pin 5 of 4066 bidirectional analog switches is realized the control of break-make, when disconnecting, switches to the synthetic digital tuning state of voltage; When connecting, switch to frequency synthesis digital tuning state, and use the JK flip-flop hold mode.
Advanced line frequency is synthetic/switching of the synthetic digital tuning of voltage, and the back is confirmed with the variation of master controller CE end level.When PIP sprite display switch was connected (on) and quiet frame, " L " level of pin 3 outputs of IC1 was added to IC
3555 pin 2 through the RC charging, makes IC
3Pin 3 output " H " high level.With IC
3The signal of pin 3 outputs is added to IC
1Pin 9, IC at this moment
1Pin 4 also export " H " level, through R
4C
4Integration is added to IC after postponing
1 Pin 8 because pin 9,8 is " H " level, then pin 10 output " L " level signals are added to IC
44066 pin 6 makes IC
4Pin 8,9 disconnect, thereby cause the pin 13CE of master controller to hold instantaneous dead electricity.Because main power source pin 13 instantaneous dead electricity, make IC
1The output switching activity of pin 3, restPose.But voltage at this moment is synthetic/and frequency synthesis digital tuning state maintains the original state constantly by two JK flip-flop, therefore can realize the chip initiation logic control that two states switches.
Complete machine power supply retentive control circuit comprises bidirectional analog switch (14), adder (13), rectifying and wave-filtering and complete machine power control circuit (15).The bidirectional analog switch is connected with " key scanning goes out " (52 pin) with the output of the monostable multivibrator (10) of master controller initialization control circuit and " key scanning is gone into " (59 pin) of master controller respectively.The input of adder (13) is connected with the output of the monostable multivibrator (10) of master controller initialization control circuit and the mains switch control pin (21 pin) of master controller respectively.
Complete machine power control terminal Power is the pin 21 of master controller, and when power remove, pin 21 is output as " L " low level, there is not picture on the screen, when the main power source CE of master controller pin 13 end is " L " low level, also cause pin 21 dead electricity, television image does not appear equally.
Referring to Fig. 2, when the PIP sprite shows that connection switch and quiet frame control end are " H " high level, IC
3 Pin 3 output " H " high level of 555 utilize this high level signal to keep the on-state of complete machine power supply relay.When the chip enable end CE of main core (μ PD17053) becomes low level, will make complete machine power control terminal Power pin 21 dead electricity; And when the CE end became " H " high level, the pin 21 of Power end can not become high level " H " automatically, can only pass through closed key power supply, and the level of 21 pin is uprised.Based on above-mentioned analysis, with IC
44066 pin 1,2 is in parallel with keyboard power (being the pin 52,59 of μ PD17053), then at IC
4Pin 13 add from IC
3" H " high level signal of pin 3 makes when sprite switch connection (on) demonstration of PIP and quiet frame, uses its control IC
4Pin 1,2 closures.
When the Power end turn-offs for " L " low level, from IC
3" H " high level signal of pin 3 is through D
3, C
9Rectifying and wave-filtering is at C
9The voltage that forms is kept BG
1Conducting, thus make complete machine power control relay J keep closure, promptly keep on the screen picture not lose.
Power connection is put, when the effect of reset control circuit is each energized, make the digital tuning of complete machine channel selection all be in the frequency synthesis state of TV, do not cause the disorder of other function and out of control in the time of also power connection must being guaranteed, IC in the time of promptly power connection must being guaranteed
3The pin 3 of (referring to Fig. 2) is in initial low level state.Because the keyboard power in the native system connects control and outer deposit data is preserved control and the retentive control of complete machine power supply all is subordinated to IC
3State Control.
Power connection is put reset circuit (30) by IC
2Two JK F/F4027 form, its pin 7S
2End is when each power connection, and all set is high level " H ", then pin 1Q
2Output " H " level, (A) signal that is somebody's turn to do " H " level is added to bidirectional analog switch (32) IC
4Pin 5, connect thereby make the state of the synthetic digital tuning of frequency synthesis/ voltage switch pin 3,4, send remote control/digital tuning system switching plate two ends, all be in frequency synthesis digital tuning state to realize each power connection.
For guaranteeing after the complete machine power connection not dead electricity, monostable multivibrator (36) IC
3 Pin 4 should be low level " L " when power connection, state is not overturn.Its control logic is as follows: NAND gate (34) IC
1 Pin 13 meet power supply (29) V
DDBe " H " high level, pin 12 is received the C of RC charging delay circuit (33)
3, because V
DDPass through R
3C
3Charging has the regular hour constant, so during power connection, pin 13 is a high level, pin 12 is a low level.Because the state of electric capacity can not suddenly change, so the pin 11 of NAND gate is output as high level, it is added to bidirectional analog switch (35) IC
44066 pin 12 is connected the analog switch of pin 11 and 10 (grounding pin), thereby is made IC
3555 pin 4 ground connection, i.e. IC
3555 are forced to reset, and Guarantee Status is not overturn.If state turnover, dead electricity at once just behind the power connection then, and can't start shooting.
Monostable multivibrator (36) IC
3 Pin 3 output control power connection holding circuits are connected control circuit, outer deposit data preservation control circuit and complete machine power supply retentive control circuit comprising keyboard power.
Outer deposit data is preserved control circuit and is comprised inverter (17), bidirectional analog switch (18) and E
2PROM (8).
Referring to Fig. 2, from power connection put, the IC of reset circuit
3The signal of 555 pins 3 (" H " level) is through inverter T output " L " level, by IC
64066 pin input bidirectional analog switch, IC
6Pin 1 and E
2The CS of PROM μ PD6252 connects, the E of pin 2 and master controller
2PROM writes control pin 39 and connects.
When carrying out the synthetic digital tuning conversion of frequency synthesis/voltage, should keep the data of another digital tuning state, chip enable (CE) signal of exporting with master controller pin 40 removes to control E
2The CE end of PROM, pin 39 and E
2Two sheet choosings (CS) end of the pin 7 of PROM is connected, and realizes that chip selection signal transmits; The serial clock of pin 41 (SCL) sends E to
2The SCL end of PROM; Pin 42 and E
2Pin 5 serial datas (SDA) end of PROM links to each other, and realizes that both data are passed on.
When the level of the CE of the pin 13 of μ PD17053 end main power source is uprised by low level, chip will reset, and carry out initialization, and control program will begin to carry out from zero-address, and then the digital tuning of channel selection will be since the 1st channel position, and with E
2The data that PROM μ PD6252 is stored are passed to the RAM of master controller.
For fear of the state change process that said chip resets and produced occurring; become between low period at CE; confirm to detect initial condition; do not change as initial state; just channel selection voltage and the wave band switch data of storing among the RAM " duplicated " μ PD6252; so become at CE during " L " level; should be set to low level " L " to the sheet of volatile memory μ PD6252 not choosing (CS) end; do not allow μ PD6252 chip operation, then can realize tuning voltage and the wave band switch data of protecting μ PD6252 to be stored.
The conversion control circuit of the 1st cover and the 2nd frequency synthetizing digital tuning comprises two-way inverter (19,24), emitter follower (20,25) and bidirectional analog switches set (21-23,26-28).
The switching of frequency synthesis digital tuning " 1 " and " 2 " as shown in Figure 1, the 1st cover and the phase-locked loop integrated package of the 2nd frequency synthetizing digital tuning all adopt TD6358P (in the frequency synthesis tuner).Pinning output signal from frequency synthesis tuner IC (TD6358P) pin 20 is input to the corresponding keyed end of master controller, when this keyed end is the locking-in state of frequency synthesis digital tuning during for high level, as this end is low level, then is the non-locking-in state of frequency synthesis digital tuning.
The conversion of the 1st cover and the 2nd frequency synthetizing digital tuning realizes by switching serial data (SDA), serial clock (SCL) and enabling (ENABLE) 3 groups of data.When frequency synthesis digital tuning state, be the related data that makes the TD6358P output channel, from pin 11-13 output VHF
L, VHF
HWith the wave band switching signal of UHF, the channel selection tuning voltage after the pin 9 output phase detections.The later channel data of μ PD17053 channel selection is latched, simultaneously the data of exportable standard channel.When the sprite of PIP shows when turn-offing, with string data, serial clock with enable the Phase Lock Loop IC that 3 groups of data passes are given the frequency synthesis digital tuning
8(TD6358P).
Referring to Fig. 2, that utilizes that the PIP sprite shows opens (on)/close (off) Phase Lock Loop IC to first cover and second frequency synthetizing digital tuning
8And IC
9On off operating mode switch.When the sprite of PIP was shown as connection (on), signal (C) was a high level, so IC
5The pin 1 of six not gates 4069 also is a high level; When the sprite of PIP is shown as shutoff (off) state, IC
5Pin 2 be high level, make bidirectional analog switch I C
64066 pin 12 and IC
74066 pin 12,13 is high level, so IC
6Pin 10 and 11 switch connections, IC
7Pin 10 and 11 and IC
7Pin 1 and 2 switches all connect.Because the signal from μ PD17053 pin 63 is to receive IC
7Pin 10 and 9, the phase-locked loop locking signal of pin 59 is to receive IC
7Pin 2 and 3, and the chip enable signal of pin 38 is to be added to IC
6Pin 10 and 9, so μ PD17053 just can make the phase-locked loop table 1 of the 1st frequency synthetizing digital tuning
| --- 1 | --- 2 | --- 3 | Passage | |
| 0 1 1 0 1 | 1 0 1 1 1 | 1 1 0 0 1 | 6 5 3 2 7 | 2 5 12 15 4 |
The selection control switching circuit of audio frequency, video (AV) signal comprises 4 groups of buffering input stages (45,48,51,54), 2 lines-4 line decoder (46,49,52,55) and 8 analog switches (47,50,53,56) form, buffering input stage (45,48) is established emitter follower (44) before.
Referring to Fig. 4, by the selection control of this circuit, can realize selection control main, sprite 4 programs, its 4 cover signal source comprises: ground broadcast TV program 2 covers that double high-frequency head receives by the 1st cover and the 2nd frequency synthetizing digital tuning; Broadcasting satellite program by the synthetic digital tuning reception of voltage; Program by external audio frequency video (AV) device plays.
IC
12-IC
15All use 4052, it is that CMOS two 4 selects 1 data selector/4 circuit-switched data distributors, forms (as shown in Figure 5) by buffering input 2 lines-4 line decoder and 8 analog switches, is input to IC
12And IC
13Pin 9 and 10 input control signal come the Q signal of the flip-flop circuit output of autonomous controller PIP sprite display switch signal and master controller initialization control circuit.Be input to IC
14The input control signal of pin 9,10 is the output signals from the main picture image input conversion of μ PD17053 pin 43,44.Be input to IC
15The input control signal of pin 9,10 is the output signals from the sub-screen image input conversion of μ PD17053 pin 49,50.
Table 2 provides the corresponding situation of state of 4 cover signal sources.
Table 3 is the truth table of IC4052.
Table 4 provides audio frequency, video (AV) signal selects control can realize logic diagram main, the sprite state variation.
In addition, when the synthetic digital tuning of voltage converts the frequency synthesis digital tuning to, the relevant information that broadcasting satellite receives will be stored in E
2Among the PROM μ PD6252, when the frequency synthesis digital tuning converts the synthetic digital tuning of voltage to, from the Phase Lock Loop IC of frequency synthesis digital tuning
8,9(TD6358P) the pinning output signal of pin 20 is a high level, and then the data of the tuning voltage of channel selection and wave band switching will be kept at the Phase Lock Loop IC of frequency synthesis digital tuning
8,9In.(IC
8-TD6358P), realize the digital tuning of the 1st cover frequency synthesis.
When the PIP sprite is shown as connection (on), IC
5Pin 2 be low level, then above-mentioned various states are all changed, then μ PD17053 just can make the Phase Lock Loop IC of the 2nd frequency synthetizing digital tuning
9, realize that the 2nd overlaps the digital tuning of frequency synthesis.
The sound subcarrier tuner control circuit that broadcasting satellite receives comprises sound subcarrier tuning voltage initialization circuit (38), 8 tunnels analogy switches (39), 4D latch (40), input control circuit (41), level-conversion circuit (42) and the decoder (43) that stabilized voltage power supply (37), broadcasting satellite receive, and 8 tunnels analogy switches export the broadcasting satellite dash receiver to.
Referring to Fig. 3, IC
104051 is 8 to select 1 data selector/8 circuit-switched data distributors, its pin 9-11 is for selecting the control end of input, through input control and level-conversion circuit, be added to decoder, in order to control the analog switch of 8 channel data inputs, pin 4,2,5,1,12,15,14,13 is the data input pin of 8 passages, and pin 3 is public data output end, is connected with broadcasting satellite intermediate frequency receiving element.W
1-W
5Be used to preset the level of the sound subcarrier frequency of 5 different colour television standards, and be added to IC respectively
10 Pin 4,12,15,2,5, select the sound subcarrier of 5 colour television standards separately.
The NTSC/PAL/SECAM television system switching signal of the pin 1-3 output of μ PD17053 is to be added to Fig. 3 IC
11Pin 4,7,13, by the various combination of high-low level, main control system television system change-over circuit can be selected the sound subcarrier of 5 kinds of television systems.
Referring to Fig. 2, work as IC
2When the signal of pin 1 output is high level, be the frequency synthesis digital tuning; If during low level, then be in the synthetic digital tuning state of voltage.When the voltage of broadcasting satellite reception synthesizes the digital tuning state, Fig. 3 IC
11The CP of pin 5 be low level, promptly allow the data of the synthetic digital tuning of voltage that the broadcasting satellite intermediate frequency receives to transmit, make to send IC to from μ PD17053 pin 1-3 system conversion data
104051 selection input pin 9-11.
When being operated in frequency synthesis digital tuning state, 4D latch (IC
114042) CP end is input as high level, then carries out data latching, because E
2The data that PROM stored are the memory blocks that are stored in different addresses, so the data of different systems can realize latching, even the state of the pin 1-3 of μ PD17053 changes, its output is still constant.
The truth table of the respective channel data of 8 tunnels analogy multiplexers of the different output level institute corresponding selection of μ PD17053 television system switched pins 1-3 is as shown in table 1.
When the frequency synthesis digital tuning converted the synthetic digital tuning of voltage to, promptly the intermediate-freuqncy signal that receives from broadcasting satellite was carried out the synthetic digital tuning of voltage, from the tuning voltage of the pin 22 output pulse widths modulation (PWM) of μ PD17053.Table 2
Table 3
Annotate: the no high-low level of " φ " expression changes, and is meaningless.
| The TV/ satellitosis | Key frame | Sprite | |||||||
| State | on | | State | 44 | 43 | | 50 | 49 | |
| TV TV/PIP satellite satellite/ | 0 1 0 1 | 1 1 0 0 | TV looks 1 and looks 2 | 0 1 0 1 | 0 0 1 1 | TV looks 1 and looks 2 | 0 1 0 1 | 0 0 1 1 | |
| Input | Output channel | ||
| | B | A | |
| 0 0 0 0 1 | 0 0 1 1 | 0 1 0 1 φ | 1D 0/Q 0,2D 0/Q 01D 1/Q 1,2D 1/Q 11D 2/Q 2,2D 2/Q 21D 3/Q 3,2D 3/Q 3Do not have |
Table 4 picture state changes logic diagram
| Sequence number | Expanding system | μPD17053 | Key frame | Sprite | |||||||||||
| PIP ON | PLL/VS Q | Main picture control | Son is drawn control | Remarks | |||||||||||
| 44 | 43 | 50 | 49 | TV | Look 1 | Look 2 | Satellite | TV | Look 1 | Look 2 | Satellite | ||||
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 | 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 | 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 | 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 | Φ Φ Φ Φ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Φ Φ Φ Φ 0 1 | Φ Φ Φ Φ 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Φ Φ Φ Φ 0 0 | PLL 1PLL 2PLL 2PLL 2PLL 2BS BS BS | PLL 1PLL 1PLL 1PLL 1PLL 1PLL 2 | The outer AV of the outer AV of the outer AV of the outer AV of the outer AV of outer AV | BS BS BS BS BS BS | PLL 2PLL 2PLL 2PLL 2BS | PLL 1PLL 1PLL 1PLL 1PLL 1 | PLL 2PLL 2PLL 2PLL 2 | BS BS BS BS | The start original state need preset that external need preset on the same stage that adjustable master is adjustable, non-adjustable, the sub adjustable boss of son adjustable, the sub non-adjustable master of non-adjustable on the same stage adjustable master all non-adjustable and on the same stage boss all non-adjustable boss all can not tune adjustable all non-adjustable all non-adjustable all can not adjustable, the main non-adjustable all adjustable non-adjustable non-adjustable bosses of non-adjustable all non-adjustable all non-adjustable satellites of tune on the same stage, but tune is adjustable |
Continuous table 4
Annotate: the no high-low level of " Φ " expression changes, and is meaningless.
| 27 28 29 30 31 32 33 34 35 36 37 38 39 40 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 1 1 1 1 0 0 0 0 1 1 1 1 | 0 0 0 0 0 0 1 1 1 1 1 1 1 1 | 0 1 0 1 0 1 0 1 0 1 0 1 0 1 | 1 1 0 0 1 1 0 0 1 1 0 0 1 1 | BS BS | PLL 1 PLL 1 PLL 1 PLL 1 | The outer AV of the outer AV of the outer AV of outer AV | BS BS BS BS | BS BS BS | PLL 1 PLL 1 PLL 1 | PLL 2 PLL 2 PLL 2 PLL 2 | BS BS BS BS | Main adjustable boss on the same stage, but tune is adjustable, main non-adjustable boss on the same stage, all non-adjustablely all non-adjustablely all can not the adjustable all non-adjustable all non-adjustable all non-adjustable boss of tune be satellite, adjustable on the same stage all non-adjustable all non-adjustable boss on the same stage, and is non-adjustable |
Claims (2)
1. the remote control and the digital tuning system of a satellite reception, two high-frequency TV, picture-in-picture comprise the main controller of being made up of single chip microcomputer, it is characterized in that:
(1), said master controller is by forming with the one chip microcomputer of frequency synthesis and the synthetic digital tuning video PIP control of voltage;
(2), also including control signal identification circuit, master controller initialization control circuit, complete machine power supply retentive control circuit, power connection puts reset control circuit, outer deposit data and preserves the conversion control circuit of control circuit, first cover and second frequency synthetizing digital tuning, sound subcarrier tuner control circuit that broadcasting satellite receives and the selection control switching circuit of AV signal
(3), said control signal identification circuit comprises differential circuit and NAND gate, two differential circuits are connected with the quiet frame pin of sprite with the sprite display end of the PIP of master controller respectively, the control signal that the output of differential circuit is exported after NAND gate is sent the master controller initialization control circuit, the differential circuit that input is connected with the sprite display switch end of master controller PIP, its output are also delivered to the input of the conversion control circuit of described first cover and second frequency synthetizing digital tuning;
(4), said master controller initialization control circuit comprises inverter, flip-flop circuit, the bidirectional analog switches set, monostable multivibrator, NAND gate, integral delay circuit, the input of inverter and monostable multivibrator are connected with the output of control signal identification circuit respectively, the output one tunnel of inverter is according to this through integral delay circuit, send the bidirectional analog switch after the NAND gate, the bidirectional analog switch also is connected with the main power source pin of master controller, another road input of NAND gate is provided by the output of monostable multivibrator, another bidirectional analog switch is arrived again through flip-flop circuit in another road of inverter output, this bidirectional analog switch is connected with the switch of remote control/digital tuning system plate in addition, and the output of monostable multivibrator is also preserved control circuit with complete machine power supply retentive control circuit and outer deposit data respectively and is connected;
(5), said complete machine power supply retentive control circuit comprises bidirectional analog switch, adder, rectifying and wave-filtering and complete machine power control circuit, the bidirectional analog switch is connected with " key scanning goes out " pin with the output of the monostable multivibrator of master controller initialization control circuit and " key scanning is gone into " of master controller respectively, and the input of adder is connected with the output of the monostable multivibrator of master controller initialization control circuit and the mains switch control pin of master controller respectively;
(6), said power connection is put multiple control circuit and is comprised the power connection setting circuit, the bidirectional analog switches set, the RC delay circuit that charges, NAND gate and monostable multivibrator, the switch ends of remote control/digital tuning system plate is sent in the output that power connection is put reset circuit behind the bidirectional analog switch by monostable trigger-action circuit, the output of RC charging delay circuit and+5V power supply are successively through NAND gate, the bidirectional analog switch, insert the power connection holding circuit behind the monostable multivibrator, the power connection holding circuit comprises keyboard power connection control circuit, outer deposit data is preserved control circuit and complete machine power supply retentive control circuit;
(7), said outer deposit data preservation control circuit comprises inverter, bidirectional analog switch and E
2PROM, the signal that comes autonomous controller initialization control circuit monostable multivibrator by inverter behind the bidirectional analog switch with E
2The CS end of PROM connects E
2CE end and the master controller E of PROM
2PROM writes control end and connects E
2The E of the SCL end of PROM, SDA end and master controller
2PROM communication is connected with the phase-locked loop intergrated circuit communication ends of frequency synthesis digital tuning.The bidirectional analog switch also with the E of master controller
2PROM writes control end and connects;
(8), the conversion control circuit of said first cover and second frequency synthetizing digital tuning comprises two-way inverter, emitter follower and bidirectional analog switches set, the PIP sprite of control signal identification circuit shows that the differential circuit output of connection signal delivers to wherein 1 inverter, and the keyed end of phase-locked loop of phase-locked loop, master controller of described first frequency synthetizing digital tuning and the remote control/digital tuning system plate of television set are delivered in the output one tunnel of inverter respectively after emitter follower is delivered to 3 bidirectional analog switches respectively; The keyed end and the remote control/digital tuning system plate of phase-locked loop of phase-locked loop, the master controller of described second frequency synthetizing digital tuning delivered in another road output of inverter successively respectively after another inverter, emitter follower also send 3 bidirectional analog switches respectively; Also be connected with the described first phase-locked loop of cover and the bidirectional analog switch that is connected of the phase-locked loop of described second cover respectively with the Enable Pin of the phase-locked loop of the frequency synthesis digital tuning of master controller;
(9), the sound subcarrier tuner control circuit of said broadcasting satellite reception comprises stabilized voltage power supply, sound subcarrier tuning voltage initialization circuit, 8 tunnels analogy switches, 4D latch, input control circuit, level-conversion circuit and decoder, the CP end and the D of 4D latch
0-D
2End is connected with the flip-flop circuit Q signal output of master controller initialization control circuit and the NTSC/PAL/SECAM television system switching signal end of master controller respectively, and the output one tunnel of 4D latch is sent the broadcasting satellite dash receiver successively behind input control circuit, level-conversion circuit, decoder and 8 tunnels analogy switches; Television set television system change-over circuit is sent on another road, and 8 channel data inputs of 8 tunnels analogy switches also are connected with broadcasting satellite sound subcarrier tuning voltage initialization circuit;
(10), the selection control switching circuit of said AV signal comprises 4 groups of buffering input stages, 2 lines-4 line decoder and 8 analog switches are formed, the 1st, 2 groups of buffering input stages are connected with the flip-flop circuit Q signal output of master controller PIP sprite display switch end and master controller initialization control circuit respectively, the output of buffering input stage is respectively through the 1st, deliver to analog switch respectively behind 2 group of 2 line-4 line decoder, the 1st, the input of 2 groups of analog switches receives with broadcasting satellite respectively, the video of double high-frequency head, audio signal connects, the 1st, the broadcasting satellite reception of 2 groups of analog switch outputs and the video of tuner key frame, audio signal with without the broadcasting satellite vision signal of the 1st group of analog switch, and external vision signal is delivered to the 3rd group of analog switch and is exported main screen video, audio signal, the input of the 3rd group of buffering input stage is connected with the selecting side, picture signal source of master controller, and output signal is imported the 3rd group of analog switch behind 2 lines-4 line decoder, the broadcasting satellite vision signal and the broadcasting satellite of the 1st group of analog switch output receive, the video of double high-frequency head, audio signal and external audio frequency signal are delivered to the 4th group of analog switch and are exported sprite video and audio signal, the 4th group of buffering input stage is connected with the signal source selecting side of master controller, and output signal is imported the 4th group of analog switch behind 2 lines-4 line decoder.
2. the remote control and the digital tuning system of broadcasting satellite reception as claimed in claim 1, two high-frequency TV, picture-in-picture is characterized in that said master controller is made up of 4 microcomputers of μ PD17053 type monolithic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93114642A CN1043398C (en) | 1993-11-08 | 1993-11-08 | Satellite receiving, dual HF T.V, picture-in-picture telecontrol and digital tuning system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93114642A CN1043398C (en) | 1993-11-08 | 1993-11-08 | Satellite receiving, dual HF T.V, picture-in-picture telecontrol and digital tuning system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1102742A CN1102742A (en) | 1995-05-17 |
| CN1043398C true CN1043398C (en) | 1999-05-12 |
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ID=4990594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN93114642A Expired - Fee Related CN1043398C (en) | 1993-11-08 | 1993-11-08 | Satellite receiving, dual HF T.V, picture-in-picture telecontrol and digital tuning system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1043398C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101742191B (en) * | 2008-11-25 | 2012-07-04 | 康佳集团股份有限公司 | Novel TV set |
| TWI436643B (en) * | 2011-02-25 | 2014-05-01 | Tatung Co | Television motherboard and a source code burning method applied thereon |
| CN105158805B (en) * | 2015-08-11 | 2017-10-27 | 中国石油天然气集团公司 | The phased orientation receive transducer mounting structure of acoustic logging |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1032893A (en) * | 1987-10-28 | 1989-05-10 | Rca许可公司 | Television receiver with in-memory switching signal |
| CN1056207A (en) * | 1990-04-30 | 1991-11-13 | 汤姆森消费电子有限公司 | Television equipment with picture-in-picture processing capacity |
-
1993
- 1993-11-08 CN CN93114642A patent/CN1043398C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1032893A (en) * | 1987-10-28 | 1989-05-10 | Rca许可公司 | Television receiver with in-memory switching signal |
| CN1056207A (en) * | 1990-04-30 | 1991-11-13 | 汤姆森消费电子有限公司 | Television equipment with picture-in-picture processing capacity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1102742A (en) | 1995-05-17 |
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