CN104333711A - Fixed output sequence image magnification algorithm and system thereof - Google Patents
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Abstract
The invention discloses a fixed output sequence image magnification algorithm and a system thereof. The system comprises a sequence control module and a data processing module, wherein the sequence control module comprises an input sequence computation unit and an input sequence image output unit; and the data processing module comprises an image magnification unit and an output sequence sorting unit. The algorithm comprises the following steps: S1, input image sequence control processing: a background system determines the sequence of an image needing to be input by a magnification module of current fixed sequence output, wherein the sequence is an input sequence; and the sequence control module controls an image source according to an input image sequence, and outputs an image to the magnification module; and S2, image magnification processing of a fixed output sequence. Through adoption of the algorithm and the system, the effects of avoidance of sudden change of image brightness, normal image magnification function, use of small cache in the image magnification algorithm, saving of cost and lowering of the power consumption can be achieved.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of fixing output timing image interpolator arithmetic and system thereof.
Background technology
Digital image processing techniques originate from the twenties in 20th century, through the development of over half a century, have been widely used in the every field such as industry, health care, Aero-Space, have played more and more important effect in national economy.A substance of image processing technique is the mitigation and amplification (abbreviation scaling) of image, and it has a wide range of applications in image display, transmission (communication), analysis and cartoon making etc.In such applications, a kind of interpolator arithmetic of fixing output timing and system thereof are applied often.
The image magnification method of traditional fixing output timing has frame buffer to amplify the multirow buffer amplification different with input and output clock.Frame buffer amplification utilizes a frame buffer to store data, according to output timing output image after amplification.Its advantage controls simply, and shortcoming is that excessive, the integrated difficulty of buffer is high, area is large, power consumption is large, thus the noise of meeting effect diagram picture and quality.The interpolator arithmetic of different input clocks and output clock is adopted to have buffer used a lot of advantage less of frame buffer, but still need larger buffer, be unfavorable for integrated, area is larger, power consumption is comparatively large, and there is latches data problem because input clock is different with output clock.Therefore, research and develop a kind of integrated easily, the interpolator arithmetic of area is little, power consumption is little fixing output timing and system very necessary.
Summary of the invention
The object of the present invention is to provide a kind of fixing output timing image interpolator arithmetic and system thereof, thus solve the foregoing problems existed in prior art.
To achieve these goals, the system of a kind of fixing output timing image interpolator arithmetic of the present invention, this system comprises time-sequence control module and data processing module;
Described time-sequence control module, calculates the information of input timing according to input picture size, output image size, cache size and output timing, and exports with input timing control inputs image;
Described data processing module, the sequential for carrying out input picture to amplify, adjust output image makes output timing meet the standard of fixing output timing and export enlarged image by fixing output timing.
Described time-sequence control module comprises input timing computing unit and input timing image output unit;
Described input timing computing unit, for calculating the information of input timing, comprises the row length of input timing, total line number of input timing and redundancy clock number;
Described input timing image output unit, for exporting according to input timing control inputs image.
Preferably, described data processing module comprises image enlarging unit and output timing arrangement unit;
Described image enlarging unit, for amplifying input picture;
Described output timing arranges unit, meets the standard of fixing output timing for arranging output timing to it.
The fixing output timing image interpolator arithmetic of the present invention's one, this algorithm comprises:
S1, the process of input picture sequencing control:
S1-1, background system determine the sequential of the amplification module required input image of current fixing output timing, and described sequential is input timing;
S1-2, time-sequence control module are according to input timing control chart image source, and output image is to amplification module;
S2, Nonlinear magnify process is carried out to the input picture of amplification module, adjust the output timing of amplification module output image to required fixed time sequence simultaneously.
Preferably, input picture sequencing control process described in step S1, step is as follows more specifically:
S0-1, background system determination line of input sequential;
S0-2, background system determine input row sequential;
S0-3, background system determination clock redundant digit;
S0-4, background system determination current line clock number;
S0-5, by input timing control chart image source, output image to amplification module.
More preferably, background system determination current line clock number described in step S0-4, concrete grammar is: by the total line number of clock redundant digit divided by input timing, and the clock number scattered often gone, then judges from the first row whether each line of input can scatter clock successively;
Wherein, the described often row clock number scattered is decimal more.
More preferably, described to judge whether each line of input can scatter the determination methods of clock as follows: start to increase progressively numbering successively with Arabic numerals 1 from the first row line of input, judges whether the clock number of current input line increases by 1 with the product of numbering and the every row clock number scattered more;
The integer part of product described in current line is identical with the integer part of product described in previous row, then the clock number of current input line does not increase;
The integer part of product described in current line increases by 1 than the integer part of product described in previous row, then the clock number of current input line increases by 1.
Preferably, the Nonlinear magnify described in step S2 and fixed time sequence export, and concrete steps are:
The input picture of S2-1, confirmation amplification module;
S2-2, buffer latch view data;
S2-3, background system determination output image export the outgoing position of row;
The current coefficient used exporting the row line of input of input picture used and each row of line of input of described input picture used of S2-4, background system determination output image;
S2-5, the line of input data adopting input picture used and coefficient thereof, calculate the defeated trip data of output image;
S2-6, output data.
More preferably, the described defeated trip data determining the line of input of the current output row of output image input picture used, the coefficient used calculating each row of line of input of described input picture used and calculating output image, concrete grammar is as follows:
Using the initial coefficients s of amplification coefficient as each line of input, described s meets 1≤s < 2;
If the current coefficient n exporting row line of input used, n is not less than 1, then current defeated trip data is line of input data used, and namely current output row is identical with line of input used; The remaining coefficient of line of input used becomes (n-1), line of input used participates in next line and exports row calculating, the defeated trip data of next line is the sum of products of a line line of input data coefficient 1-(n-1) used with it after the sum of products line of input used of line of input data used coefficient remaining with it change (n-1), after line of input used, the coefficient of a line line of input becomes s-[1-(n-1)], i.e. s+n-2;
If the current Coefficient m exporting row line of input used, m is less than 1, then current defeated trip data is the sum of products of a line line of input data coefficient used with it (1-m) after the sum of products line of input used of line of input data used and its coefficient, line of input used no longer participates in follow-up output row operation, after line of input used, the coefficient of a line line of input becomes s-(1-m), i.e. s+m-1;
Stop to last column from the first row by the defeated trip data of above-mentioned algorithm computing.
More preferably, the described coefficient sum used exporting row each line of input used is all 1.
More preferably, described s meets 1≤s≤1.3.
The invention has the beneficial effects as follows:
1, because the method that fixing output timing image of the present invention amplifies adopts the method for dividing equally to be distributed in line of input by clock redundant digit, therefore image brightness is not suddenlyd change;
2, because fixing output timing image interpolator arithmetic of the present invention adopts the input timing being different from output timing, therefore less buffer memory just can maintain zoom function normal operation;
3, only use less buffer memory just can reach the function of Nonlinear magnify and keep brightness not suddenly change in image multiplication method of the present invention, therefore algorithm of the present invention and system cost ground, power consumption is little.
Accompanying drawing explanation
Fig. 1 is the system schematic of a kind of fixing output timing image interpolator arithmetic of the present invention;
Fig. 2 is the schematic flow sheet of a kind of fixing output timing image interpolator arithmetic of the present invention;
Fig. 3 is the flow chart schematic diagram of input picture sequencing control process in a kind of fixing output timing image interpolator arithmetic of the present invention;
Fig. 4 is the schematic flow sheet that in a kind of fixing output timing image interpolator arithmetic of the present invention, Nonlinear magnify and fixed time sequence export.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with accompanying drawing, the present invention is further elaborated.Should be appreciated that embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
With reference to figure 1, the system of a kind of fixing output timing image interpolator arithmetic of the present invention, this system comprises time-sequence control module and data processing module;
Described time-sequence control module, according to input picture size, output image size, cache size and output timing, for calculating the information of input timing, and exports with input timing control inputs image;
Described data processing module, the sequential for carrying out input picture to amplify, adjust output image makes output timing meet the standard of fixing output timing and export enlarged image by fixing output timing.
Described time-sequence control module comprises input timing computing unit and input timing image output unit;
Described input timing computing unit, for calculating the information of input timing, comprises the row length of input timing, total line number of input timing and redundancy clock number;
Described input timing image output unit, for exporting according to input timing control inputs image.
Described data processing module comprises image enlarging unit and output timing arranges unit;
Described image enlarging unit, for amplifying input picture;
Described output timing arranges unit, meets the standard of fixing output timing for arranging output timing to it.
With reference to figure 2, one of the present invention fixes output timing image interpolator arithmetic, and this algorithm comprises:
S1, the process of input picture sequencing control:
S1-1, background system determine the sequential of the amplification module required input image of current fixing output timing, and described sequential is input timing;
S1-2, time-sequence control module are according to input timing control chart image source, and output image is to amplification module;
S2, Nonlinear magnify process is carried out to the input picture of amplification module, adjust the output timing of amplification module output image to required fixed time sequence simultaneously.
With reference to figure 3, the fixing output timing image interpolator arithmetic of the present invention's one, input picture sequencing control process described in step S1, step is as follows more specifically:
S0-1, background system determination line of input sequential;
Line of input sequential described in step S0-1 is the clock number of every a line line of input, adopts following formula to realize:
Line of input clock number=(output image height/input picture height) × output row clock number (1);
S0-2, background system determine input row sequential;
Input the line number that row sequential is each frame described in step S0-2, adopt following formula to realize:
Input line number=INT (exporting row clock number × output line number/line of input clock number) (2);
S0-3, background system determination clock redundant digit;
Background system determination clock redundant digit described in step S0-3, adopts following formula to realize:
Redundancy clock number=output row clock number × output line number-line of input clock number × input line number (3);
S0-4, background system determination current line clock number;
Background system determination current line clock number described in step S0-4, the method of dividing equally is adopted to be distributed in line of input by clock redundant digit, concrete grammar is: by the total line number of clock redundant digit divided by input timing, often gone the clock number that should scatter more, from the first row, then judged whether each line of input can scatter clock successively; Wherein, the clock number that described often row should scatter more is decimal;
S0-5, output image to amplification module by input timing control chart image source.
Wherein, judge described in step S0-4 whether each line of input can scatter the determination methods of clock as follows: all input line numbers are started to increase progressively numbering successively with Arabic numerals 1, judge whether the clock number of current input line increases by 1 with numbering and the product of clock number that often row scatters;
The integer part of product described in current line is identical with the integer part of product described in previous row, then the clock number of current input line does not increase;
The integer part of product described in current line increases by 1 than the integer part of product described in previous row, then the clock number of current input line increases by 1.
Citing 1 illustrates how to judge whether each line of input can scatter clock, and such as input total line number and redundancy clock number is respectively 50 row and 30, so often row should scatter 0.6 clock more, again due to the integer of clock, draws and scatters result as following table 1:
Table 1: example 1 judges whether each line of input can scatter the result of clock
Because often the clock number of row line of input has the characteristic of integer type, so after adopting the method for dividing equally to carry out distribution clock, carrying out judging whether the clock number of current line can increase according to described determination methods.
With reference to figure 4, the fixing output timing image interpolator arithmetic of the present invention's one, the Nonlinear magnify described in step S2 and fixed time sequence export, and concrete steps are:
The input picture of S2-1, confirmation amplification module;
Amplification module input picture described in step S2-1 is through the adjusted output image of sequencing control through step 1;
S2-2, buffer latch view data;
The output line output position of S2-3, background system determination output image;
The output line output position of output image is determined described in step S2-3, defining method is: according to the outgoing position of buffer size, input timing, output timing, input picture the first row position, input image size and output image size determination output image the first row, later each row connects its previous row and exports successively.
The current line of input exporting row input picture used of S2-4, background system determination output image, calculates the coefficient used of each row of line of input of described input picture used according to the line of input position of input picture used and amplification coefficient;
S2-5, the line of input data adopting input picture used and coefficient thereof, calculate the defeated trip data of output image;
Wherein, describedly determine the output image current output row line of input of input picture used and the coefficient used of each row of line of input of input picture used and the defeated trip data of output image, concrete grammar is as follows:
Using the initial coefficients s of amplification coefficient as each line of input, described s meets 1≤s≤1.3;
If the current coefficient n exporting row line of input used, n is not less than 1, then current defeated trip data is line of input data used, and namely current output row is identical with line of input used; The remaining coefficient of line of input used becomes (n-1), line of input used participates in next line and exports row calculating, the defeated trip data of next line is the sum of products of a line line of input data coefficient 1-(n-1) used with it after the sum of products line of input used of line of input data used coefficient remaining with it change (n-1), after line of input used, the coefficient of a line line of input becomes s-[1-(n-1)], i.e. s+n-2;
If the current Coefficient m exporting row line of input used, m is less than 1, then current defeated trip data is the sum of products of a line line of input data coefficient used with it (1-m) after the sum of products line of input used of line of input data used and its coefficient, line of input used no longer participates in follow-up output row operation, after line of input used, the coefficient of a line line of input becomes s-(1-m), i.e. s+m-1;
Stop to last column from the first row by the defeated trip data of above-mentioned algorithm computing;
S2-6, output data.
Wherein, described in step S2-5, calculate the defeated trip data of output image, adopt formula (4) and formula (5):
The coefficient used (4) of coefficient used+rear a line line of input data × rear a line line of input of defeated trip data=input Current Datarow × input current line;
Coefficient=1 used (5) of coefficient used+rear a line line of input of current input line.
Illustrate the coefficient of each row of line of input how calculating described input picture used and calculate the defeated trip data of output image, the line number of citing line of input is 3 row, and fixed time sequence exports line number 5 row of row, and concrete outcome is as following table 2:
Table 2: the result of the coefficient of each row of the line of input of input picture used described in example 2 and the defeated trip data of calculating output image
By adopting technique scheme disclosed by the invention, obtain effect useful as follows:
The present invention can reach that image brightness is not suddenlyd change, zoom function is normal, use less buffer memory in image multiplication method, saves cost, reduces the effect of power consumption.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should look protection scope of the present invention.
Claims (10)
1. a system for fixing output timing image interpolator arithmetic, it is characterized in that, this system comprises time-sequence control module and data processing module;
Described time-sequence control module, calculates the information of input timing according to input picture size, output image size, cache size and output timing, and exports with input timing control inputs image;
Described data processing module, the sequential for carrying out input picture to amplify, adjust output image makes output timing meet the standard of fixing output timing and export enlarged image by fixing output timing;
Described time-sequence control module comprises input timing computing unit and input timing image output unit;
Described input timing computing unit, for calculating the information of input timing, comprises the row length of input timing, total line number of input timing and redundancy clock number;
Described input timing image output unit, for exporting according to input timing control inputs image.
2. system according to claim 1, is characterized in that, described data processing module comprises image enlarging unit and output timing arranges unit;
Described image enlarging unit, for amplifying input picture;
Described output timing arranges unit, meets the standard of fixing output timing for arranging output timing to it.
3. a fixing output timing image interpolator arithmetic, it is characterized in that, this algorithm comprises:
S1, the process of input picture sequencing control:
S1-1, background system determine the sequential of the amplification module required input image of current fixing output timing, and described sequential is input timing;
S1-2, time-sequence control module are according to input timing control chart image source, and output image is to amplification module;
S2, Nonlinear magnify process is carried out to the input picture of amplification module, adjust the output timing of amplification module output image to required fixed time sequence simultaneously.
4. one fixes output timing image interpolator arithmetic according to claim 3, and it is characterized in that, input picture sequencing control process described in step S1, step is as follows more specifically:
S0-1, background system determination line of input sequential;
S0-2, background system determine input row sequential;
S0-3, background system determination clock redundant digit;
S0-4, background system determination current line clock number;
S0-5, by input timing control chart image source, output image to amplification module.
5. one fixes output timing image interpolator arithmetic according to claim 4, it is characterized in that, background system determination current line clock number described in step S0-4, concrete grammar is: by the total line number of clock redundant digit divided by input timing, the clock number scattered often gone, then judges from the first row whether each line of input can scatter clock successively;
Wherein, the described often row clock number scattered is decimal more.
6. one fixes output timing image interpolator arithmetic according to claim 5, it is characterized in that, described to judge whether each line of input can scatter the determination methods of clock as follows: start to increase progressively numbering successively with Arabic numerals 1 from the first row line of input, judges whether the clock number of current input line increases by 1 with the product of numbering and the every row clock number scattered more;
The integer part of product described in current line is identical with the integer part of product described in previous row, then the clock number of current input line does not increase;
The integer part of product described in current line increases by 1 than the integer part of product described in previous row, then the clock number of current input line increases by 1.
7. one fixes output timing image interpolator arithmetic according to claim 3, it is characterized in that, the Nonlinear magnify described in step S2 and fixed time sequence export, and concrete steps are:
The input picture of S2-1, confirmation amplification module;
S2-2, buffer latch view data;
S2-3, background system determination output image export the outgoing position of row;
The current coefficient used exporting the row line of input of input picture used and each row of line of input of described input picture used of S2-4, background system determination output image;
S2-5, the line of input data adopting input picture used and coefficient thereof, calculate the defeated trip data of output image;
S2-6, output data.
8. one fixes output timing image interpolator arithmetic according to claim 7, it is characterized in that, the described defeated trip data determining the line of input of the current output row of output image input picture used, the coefficient used calculating each row of line of input of described input picture used and calculating output image, concrete grammar is as follows:
Using the initial coefficients s of amplification coefficient as each line of input, described s meets 1≤s < 2;
If the current coefficient n exporting row line of input used, n is not less than 1, then current defeated trip data is line of input data used, and namely current output row is identical with line of input used; The remaining coefficient of line of input used becomes (n-1), line of input used participates in next line and exports row calculating, the defeated trip data of next line is the sum of products of a line line of input data coefficient 1-(n-1) used with it after the sum of products line of input used of line of input data used coefficient remaining with it change (n-1), after line of input used, the coefficient of a line line of input becomes s-[1-(n-1)], i.e. s+n-2;
If the current Coefficient m exporting row line of input used, m is less than 1, then current defeated trip data is the sum of products of a line line of input data coefficient used with it (1-m) after the sum of products line of input used of line of input data used and its coefficient, line of input used no longer participates in follow-up output row operation, after line of input used, the coefficient of a line line of input becomes s-(1-m), i.e. s+m-1;
Stop to last column from the first row by the defeated trip data of above-mentioned algorithm computing.
9. a kind of fixing output timing image interpolator arithmetic according to claim 8, is characterized in that, describedly exports the coefficient used of row each line of input used and is all 1.
10. one fixes output timing image interpolator arithmetic according to claim 8, and it is characterized in that, described s meets 1≤s≤1.3.
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| CN101060607A (en) * | 2007-05-31 | 2007-10-24 | 友达光电股份有限公司 | Image zooming device and its method |
| US20080313439A1 (en) * | 2007-06-15 | 2008-12-18 | Denso Corporation | Pipeline device with a plurality of pipelined processing units |
| CN101662598A (en) * | 2008-08-26 | 2010-03-03 | 深圳艾科创新微电子有限公司 | Scaling system for continuous video data stream |
| CN103916612A (en) * | 2012-12-28 | 2014-07-09 | 深圳艾科创新微电子有限公司 | Random proportion zoom system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101060607A (en) * | 2007-05-31 | 2007-10-24 | 友达光电股份有限公司 | Image zooming device and its method |
| US20080313439A1 (en) * | 2007-06-15 | 2008-12-18 | Denso Corporation | Pipeline device with a plurality of pipelined processing units |
| CN101662598A (en) * | 2008-08-26 | 2010-03-03 | 深圳艾科创新微电子有限公司 | Scaling system for continuous video data stream |
| CN103916612A (en) * | 2012-12-28 | 2014-07-09 | 深圳艾科创新微电子有限公司 | Random proportion zoom system and method |
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