CN104321757B - Equipment connecting detection - Google Patents
Equipment connecting detection Download PDFInfo
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- CN104321757B CN104321757B CN201380027939.0A CN201380027939A CN104321757B CN 104321757 B CN104321757 B CN 104321757B CN 201380027939 A CN201380027939 A CN 201380027939A CN 104321757 B CN104321757 B CN 104321757B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
This document describes the system and method for detecting the connection of input/output (I/O) equipment.This method includes that I/O equipment is physically coupled to host port by the first signal wire and second signal line.This method further includes driving the first signal wire or second signal line for height via the active buffer of I/O equipment.This method further includes providing confirmation signal from host to equipment by not being driven to another signal wire of high potential by the active buffer of I/O equipment.
Description
Background technique
Methods and systems disclosed herein is related to input/output (I/O) signaling protocol.More specifically, use is disclosed
Low pressure, low-power solution in universal serial bus 2.0(USB2).
USB is configured to be standardized for communicating and supplying electrical power the interface between computer equipment
Industry agreement.USB2 agreement has enjoyed being widely used in almost each calculating equipment, and with perfect
Intellectual property (IP) asset portfolio and standardized software infrastructure technological development in terms of by numerous supports.
3.3 volt analog signaling of standard USB2 Normalization rule is for the communication between two ports USB2.3.3 volts
Signal strength tends to introduce integration challenge, this is because some advanced semiconductor technologies are just sent out towards low-down geometry
Exhibition, is no longer able to endure high voltage, such as 3.3 volts so as to cause the gate oxide of CMOS transistor.In addition, standard USB2
Specification leads to the power consumption in the relative high levels at both idle and active state places.Therefore, USB2 may be unsuitable for I/O function
Consumption applies the equipment strictly regulated, such as mobile platform.
Detailed description of the invention
Fig. 1 is the block diagram of universal serial bus structural according to the embodiment;
Fig. 2 is the block diagram of the universal serial bus physical layer with high speed (HS), low speed (LS) and full speed (FS) ability;
Fig. 3 is the block diagram with the eUSB2 physical layer of low speed or full speed ability;
Fig. 4 is used to the timing diagram of the SYNC pattern (pattern) in low speed or Full-Speed mode;
Fig. 5 is the timing diagram of end-of-packet (EOP) pattern in low speed or Full-Speed mode;
Fig. 6 A and 6B are the exemplary timing diagrams for showing eUSB2 signal sequence;
Fig. 7 is the timing diagram of low speed ties up the signal that continues;
Fig. 8 is the timing diagram for the equipment disconnection detection technology of full speed or low-speed handing during L0;
Fig. 9 is the timing diagram for the equipment disconnection detection technology of the high-speed mode during L0 state;
Figure 10 is the exemplary timing diagram for showing equipment connecting detection technology;And
Figure 11 is the exemplary timing diagram for showing the wherein equipment connecting detection scheme of equipment statement high speed capability.
Specific embodiment
Embodiment described herein is related to providing the power consumption of lower signal voltage and reduction compared with standard USB2
Improved signaling technology.Improved signaling technology can be used in new usb protocol, can referred to herein as be embedded in
Formula USB2(eUSB2).Signaling technology described herein can be used to the standard USB2 operation of supported protocol level.This
Outside, compared with standard USB2 physical layer framework, simplified physical layer framework is can be used in signaling technology described herein.Herein
Disclosed simplification physical layer framework can support low speed (LS) operation, at full speed (FS) operation or high speed (HS) operation.In height
It is opposite with 0.4 volt of difference signaling being used in standard USB2 during speed operation, use low swing differential signaling (such as 0.2
Volt difference signaling) operate link.During low speed or full-speed operation, simplifies PHY framework and make it possible for digital lead to
Letter scheme.For example, simplifying PHY framework can be used 1 volt of cmos circuit, this and be used in standard USB2 3.3 volts
CMOS signaling is opposite.In all-digital communication scheme, eliminate the simulated assembly being normally used in USB2, such as current source and
Operational amplifier.
Embodiment can support local mode and transponder pattern.As quoted in this article, local mode description is wherein led
The operation that both machine and device port are realized eUSB2 PHY and communicated based on eUSB2 signaling.Local mode can be by
For do not need wherein in the situation of the downward compatibility of standard USB2.For example, local mode can be used for chip to core
Piece communication, two of them chip are welded to mainboard.Transponder pattern allows eUSB2 to support mark by means of half-duplex repeater equipment
Quasi- USB2 operation.About entitled " the A Clock-Less Half-Duplex Repeater's " submitted on June 30th, 2012
Co-pending patent application sequence number _ _ _ _ further describe the transponder pattern of operation, this application is passed through with entire contents
It is incorporated herein by reference with for all purposes.
Embodiment described herein supports new equipment, and there are detection schemes, can be used for low pressure signaling protocol and lead
Cause the low-down power consumption in idle mode.Under standard USB2 specification utilizes equipment passive (passive) pull-up and host passive
It draws and carrys out detection device connection and determine operation mode.Thus, USB2 link maintains passively to be pulled up by equipment in link idle
It is passively pulled down with host and is formed by the path constant direct current (DC).Cable voltage is read out the company to determine equipment by host
Connect state.Standard USB2 is caused to consume about 600 μ W when link is in idle mode due to pull-up and pull-down-resistor
Power.New digital disconnection detection technology described herein indicated using equipment examination (ping) free time (LPM-L1 or
Hang up) during equipment exist, rather than pulled up using equipment.It, can by eliminating for the pull-up of equipment existing for detection device
To eliminate link power consumption when idle state.For example, the resulting power consumption of the result of link can reduce to by Leakage Current and be drawn
The power consumption risen.
In addition, eUSB2 agreement according to the embodiment use at full speed and low-speed handing 1 volt of signaling rather than 3.3
Volt.Compared to 3.3 volts of transistors having compared with thick grating oxide layer, the pin leakage usually with higher of 1 volt of transistor
Electric current.In order to reduce by pulling up the electric current with pull-down-resistor, the resistance of pullup resistor and pull-down-resistor can be increased.
However, the resistance of increase pullup resistor and pull-down-resistor, which will lead to actively (active) buffer, can not ignore reinforcement
Pull-up.New equipment detection scheme according to the embodiment initiatively drives eD+ using active buffer driver to upstream device
Or eD- signal wire exists with indicating equipment, rather than use pullup resistor.Therefore, it is possible to eliminate ignore the pull-up of reinforcement
The use of active buffer.In some embodiments, pullup resistor can be eliminated.
Current USB2 specification also detects portable (OTG) equipment using sideband cable, and it is general to be routed on piece
Input buffer (GIO).According to embodiment, the detection of OTG equipment can be completed by using with interior OTG testing mechanism.Cause
And the sideband cable for detecting OTG ability can be eliminated, thus reduce GIO pin-count.
Fig. 1 is the block diagram of universal serial bus structural according to the embodiment.EUSB2 framework can be used for any suitable
It except other things especially include desktop computer, laptop computer, plate and mobile phone etc. in electronic equipment.According to
Embodiment, eUSB2 framework 100 may include standard USB2 section 102 and eUSB2 section 104.Standard USB2 section 102 may include association
Discuss layer 106 and link layer 108.Protocol layer 106 is for the signal transmitting between management equipment and host.For example, protocol layer 106 is used
To determine how structured message packet.Link layer 108 is used to create and maintain communication channel (or the chain between equipment and host
Road).Link layer 108 also controls the power management state and information flow of link.In embodiment, protocol layer 106 and link layer this
The two is operated according to standard USB2 communication protocol.
EUSB2 section 104 includes unique physical layer (PHY) 110 for eUSB2 framework 100.Physical layer 110 can be with
It is docked by any suitable interface 112 with link layer 108, except other things especially such as USB2.0 Transceiver Macrocell Interface
(UTMI) and the UTMI(UTMI+ with extension) etc..
Physical layer 110 may include a pair of of eUSB2 data line 114, be referred to herein as eD+ 116 and eD- 118.
Data line is used to send signal between upstream port and downstream port.Dependent on specific operation mode, physical layer 110 is matched
It is set to using difference signaling, single ended digital communication or some combinations and sends data on data line 114, this is as below into one
What step was explained.For example, difference signaling can be used to send data when operating in high speed, and single ended digital communication can be used
To send control signal.When operating in low speed or full speed, single ended digital communication can be used to send data and control signal.
The function of eD- and eD+ and behavior may rely on the data rate of equipment and change.
Physical layer 110 can also include Serial Interface Engine (SIE) 120 to be used by protocol layer 106 for changing
USB information packet.Serial Interface Engine 120 is used for including serial input, parallel output (SIPO) block 122 will be via signal wire
114 serial datas come in received are converted into the parallel data for being sent to link layer 108.Serial Interface Engine 120
It further include parallel input, Serial output (SIPO) block 122 with the parallel data gone out for will be received from link layer 108 turn
Change the serial data for being sent on signal wire 114 into.Physical layer 110 can also include data convert circuit (DRC) 126 He
Phaselocked loop (PLL) 128 is for restoring the data received via signal wire 114.Physical layer 110 further includes many transmitters
130 and receiver 132 be used for control signal wire 114.For simplicity, single transmitter 130 is shown in FIG. 1 and connects
It is right to receive device 132.It will be appreciated, however, that physical layer 110 may include any conjunction for realizing each embodiment described herein
The transmitter 130 and receiver 132 of suitable number.Physical layer 100 is described more fully with about Fig. 2 and 3 and appended description.
Fig. 2 is the block diagram of the universal serial bus physical layer with high speed (HS), low speed (LS) and full speed (FS) ability.?
In embodiment, HS, FS and LS data rate correspond to the data rate by USB2 agreement defined.For example, during LS operation
PHY can provide the data rate of about 1.5 Mbit/s, and PHY can provide the number of about 12 Mbit/s during FS operation
According to rate, and during HS operation, PHY can provide the data rate of about 480 Mbit/s.EUSB2 PHY 200 can be with
Including both low speed/full speed (LS/FS) transceiver 202 and high speed (HS) transceiver 204.In embodiment, PHY 200 is also wrapped
Include a pair of of the pull-down-resistor 206 for being used for equipment connecting detection.LS/FS transceiver 202 and HS transceiver 204 are communicatively coupled to
EUSB2 signal wire 208 comprising eD+ 210 and eD- 212.HS transceiver 204 and LS/FS transceiver 202 may be configured to
Control selectively is taken to signal wire 208 dependent on the data rate capabilities for the upstream equipment for being connected to PHY 200.Under
Text further describes the technology for determining the data rate capabilities of upstream equipment.
LS/FS transceiver 202 may include a pair of of single ended digital transmitter 214 and a pair of of single ended digital receiver 216.This
A little components are respectively served as outputting and inputting for single-ended signaling.In single-ended signaling, each signal wire eD+ 210 and eD-
212 can send individual signal message.This is realized in contrast to the wherein LS/FS standard USB2 for operating with difference signaling.?
In difference signaling, information is sent by two complementary signals sent on a pair of of signal wire eD+ 210 and eD- 212.
The physical signal sent by signal wire 208, which is transformed into binary signal data, can be used any suitable technology come complete
At such as Non Return to Zero Inverted (NRZI).
LS/FS transceiver 202 can be digital, exist to mean to eliminate usually for USB2 LS/FS electricity
The simulated assembly on road, such as operational amplifier and current source.Single ended digital transmitter 214 and single ended digital receiver 216 can be with
Be using 1.0 volts signaling voltage operate digital CMOS (CMOS complementary metal-oxide-semiconductor) component, this be used for
3.3 volts of signalings of standard of USB2 are compared.Maintain low speed/full speed empty by the pull-down-resistor 206 realized in downstream port
Not busy state (SE0).In order to ensure arriving the rapid transfer of idle state, port should be before disabling its transmitter by bus driver
For SE0.
HS transceiver 204 can be the analog transceiver for being configured for low swing differential signaling.For example, HS transceiver can
With using 0.2 volt signaling voltage operate, this compared with 0.4 volt be used in USB2, thus data send during
Realize reduced power consumption.HS transceiver 204 may include the high speed transmitter 230 sent for data, for data receiver
High-speed receiver 232 and the detection for link state (i.e. HS activity and HS idle) squelch detector 234.It is additional
Ground, in some embodiments, HS transceiver 204 can also include that HS receiver terminates 236 to minimize the signal at receiver
Reflection, so as to cause improved signal integrity.During the HS operation mode for wherein enabling HS transceiver 204, PHY 200 makes
Data are transmitted with difference signaling and control signal can also be sent using single ended communication.
The link layer that both HS transceiver 204 and LS/FS transceiver 202 are docked by passing through interface 112 with PHY 200
108 controls.Various data and control line from interface 112 are coupled to transceiver 202 and 204.For example, as shown in Figure 2, opening
It is respectively intended to be selectively enabled LS/FS transmitter 214, LS/FS receiver 216, HS with signal 218,224,244 and 238 and connect
Receive device 232 or HS transmitter 230.Complementary drive input 240 and 242 is coupled to HS transmitter 230 for driving HS to send out
Send device that data and/or control signal are output to signal wire 208.Receiver output 246 is coupled to HS receiver 232 for connecing
Receive the data that PHY 200 is sent to via signal wire 208.The disabling when detecting the beginning of HS data packet of squelch detector 248
SE receiver 216, enables HS receiver 232 and optionally receiver terminates 236.226 and 228 coupling of positive and negative receiver output
To LS/FS receiver 216 for receiving the data for being sent to PHY 200 via signal wire 208.The input of positive and negative driver
220 and 222 are coupled to LS/FS transmitter 214 for driving LS/FS transmitter that data and/or control signal are output to letter
Number line 208.
In embodiment, device port (not shown) will have and the physical layer that is substantially similar to physical layer 200
EUSB interface.In such embodiments, both host and equipment use eUSB agreement.In embodiment, device port can be with
It is the port standard USB2 with standard USB2 physical layer.In such embodiments, transponder can be used to send from host
EUSB signal is changed into standard USB2 signal.For example, transponder may be configured to convert signals, such as equipment connection, equipment
Disconnection, data rate negotiations etc..Transponder, which can also be used to for the voltage of eUSB signal being redeveloped into, to be used in standard USB2
Voltage.About co-pending patent application sequence number _ _ _ _ further describe the operation of transponder.
Fig. 3 is the block diagram with the universal serial bus physical layer of low speed or full speed ability.As shown in Figure 3, eUSB2 object
Reason layer 300 may include digital single ended transceiver 302 and equally not include High Speed Analog transceiver.It can be with institute in Fig. 2
The eUSB PHY 200 shown is similarly run, but is not had with the ability of high speed (HS) operation.LS/FS PHY 300 can wrap
Include 302, one groups of pull-down-resistors 304 of SE transceiver and a pair of eUSB2 data line 306.
Fig. 4 is used to the timing diagram of the SYNC pattern in low speed or Full-Speed mode.SYNC pattern 400 can be with PHY
200(Fig. 2) it is used together with PHY 300(Fig. 3) to mark packet since a port is sent to another packet.Such as Fig. 4
Shown in, single ended communication can be used in SYNC pattern, is suitable for digital CMOS and operates.According to embodiment, eUSB2 passes through drop-down electricity
Resistance device 206 drives SYNC pattern to maintain logic ' 0' on eD+ 402 simultaneously on eD- 404.As shown in Figure 4, work as data line
ED+ 402 is pulled down to indicate SYNC when logic ' 0', and data line eD- 404 sends KJKJKJKK's during this time period
Pattern.
In high speed, SYNC pattern (not shown) is similar to the pattern of standard USB2, and wherein voltage swing is re-defined.
In high speed, data line eD+ 402 or eD- 404 are not kept at logic ' 0', this is because high speed utilizes difference signaling.
As replacement, the two data lines can switch SYNC pattern, such as sequence KJKJKJKK.
Fig. 5 is the timing diagram of end-of-packet (EOP) pattern in low speed or Full-Speed mode.EOP pattern 500 is used to indicate from one
A port is sent to the end of another data packet.According to embodiment, pass through the logic at eD+ ' 1' 2 of EOP pattern 500
A UI of UI and SE0 is indicated, and eD- maintains logic ' 0' by pull-down-resistor 304.Single-ended 0(SE0) wherein eD- is described
The signal condition at logic ' 0' is in eD+ both of which.EOP is sent on eD+ with the SYNC and packet sent on eD-
The three condition (J, K, SE0) of data permitting deformation USB2 packet indicates may.According to the EOP pattern pair of embodiment described herein
Than the standard USB2 that 1 UI of J will be followed to indicate by the 2 of SE0 UI in wherein EOP pattern.
In addition to voltage swing is re-defined, high speed eUSB2 EOP pattern (not shown) is similar to the sample of standard USB2
Formula.High speed EOP is indicated by 8 UI of continuous J or K.SOF EOP is indicated by 40 UI of continuous J or K.
Fig. 6 A and 6B are the exemplary timing diagrams for showing eUSB2 signal sequence.In embodiment, single-ended signaling is used for L0 mould
LS/FS packet in formula is sent.Wherein the connection between host and equipment is movable operation mode for term " L0 " description, to make
Winner's machine can be communicated with equipment.Single-ended signaling can be also used for two ports in different link states (not including L0)
Between interaction, and for host with any link state issue control message.
When LS/FS, which is coated with, to be sent, SYNC pattern 400 and bag data, which are sent eD+ simultaneously at eD- 604 and be maintained at, is patrolled
Volume ' 0' place, and the SE0 of EOP pattern 500 at eD+ by send and meanwhile eD- be maintained at logic ' 0'.When host initiates to control
When message, control message may begin at SE1.Single-ended 1(SE1) wherein eD- and eD+ both of which is at logic ' 1' for description
Signal.Difference in the signal sequence and format at the beginning between transmission of the transmission to control message of data packet allows
It is data packet or control message that equipment in L0, which distinguishes the packet received before continuing with packet,.In embodiment, downstream
Port based on it bag affairs or link state before state interpret the signaling from upstream port.
Fig. 6 A is LS/FS packet beginning (SOP) pattern 602 that downstream port (equipment) is sent to from upstream port (host)
Timing diagram.As shown in FIG, SOP pattern 602 is indicated by using eD- 604, to send SYNC pattern and bag data, together
When eD+ 606 be maintained at logic ' 0'.When all packets are sent, eD+ 606 can be used to send EOP eD- simultaneously
604 are maintained at logic ' 0'.
Fig. 6 B is the timing diagram that the control message pattern 608 of downstream port (equipment) is sent to from upstream port (host).
As depicted in figure 6b, message beginning (SOC) pattern is controlled when driving SE1 pulse 610 in certain period of time when downstream port
608 are indicated as the signature (signature) for SOC message.And then SE1 pulse 610, control message can be used a series of
Pulse is encoded in active window 612.During the active window 612, eD+ 606 can be driven at logic ' 1'
Many pulses 614 simultaneously can be activated on eD- 604.The number of pulse 614 can determine the property of control message.?
The copending Patent Shen of entitled " the Explicit Control Message Signaling " that submits on June 30th, 2012
Please sequence number _ _ _ _ in further describe control message signaling, this application is incorporated herein by reference with entire contents to be used for
All purposes.
In embodiment, single-ended signaling is also used for host and equipment interaction during energization, resetting, hang-up and L1.
The interim disabling link activity of equipment is sent to limit the control of power consumption from host as it is used herein, hanging up description
Message.When in hanging up, equipment may still receive recovery control message or replacement control message from host.Such as this
Used in text, L1 describes the mode that can similarly execute in some eUSB2 and USB2 embodiments with hang-up.Such as this paper institute
It uses, restores control message of the description from host, signals device reenters L0 mode from hang-up or L1.Such as
Used herein, reset describe is from host is sent equipment to be arranged in the control message defaulted in non-configuration status.
Fig. 7 is the timing diagram of low speed ties up the signal that continues.LS dimension after 700 be periodically sent during L0 it is low to prevent
Fast peripheral equipment enters the control message of hang-up.As seen in Figure 7, dimension signal 700 may include SE1 pulse 702, wherein exist
There is no the active window 704 and eop signal 708 on the eD+ 705 of pulse on eD- 706.
Equipment disconnects mechanism
As explained above, standard USB2 using equipment pull-up and host downdraw machine come operating at LS/FS or
Person L1 or hang up in when detection device connection or equipment disconnect.It is formed by from pullup resistor and pull-down-resistor 206
The cable voltage of divider network is read by host to determine equipment connection status.This cause in LS/FS or in L1 or
Person wastes constant DC power in hang-up.
By the present invention in that link eliminates idle power in single-ended 0(SE0) during idle state, in the situation
In two data cables eD+ and eD- be held at ground by downstream port.Thus, it is consumed during idle state seldom idle
Power does not consume idle power.During the standard USB2 idle state for being referred to as " idle J ", enables pull-up and pull down this
The two, so as to cause waste power.In embodiment, the pull-up from equipment can be eliminated.When from recovery is hung up, host is asked
Ask the examination of equipment sending device to affirm connectivity again.If host does not receive the digital ping signa from equipment,
Disconnected event will be detected.
Fig. 8 is the timing diagram for the equipment disconnection detection technology of full speed or low-speed handing during L0.Such as institute in Fig. 8
Show, numeral examination mechanism 800 can be used to complete the equipment disconnection detection during the L0 at LS/FS operation.Equipment examination 802 can
To be defined as being in 1 UI logic ' 1' at the eD- in FS or LS mode.As shown in Figure 8, it and then wraps detecting
After eop signal 806 on eD+, upstream port can limit (example in the stipulated time when detecting the beginning of eop signal 802
Such as the sending device examination 802 on eD- 804 in 3 UI).Dependent on the phase between long-range bit clock and local bit clock
Position and frequency shift (FS), equipment examination 802 can actually be sent out to evening earlyly and as more than two UI as 1 UI
It send.After numeral examination 802 is sent back to host, equipment can enter idle mode 812.In order to confirm connectivity, on
Swimming port can the periodically sending device examination 802 on each frame period.Sending device examination 802 is permitted in a periodic fashion
Perhaps host is even perceived equipment when there is no the data service between host and equipment and is existed, thus prevents equipment from being broken
It opens.If it does not receive any packet, and does not receive any equipment examination within three successive frame periods, then downstream port
It can state that equipment disconnects during L0.
In embodiment, downstream (host) port is executing disconnection detection from L1 or during hanging up recovery.In response, on
It swims (equipment) port and sends digital ping signa when restoring to state connection status during L1 or hang-up.For being in L1
Or for sending equipment of the numeral examination to state connection when hanging up, device drives eD+ is to send numeral examination.For being in
L1 or hang up when send numeral examination with state connection equipment for, device drives eD- is to send numeral examination.
Fig. 9 is the timing diagram for the equipment disconnection detection technology of the high-speed mode during L0 state.Standard USB2 HS makes
With analogy method come detection device disconnection.Specifically, standard USB2 SOF(frame start) EOP(end-of-packet) during use
Envelope detected is to be used for disconnection detection.The requirement analog comparator and accurate reference voltage of envelope detected.In order to promote
The disconnection detection of the type, the EOP of SOF are extended to 40 UI so that envelope detector has sufficient time in equipment
Disconnected event is detected in the case where being disconnected.In embodiment, the L0 that eUSB is completed using simulation examination mechanism 900 with high speed
The equipment disconnection detection of period.Equipment examination 902 can periodically be sent during L0 is idle by equipment, to announce depositing for it
And prevent from being disconnected.By using numeral examination mechanism rather than envelope detected, can remove such as envelope detector it
The various simulated assemblies of class, so as to cause simplified physical layer framework.For the disconnection in the L1 for high-speed equipment or hang-up
The mechanism of detection can be identical as full speed.
As shown in Figure 9, data packet 904 is completed to send at t0, and is taken over by eop signal 906.At t1, EOP letter
Numbers 906 complete.At t2, if other activities do not occur, equipment can check 902 with sending device with downstream (host) end
Its presence of mouth bulletin.Equipment examination 902 may include 8 UI of continuous J or K.At t3, equipment examination 902 is completed to send.
If the transmitter of upstream port was in the L0 free time, upstream port can be with specific time interval (example when in L0
Such as, every micro-frame period of 125 μ s) send at least one equipment examination 902.If it is in three continuous micro-frame periods not from setting
Standby to receive any packet or examination, then downstream port can state the disconnection of equipment.
In local mode, upstream equipment may not be required that reporting device disconnects during L1 or hang-up.This allows to set
It is standby to make the complete power down of transmitter during the power management state and maximize power save.When recovered, upstream port can
To send numeral examination and downstream port can execute disconnection detection routine.
When operating in transponder pattern, equipment, which disconnects, to be detected by transponder and is reported to host.When in transponder
When being operated in mode, reporting device it can be disconnected in hang-up or L1.When transponder detects the disconnection thing of standard USB2 equipment
When part, message will be communicated to the port host eUSB2, two of them signal wire by single-ended disconnection signaling (SEDISC) by transponder
Both eD+ and eD- are driven to logic ' 1' in the stipulated time measures.Once host observes SEDISC, then link state machine
Connecting link state will be transferred to from hang-up/L1 link state.About co-pending patent application sequence number _ _ _ _ further retouch
Used disconnection process during having stated transponder pattern.
It should be understood that equipment disconnection detection technology described herein is practiced without limitation to only eUSB2 realization.In embodiment
In, it is used any defeated in the process that disconnection detection technology described above can be applied in advanced deep-submicron
Enter/export (I/O) standard or supports any I/O standard of multiple data rates and operation mode.
Equipment connection and operation mode detection
Equipment connecting detection makes host port can determine when equipment is coupled to host port.The detection of equipment connection
Further relate to the process for the data rate capabilities for enabling host and equipment to state them to each other, such as host and/or equipment
It is with LS ability, FS ability and/or HS ability.
As explained above, passively pulled up using the standard USB2 of 3.3V signaling using equipment and host passively pull down come
Detection device connection.Host port can have the 15k Ω drop-down enabled with default behavior.When no device is connected, two
A data cable D+ and D- is pulled low.When connected, equipment will have 1.5k Ω pull-up on any cable, this depends on and sets
Standby data rate.Host can be by judging which cable is raised data rate to determine equipment.Additionally, standard
USB2 specification instruction detects the ability of portable (OTG) equipment by being referred to as the sideband cable of ID pin, is connected to
On piece GIO.For using the operation of lower signaling voltage, standard connects detection scheme may not be it is feasible, this be because
It must obviously be reinforced for the resistance of pull-down-resistor and pullup resistor, and active buffer may not be ignored
Pullup resistor.
In embodiment, eUSB2 connection event by using device port LS/FS transmitter 214(Fig. 2) Lai Shengcheng,
Signal wire (eD+ 210 or eD- 212) is driven to logic ' 1'.In addition, during connecting with connecting detection, 210 He of eD+
ED- 212 forms double simplex links to allow host and equipment interactively with each other in the case where not causing contention.For example, if FS
Or HS equipment is connected, then eD+ will be driven to logic ' 1' by the FS transmitter at equipment side, while eD- makes to pull down to remain to patrol
Volume ' 0', and enable any at the eD- that the FS receiver at equipment side is driven with the FS transmitter detected by host computer side
State changes.In embodiment, the passive pullup resistor on device port can be eliminated.Additionally, equipment detection scheme
1000 may include in-band mechanisms to detect OTG ability without using sideband cable, thus reduce GIO pin meter
Number.
Figure 10 is the exemplary timing diagram for showing equipment connecting detection technology.In the example shown in Figure10, interaction hair
Life is between the downstream port and upstream port in the local mode of full speed.The other embodiments that the process is considered may include
The friendship between the upstream port on downstream port and dual-role device on low speed data rate or peripheral transponder pattern
Mutually.
At t0 or when being powered, port can enable their pull-down-resistor.Downstream port can be in eD+ and eD-
Its transmitter is disabled at both and enables its receiver.
At t1, eD+ or eD- can be driven to logic ' 1' by upstream port, this is depended on will be by upstream port statement
Speed.For example, as shown in Figure 10, if equipment is at full speed or high speed is enabled, it can only eD+ at driving logic '
1' and the receiver that it is enabled at eD-, are not driven by upstream port.If upstream port only has low speed capabilities,
It can drive logic ' 1' at eD- and enable its receiver at eD+, not driven by upstream port.
At t2, downstream port can state that equipment connects and confirms equipment.Confirmation process may rely in the time
The ability for the upstream equipment that t1 is stated and change.For example, if downstream port is in TATTDBIt is examined at eD+ in duration
It measures logic ' 1' and detects logic ' 0' at eD-, then as shown in Figure 10, downstream port is in TACKDriving is patrolled at inherent eD-
Volume ' 1'.If it is in TATTDBDetect logic ' 0' at eD+ and detect logic ' 1' at eD- in duration, then it
TACKIt is interior to drive logic ' 1' for eD+ and state that low-speed device connects.In other words, handshake mechanism is configured as double either simplex
Link, to ensure be used to state to drive on the opposite signal wire of its existing signal wire to confirm with upstream equipment.In Figure 10
Shown in scene, there are signals for receiving device on eD+ for downstream port.Thus, handshake is laterally across D-.With the party
Formula, link partner not simultaneously driving signal cable, thus avoid cable contention.In standard USB2, the activity-driven of host
Device, which is expected into, ignores cable state, is maintained at weak high potential by the passive pull-up of upstream equipment.
Equally at t2, upstream port can be responded when receiving confirmation from downstream port.If upstream port
It is full speed or high speed, then drives logic ' 0' when it can detect host acknowledgement at eD- at eD+, disable its transmission
Device, and its receiver of enabling also at eD+, thus the connection that terminates.
In wherein host function by the connected situation of transponder in transponder pattern, eD+ can constantly by
Logic ' 1' is driven to until transponder detects logic ' 0' at eD-, this is had been detected by dual role host port
When the host function being connect with its micro- AB receptor.If downstream port is in TATTDBIt is examined at eD+ in duration
Measure logic ' 1' and detect logic ' 0' at eD-, then downstream port can by as in Figure 10 as shown in t2
Logic ' 1' is driven to start to confirm at eD-.By TACKDuring the indicated period, downstream port can continue to monitor eD
+.If eD+ keeps logic ' 1' at the confirmation end at t3, downstream port can state that host function is connected.If
Downstream port has been detected by transfer before t3 as the eD+ of ' 0', then it can state that FS or HS equipment is connected.
At t4, downstream port can issue resetting message.Upstream port can reset its control when detecting SE1
Message decoder.
At t5, downstream port can be by maintaining SE0 to continue to reset based on pull-down-resistor.Upstream port can be with
Resetting is completed to decode and enter resetting.
At t6, if equipment is low speed or full speed, downstream port can drive EOP with the resetting that terminates.If set
Standby is only low speed or full speed, then equipment monitor resetting is until its completion.At t7, downstream port can by driving SE0 come
Termination resets and enters resetting reduction.At t8, port prepares for initializing.
Back to t6, if equipment is it is stated that full speed ability, speed negotiation start at t6 whether to determine equipment
Enabled for high speed.High-speed negotiation is described below about Figure 11.
Figure 11 is the exemplary timing diagram for showing the wherein equipment connecting detection scheme of equipment statement high speed capability.Speed association
Quotient is completed using single-ended signaling, when instruction high speed is enabled since equipment to when downstream port confirmation and to
Equipment is when its receiver termination is turned on and prepares for high speed operation.Until the t6 of Figure 11, equipment connection inspection
Survey operation is all identical as the situation in low speed/full speed, this is described about Figure 10.
If equipment is high speed, following operation occurs.At t6, after upstream port detects resetting, equipment
Drive logic ' 1' to represent equipment chirp (Chirp) at eD+, if it is if high speed is enabled.Downstream and upstream port this
Optional receiver at the two terminates 236(Fig. 2) it is disabled until t9.
At t7, when downstream Port detecting is to after equipment chirp, downstream port start to drive at eD- logic ' 1' with
It represents host chirp and prepares downstream PHY 200 for high speed operation.
At t8, upstream port should make the preparation of its high speed PHY 200 for the operation after detecting host chirp.For
Preparation upstream port is to be used for high speed operation, and eD+ is driven to logic ' 0' by upstream port, after TSE0_DR at eD+
Its single-ended transmitters are disabled, and enable its single ended receiver at eD+.
At t9, downstream port drives logic ' 0' at eD- to signal the completion of velocity measuring, and PHY is quasi-
It is ready for use on high speed operation.Equally at t9, upstream port terminated by enabling its optional receiver and squelch detector into
Enter L0.
At t10, downstream port termination resetting.At this point, link is in L0 state.
It should be understood that the only eUSB2 that is practiced without limitation to of equipment connection described herein and operator scheme detection technique is realized.
In embodiment, used in disconnection detection technology described above can be applied in during advanced deep-submicron
Any input/output (I/O) standard or any I/O standard for supporting multiple data rates and operation mode.
Although describing some embodiments referring to specific implementation, it is possible that other, which are realized according to some embodiments,
's.Additionally, the arrangement and order of illustrate in the figure or circuit element being described herein or other features are not required to
It to be arranged with illustrated and description ad hoc fashion.Many other arrangements are possible according to some embodiments.
In each system shown in the figure, element can all have in some cases identical appended drawing reference or
Different appended drawing references implies that representative element can be different or similar.However, element can be enough flexibly to have
Difference is realized and is worked together with illustrated herein or description some or all of system.Various elements shown in figure
It can be same or different.Which is referred to as first element and which is referred to as second element and is arbitrary.
In the specification and in the claims, term " coupling " and " connection " and their derivative form can be used.
It should be understood that these terms are not intended as mutual synonym.On the contrary, in a particular embodiment, " connection " can be used to
Indicate that two or more elements are in directly physically or electrically gas contact each other." coupling " may mean that at two or more elements
In directly physically and electrically gas contacts.However, " coupling " may also mean that two or more elements are not in direct contact with each other,
But it still cooperates or interacts with.
Embodiment is realization or example of the invention.In the description to " embodiment ", " one embodiment ", " some realities
Apply example " or the reference of " other embodiments " mean that in conjunction with the embodiments described a particular feature, structure, or characteristic is included
It at least some embodiments of the invention, but may not be including being in all embodiments." embodiment ", " one embodiment " or
Occur being not necessarily all referring to identical embodiment everywhere in " some embodiments ".
It is not that all components described and illustrated herein, feature, structure, characteristic etc. require to be included in specifically
In embodiment or multiple embodiments.For example, if specification statement " can with ", " possibility ", " can " or " meeting " include component, spy
Sign, structure or characteristic, then be not required for including the specific components, feature, structure or characteristic.If specification or claim
Book quotes "a" or "an" element, then this is not meant to that there is only an elements.If specification or claims draw
With " additional " element, then it is not precluded that there are more than one add ons.
Although may flow chart used herein or state diagram embodiment is described, the present invention is not limited to
These figures or corresponding description herein.For example, process may not move through each illustrated frame or state or
Definitely with same order illustrated and described herein.
The present invention is not limited to particular details listed hereins.In fact, the those skilled in the art for having benefited from the disclosure will
Understand, many other deformations can be made to above description and attached drawing within the scope of the invention.Thus, including to any of its
Modified following following claims limits the scope of the invention.
Claims (28)
1. a kind of method of detection input/output (I/O) equipment connection, comprising:
I/O equipment is physically coupled to host port by the first signal wire and second signal line;
Via the active buffer of the I/O equipment rather than via passive pullup resistor by first signal wire or described
Second signal line is driven to high potential;And
By not mentioned by another signal wire that the active buffer of the I/O equipment is driven to high potential from host to equipment
For confirmation signal.
2. according to the method described in claim 1, wherein the host and the I/O equipment pass through universal serial bus coupling
It closes.
3. according to the method described in claim 2, wherein the I/O equipment does not include being used to indicate existing for equipment passively to pull up
Resistor.
4. according to the method described in claim 1, being first signal wire or the second signal line quilt including depending on
The active buffer of the I/O equipment is driven to high potential to determine the data rate capabilities of the equipment.
5. according to the method described in claim 4, wherein if first signal wire is delayed by the active of the I/O equipment
It rushes device and is driven to high potential, then the data rate capabilities of the I/O equipment are declared as (FS) at full speed or high speed (HS), and such as
Second signal line described in fruit is driven to high potential by the active buffer of the I/O equipment, then the data of the I/O equipment
Rate capacity is declared as low speed (LS).
6. according to the method described in claim 5, wherein if the data rate capabilities of the I/O equipment are declared as at full speed
(FS) or high speed (HS), then the I/O equipment to the host send digital signal to state HS ability.
7. according to the method described in claim 1, including on first signal wire or the second signal line from the I/O
Equipment sends in-band message to state that the I/O equipment is set as universal serial bus (USB) portable (OTG) to the host
It is standby.
8. a kind of host computing device, comprising:
Host port comprising physical layer is to drive the signal on the first signal wire and second signal line for carrying out with equipment
Communication;
Wherein the host port has been delayed by the active of equipment by detecting first signal wire or the second signal line
Rush device rather than passive pullup resistor is driven to high potential to detect the connection of the equipment;And
When detecting the equipment, the host port is not by being driven to high electricity by the active buffer of the equipment
Another signal wire of position to provide confirmation signal to the equipment.
9. host computing device according to claim 8, wherein the host port is the end universal serial bus (USB)
Mouthful.
10. host computing device according to claim 8, wherein the host dependent on be first signal wire or
The second signal line is driven to high potential by the active buffer of the I/O equipment to determine the data speed of the equipment
Rate ability.
11. host computing device according to claim 8, wherein if first signal wire is described in the equipment
Active buffer is driven to high potential, then the host determines that the data rate capabilities of the equipment are full speed (FS) or high speed
(HS), and if the second signal line is driven to high potential, the host by the active buffer of the equipment
The data rate capabilities for determining the equipment are low speed (LS).
12. host computing device according to claim 11, wherein if the host determines the data speed of the equipment
Rate ability is (FS) or high speed (HS) at full speed, then the host listens the digital signal from the equipment to be with the determination equipment
It is no that there is HS ability.
13. host computing device according to claim 11, wherein if the equipment be universal serial bus (USB) just
Formula (OTG) equipment is taken, then the host receives in band on first signal wire or the second signal line from the equipment
Message.
14. a kind of periphery I/O equipment, comprising:
Device port comprising physical layer is to drive the signal on the first signal wire and second signal line to be used for and Framework computing
Equipment is communicated;
Wherein the device port by using active buffer rather than passive pullup resistor by first signal wire or
The second signal line is driven to high potential to indicate to exist;And
The device port waits another letter by not being driven to high potential by the active buffer of the device port
The confirmation signal that number line is received from the host computing device.
15. periphery I/O equipment according to claim 14, wherein the device port is the end universal serial bus (USB)
Mouthful.
16. periphery I/O equipment according to claim 14, wherein the device port does not include to indicate existing quilt
Dynamic pullup resistor.
17. periphery I/O equipment according to claim 14, wherein the device port is by selecting first signal wire
Or which of described second signal line is driven to high potential by the active buffer to state the number of the device port
According to rate capacity.
18. periphery I/O equipment according to claim 17, wherein if first signal wire is by the active buffer
Be driven to high potential, then the data rate capabilities of the device port be declared as at full speed (FS) or high speed (HS), and if
The second signal line is driven to high potential by the active buffer, then the data rate capabilities of the I/O equipment are declared
For low speed (LS).
19. periphery I/O equipment according to claim 18, wherein the device port has HS data rate capabilities, and
And after statement full speed (FS) or high speed (HS) ability, the device port sends digital signal to the host to state HS
Ability.
20. periphery I/O equipment according to claim 14, wherein the periphery I/O equipment is universal serial bus (USB)
Portable (OTG) equipment, and the device port on first signal wire or the second signal line to the host
It calculates equipment and sends in-band message to request to connect as usb host.
21. a kind of device of detection input/output (I/O) equipment connection, comprising:
For I/O equipment to be physically coupled to the component of host port by the first signal wire and second signal line;
For the active buffer via the I/O equipment rather than via passive pullup resistor by first signal wire or
The second signal line is driven to the component of high potential;And
For another signal wire by not being driven to high potential by the active buffer of the I/O equipment from host to setting
It is standby that the component of confirmation signal is provided.
22. device according to claim 21, wherein the host and the I/O equipment pass through universal serial bus coupling
It closes.
23. device according to claim 22, wherein the I/O equipment does not include being used to indicate on passive existing for equipment
Pull-up resistor device.
24. device according to claim 21, including being used to depend on is first signal wire or second letter
Number line high potential is driven to by the active buffer of the I/O equipment come determine the equipment data rate capabilities portion
Part.
25. device according to claim 24, wherein if first signal wire is by the active of the I/O equipment
Buffer is driven to high potential, then the data rate capabilities of the I/O equipment are declared as (FS) at full speed or high speed (HS), and
If the second signal line is driven to high potential, the number of the I/O equipment by the active buffer of the I/O equipment
Low speed (LS) is declared as according to rate capacity.
26. device according to claim 25, wherein if the data rate capabilities of the I/O equipment are declared as at full speed
(FS) or high speed (HS), then the I/O equipment to the host send digital signal to state HS ability.
27. device according to claim 21, including on first signal wire or the second signal line from
The I/O equipment sends in-band message to state that the I/O equipment is portable as universal serial bus (USB) to the host
(OTG) component of equipment.
28. a kind of computer-readable medium, is stored thereon with instruction, described instruction makes to calculate equipment execution root when executed
According to method of any of claims 1-7.
Priority Applications (1)
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CN201710722951.3A CN107688550B (en) | 2012-06-30 | 2013-06-27 | Device connection detection |
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US13/539376 | 2012-06-30 | ||
US13/539,376 US8683097B2 (en) | 2012-06-30 | 2012-06-30 | Device connect detection |
PCT/US2013/048334 WO2014004916A1 (en) | 2012-06-30 | 2013-06-27 | Device connect detection |
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CN201710722951.3A Division CN107688550B (en) | 2012-06-30 | 2013-06-27 | Device connection detection |
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CN104321757A CN104321757A (en) | 2015-01-28 |
CN104321757B true CN104321757B (en) | 2019-05-17 |
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CN (2) | CN107688550B (en) |
TW (3) | TWI506447B (en) |
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US8683097B2 (en) | 2012-06-30 | 2014-03-25 | Intel Corporation | Device connect detection |
US9811145B2 (en) * | 2012-12-19 | 2017-11-07 | Intel Corporation | Reduction of idle power in a communication port |
US9606955B2 (en) * | 2014-02-10 | 2017-03-28 | Intel Corporation | Embedded universal serial bus solutions |
US9727514B2 (en) * | 2014-12-09 | 2017-08-08 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Integrated circuits with universal serial bus 2.0 and embedded universal serial bus 2 connectivity |
US9836420B2 (en) | 2014-12-09 | 2017-12-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Integrated systems with universal serial Bus 2.0 and embedded universal serial Bus 2 connectivity |
US9843436B2 (en) * | 2015-06-27 | 2017-12-12 | Intel Corporation | Flexible interconnect architecture |
US20170063700A1 (en) * | 2015-08-26 | 2017-03-02 | Qualcomm Incorporated | Systems and methods for rate detection for soundwire extension (soundwire-xl) cables |
MY191604A (en) | 2015-12-25 | 2022-07-01 | Intel Corp | State detection mechanism |
JP7069931B2 (en) * | 2018-03-27 | 2022-05-18 | セイコーエプソン株式会社 | Circuit equipment, electronic devices and cable harnesses |
US10657089B2 (en) * | 2018-07-30 | 2020-05-19 | Texas Instruments Incorporated | Embedded universal serial bus 2 repeater |
US11068428B2 (en) * | 2018-08-16 | 2021-07-20 | Texas Instruments Incorporated | Adjustable embedded universal serial bus 2 low-impedance driving duration |
US11378600B2 (en) * | 2020-07-20 | 2022-07-05 | Nxp B.V. | Squelch and disconnect detector |
US20220206983A1 (en) * | 2020-12-30 | 2022-06-30 | Texas Instruments Incorporated | Low Power Embedded USB2 (eUSB2) Repeater |
US20230111096A1 (en) * | 2021-10-13 | 2023-04-13 | Texas Instruments Incorporated | Usb suspend mode in isolated usb repeater |
CN114996187A (en) * | 2022-05-06 | 2022-09-02 | 东莞市步步高教育软件有限公司 | OTG function control method and device, computer equipment and storage medium |
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US7707321B2 (en) | 1999-08-04 | 2010-04-27 | Super Talent Electronics, Inc. | Chained DMA for low-power extended USB flash device without polling |
US7043587B2 (en) | 2001-09-20 | 2006-05-09 | Lenovo (Singapore) Pte. Ltd. | System and method for connecting a universal serial bus device to a host computer system |
JP3778291B2 (en) * | 2004-05-24 | 2006-05-24 | セイコーエプソン株式会社 | Transmission circuit, data transfer control device, and electronic device |
US9081585B1 (en) * | 2006-03-31 | 2015-07-14 | The Mathworks, Inc. | Interfacing a device driver with an application using a virtual driver interface and a strategy |
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US8683097B2 (en) | 2012-06-30 | 2014-03-25 | Intel Corporation | Device connect detection |
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TWI506447B (en) | 2015-11-01 |
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US8683097B2 (en) | 2014-03-25 |
WO2014004916A1 (en) | 2014-01-03 |
TW201727505A (en) | 2017-08-01 |
CN104321757A (en) | 2015-01-28 |
CN107688550A (en) | 2018-02-13 |
TWI582603B (en) | 2017-05-11 |
US20140006654A1 (en) | 2014-01-02 |
TWI637273B (en) | 2018-10-01 |
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