CN104320615A - Intelligent video security and protection system and signal processing method thereof - Google Patents
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Abstract
The invention provides an intelligent video security and protection system and a signal processing method thereof. The system comprises a video analysis front end and a central video server, wherein the video analysis front end comprises a video input interface, a control module and a video output interface; the video input interface is used for deserializing a high-speed SDI (Serial Digital Interface) video signal into a digital video stream signal meeting BT.656 standard; the control module is used for performing preprocessing and video behavior analysis on the digital video stream signal and outputting an IP (Internet Protocol) video stream signal; the video output interface is used for transmitting the IP video stream signal to the central video server. Compared with the prior art, the system and the method have the advantages that multiple targets and multiple rules can be effectively realized aiming at real-time high-definition video and the video behavior analysis is simultaneously performed. In addition, great use of stream line operation for an algorithm is realized apart from the use of the parallel processing characteristic of an FPGA (Field Programmable Gate Array), and the data throughput of processing is improved by using a mode that the speed is increased by reducing the area.
Description
Technical field
The present invention relates to the technical fields such as the monitoring of a kind of public safety, Computer Vision, computer vision, artificial intelligence, particularly relate to a kind of based on the intelligent video safety-protection system of FPGA-SOC chip and the signal processing method for this safety-protection system.
Background technology
Current safety-protection system has turned to digital security from simulation security protection gradually.Following safety-protection system trend is intelligent, high definition digital, networking.Wherein, intelligent solution is important component part and an urgent demand of following security protection.In brief, intelligent security protection refers to and adopts the professional knowledge such as computer vision, artificial intelligence to carry out technical finesse to video image, the information such as attribute, feature, the direction of motion of evaluating objects judges whether target meets the rule of setting, whether send alarm signal etc., thus event is processed in time, improve the reaction speed of emergency event.
In existing safety-protection system, most of video monitoring still adopts the monitoring scheme of passive type.Such as, carry out the judgement of security protection behavior in service centre by professional's monitor scope image, or the video segment afterwards transferring storage carries out the mode of manual analysis video.Certainly, the workload of above-mentioned monitor mode is comparatively large, and fatiguability, easily causes failing to report or reporting by mistake of video behavior.By contrast, intelligentized Video Analysis Technology has given full play to the initiatively property monitored needed for safety-protection system, effectively can reduce the workload of professional, and improves the accuracy of reporting to the police, and reduces failing to report or reporting phenomenon by mistake of video behavior.
In general, the current realization of intelligent video analysis technology in safety-protection system, is mainly divided into two kinds of modes: one is based on the analysis of back-end services pure software processes, and another kind is at headend equipment instant analysis.The weak point of front a kind of scheme is, when video flowing number of passages is large, the video data volume of server end Water demand is also very big, and the analysis efficiency of pure software can obviously decline, and cannot meet the demand of safety-protection system real-time analysis and warning.What the current overwhelming majority of rear a kind of scheme adopted is based on DSP (Digital Signal Processor, digital signal processor) realize, this implementation method in the face of HD video, multiple target, more rules video analysis time, efficiency and flexibility ratio limited.Such as, for the resolution of 2560*2048, the 5M pixel video of 15 frames (Frames Per Second, FPS) per second, even if adopt high-end dsp chip, by restrictions such as DSP process core disposal ability, clock frequencies, also cannot process.In addition, for multiple target, more rules and complex operation situation, because the multitask executive capability of the integrated video processing unit of DSP core is limited, many reasons of serial process mechanism are added, still limited to the data-handling capacity of video stream signal.
In view of this, how to design a kind of intelligent video safety-protection system, or existing intelligent video safety-protection system is improved, to overcome above-mentioned defect of the prior art, improve the data-handling capacity of video stream signal, meeting the demand of intelligent safety and defence system real-time analysis and warning, is a person skilled problem urgently to be resolved hurrily.
Summary of the invention
For the above-mentioned defect that intelligent video safety-protection system of the prior art exists in the processing speed and disposal ability of video stream signal, the invention provides a kind of based on the intelligent video safety-protection system of FPGA-SOC chip and the signal processing method for this safety-protection system.
According to one aspect of the present invention, provide a kind of intelligent video safety-protection system based on FPGA-SOC, wherein, described intelligent video safety-protection system comprises video analysis front end and centered video server, and described video analysis front end comprises:
Video input interface, for the digital video stream signal unstringing high speed SDI vision signal for meeting BT.656 standard;
Control module, comprises FPGA-SOC chip, and described control module couples mutually with described video input interface, for carrying out preliminary treatment and video behavioural analysis to described digital video stream signal, and the IP video stream signal of standard after output processing; And
Video output interface, couples mutually with described control module, for described IP video stream signal is sent to described centered video server,
Wherein, described centered video server, for receiving described IP video stream signal, configures the video analysis rule of described video analysis front end, and monitors the comprehensive video stream after described video analysis front-end processing.
An embodiment wherein, described FPGA-SOC chip also comprises logic module and processing module, described logic module is for receiving described digital video stream signal, and carry out video image preliminary treatment and video analysis process to described digital video stream signal, and by the memory of the video data after process stored in system; Wherein, described processing module reads the video data after described process from described memory, movement locus extraction and judgement are carried out to it, and judged the legitimacy of motor behavior by comparing motion target trajectory and the video analysis rule configured, and then final IP video stream signal is sent to centered video server by network.
An embodiment wherein, described processing module has arm processor, dma controller, first memory controller, interrupt control unit and peripheral interface module, described arm processor couples mutually with described interrupt control unit and described first memory controller respectively, and described peripheral interface module couples mutually with described dma controller and described interrupt control unit.
An embodiment wherein, described peripheral interface module for exporting described IP video stream signal, and sends and/or receives GPIO sensor alarm signal.
An embodiment wherein, described logic module has video image pretreatment unit, video analysis unit, video compressing unit, second memory controller and multiple VDMA IP kernel, described video image pretreatment unit is coupled to described first memory controller via a VDMA IP kernel, described video analysis unit is coupled to described video image pretreatment unit and is coupled to described first memory controller via the 2nd VDMA IP kernel, described video compressing unit is coupled to described video image pretreatment unit and is coupled to described first memory controller via the 3rd VDMA IP kernel.Described video image pretreatment unit carries out image color space conversion, image enhaucament filtering, electronic steady image, noise filtering, the value process of image ash and/or binary conversion treatment to received video flowing.Described video analysis unit carries out the parallel processing of many videos rule of conduct to through pretreated digital video by intelligent vision algorithm; H.264, described video compressing unit compresses the video flowing including result.
An embodiment wherein, described peripheral interface module is I2C, UART, SPI, ETH or CAN communication interface.
An embodiment wherein, described arm processor for supporting ONVIF security protection interface protocol, and supports HTTP, FTP or RTP procotol.
An embodiment wherein, described video analysis front end also comprises DDR SDRAM and a 2nd DDR SDRAM, and wherein, a described DDR SDRAM is coupled to described processing module, and described 2nd DDR SDRAM is coupled to described logic module.
An embodiment wherein, when video stream data being transferred to memory by VDMA, set three different frame of video buffer memorys, VDMA is set to PARK mode of operation, thus by the switching between the operation of application program controlling DMA and different frame of video buffer memorys.
An embodiment wherein, the vision signal of SD-SDI, HD-SDI or 3G-SDI that described high speed SDI vision signal gathers for high definition industrial camera.
According to another aspect of the present invention, provide a kind of signal processing method for intelligent video safety-protection system, described intelligent video safety-protection system comprises video analysis front end and centered video server, and wherein, described signal processing method comprises:
The digital video stream signal that high speed SDI vision signal is unstringed as meeting BT.656 standard by described video analysis front end;
Preliminary treatment and analysis are carried out to described digital video stream signal in described video analysis front end, and the IP video stream signal of standard after output processing;
Described IP video stream signal is sent to described centered video server by described video analysis front end; And
Described centered video server receives described IP video stream signal, configures the video analysis rule of described video analysis front end, and monitors the comprehensive video stream after described video analysis front-end processing.
An embodiment wherein, described video analysis front end comprises FPGA-SOC chip, described FPGA-SOC chip comprises logic module and processing module, described logic module is for receiving described digital video stream signal, and carry out video image preliminary treatment and video analysis process to described digital video stream signal, and by the memory of the video data after process stored in system; Described processing module reads the video data after described process from described memory, movement locus extraction and judgement are carried out to it, and judged the legitimacy of motor behavior by comparing motion target trajectory and the video analysis rule configured, and then final IP video stream signal is sent to described centered video server by network.
An embodiment wherein, described logic module also for described logic module also for perform: pretreatment operation, for received video flowing is carried out image color space conversion, image enhaucament filtering, electronic steady image, noise filtering, image ash value process and/or binary conversion treatment; Video analysis operates, for carrying out the parallel processing of many videos rule of conduct to through pretreated digital video by intelligent vision algorithm; H.264, video compression operation, for compressing the video flowing including result.
An embodiment wherein, described video analysis front end also comprises one first Double Data Rate synchronous DRAM DDR SDRAM and the 2nd DDR SDRAM, wherein, a described DDR SDRAM is coupled to described processing module, and described 2nd DDR SDRAM is coupled to described logic module.
Adopt the intelligent video safety-protection system based on FPGA-SOC chip of the present invention and signal processing method thereof, the digital video stream signal that high speed SDI vision signal is unstringed as meeting BT.656 standard by the video input interface of video analysis front end, control module is connected with video input interface and carries out preliminary treatment and analysis to digital video stream signal, the IP video stream signal of the standard after output processing, video output interface is connected with control module and IP video stream signal is sent to centered video server, and then centered video server receives IP video stream signal, the video analysis rule of configuration video analysis front end, and the comprehensive video stream after monitor video analysis front-end processing.Compared with prior art, the present invention effectively can realize multiple target, more rules for real-time high-definition video (1080P, 30fps/60fps) and carries out video analysis simultaneously.In addition, for effectively improving the implementation efficiency of video analysis algorithm, the realization of algorithm, except the parallel behavior utilizing FPGA, is used pile line operation by the present invention in a large number, and takes area to exchange the mode of speed for improve the data throughput of process.Moreover video analysis algorithm and embedded system control to be completed by a FPGA-SOC integrated chip, decrease hardware cost, reduce system power dissipation.The present invention is applicable to common monitoring field, as the occasion that traffic, community, airport, square, oil field, prison, museum etc. need Timeliness coverage anomalous event linkage to report to the police.In addition, the video analysis front end of safety-protection system of the present invention can be used for integrated intelligent video analysis camera shooting integrated machine.
Accompanying drawing explanation
Reader, after having read the specific embodiment of the present invention with reference to accompanying drawing, will become apparent various aspects of the present invention.Wherein,
Fig. 1 illustrates the structural representation of the intelligent video safety-protection system based on FPGA-SOC according to an embodiment of the present invention;
Fig. 2 illustrates the structural representation of the FPGA-SOC integrated chip in the control module of Fig. 1;
Fig. 3 illustrates that the intelligent video safety-protection system of Fig. 1 is applied to a specific embodiment of moving vehicle identification;
Fig. 4 illustrates the operation logic schematic diagram of the intelligent video safety-protection system of Fig. 1; And
Fig. 5 illustrates according to another embodiment of the present invention, for the FB(flow block) of the signal processing method of intelligent video safety-protection system.
Embodiment
The technology contents disclosed to make the application is more detailed and complete, and can refer to accompanying drawing and following various specific embodiment of the present invention, mark identical in accompanying drawing represents same or analogous assembly.But those of ordinary skill in the art should be appreciated that hereinafter provided embodiment is not used for limiting the scope that contains of the present invention.In addition, accompanying drawing, only for being schematically illustrated, is not drawn according to its life size.
With reference to the accompanying drawings, the embodiment of various aspects of the present invention is described in further detail.
Fig. 1 illustrates the structural representation of the intelligent video safety-protection system based on FPGA-SOC according to an embodiment of the present invention.With reference to Fig. 1, in this way of example, intelligent video safety-protection system of the present invention comprises video analysis front end 10 and centered video server 12.
Specifically, video analysis front end 10 comprises video input interface 102, control module 104 and video output interface.Wherein, the digital video stream signal of video input interface 102 for high speed SDI vision signal is unstringed as meeting BT.656 standard.At this, digital video stream signal comprises video data signal and ranks synchronizing signal, carries out logical process for the FPGA-SOC chip in control module 104.Such as, the vision signal of SD-SDI, HD-SDI or 3G-SDI that gathers for high definition industrial camera of high speed SDI vision signal.Control module 104 comprises FPGA-SOC chip (that is, the FPGA integrated chip of SOC class).Control module 104 couples mutually with video input interface 102, for carrying out preliminary treatment and video behavioural analysis to the digital video stream signal from video input interface 102, and the IP video stream signal of standard after output processing.Video output interface couples mutually with control module 104, for IP video stream signal is sent to centered video server 12 by network.Centered video server 12 receives this IP video stream signal, and the video analysis being used for configuring video analysis front end 10 is regular, and the comprehensive video stream after monitor video analysis front end 10 process.
At a specific embodiment, video input interface 102 also can send and/or receive GPIO (General Purpose Input Output, universal input exports) sensor alarm signal.In addition, video analysis front end 10 also can comprise polytype memory, such as flash memory (Flash), Double Data Rate synchronous DRAM (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM).
Fig. 2 illustrates the structural representation of the FPGA-SOC integrated chip in the control module of Fig. 1.With reference to Fig. 2, the FPGA-SOC chip of control module 104 also comprises logic module (Programmable Logic) 1043 and processing module (Process System) 1041.At this, the function of logic module 1043 is organized in the mode of VDMA IP kernel, and is configured by the system that AXI4-Lite bus is run by arm processor and control.
Particularly, logic module 1043 for receiving the digital video stream signal from video input interface 102, and carries out video image preliminary treatment and video analysis process to digital video stream signal, and by the memory of the video data after process stored in system.Processing module 1041 is from the video data after the memory reading process of system, movement locus extraction and judgement are carried out to it, and judged the legitimacy of motor behavior by comparing motion target trajectory and the video analysis rule configured, and then final IP video stream signal is sent to centered video server 12 by network.
Preferably, processing module 1041 has arm processor, DMA (Direct Memory Access, direct memory access (DMA)) controller, first memory controller, interrupt control unit and peripheral interface module, wherein, arm processor couples mutually with interrupt control unit and first memory controller respectively.Such as, arm processor can support ONVIF security protection interface protocol, and supports HTTP, FTP or RTP procotol.Peripheral interface module couples mutually with dma controller and interrupt control unit.Such as, peripheral interface module is I2C, UART, SPI, ETH, CAN or other external communication interface.
Preferably, logic module 1043 has video image pretreatment unit, video analysis unit, video compressing unit, second memory controller and multiple VDMA IP kernel, wherein, video image pretreatment unit is coupled to first memory controller via a VDMA IP kernel, video analysis unit is coupled to video image pretreatment unit and is coupled to first memory controller via the 2nd VDMA IP kernel, and video compressing unit is coupled to video image pretreatment unit and is coupled to first memory controller via the 3rd VDMA IP kernel.In one embodiment, video analysis unit carries out the parallel processing of many videos rule of conduct to through pretreated digital video by intelligent vision algorithm.H.264, video compressing unit compresses the video flowing including result.Such as, video image pretreatment unit carries out image color space conversion, image enhaucament filtering, electronic steady image, noise filtering, the value process of image ash and/or binary conversion treatment to received video flowing.Such as, after video image preliminary treatment completes, by the VDMA IP kernel of Fig. 2 leftmost side, video stream signal is converted to AXI4-S data flow, and be cached in the DDR of system, and then from the DDR of system, stored video data is directly read video analysis unit by the VDMA IP kernel in the middle of Fig. 2.
In one embodiment, when video stream data being transferred to memory by VDMA, set three different frame of video buffer memorys (Frame Buffer), VMDA is set to PARK mode of operation, thus passes through the switching between the operation of application program controlling DMA and different frame of video buffer memorys.More preferably, in the implementation procedure of video analysis algorithm, video Frame Buffer is needed to carry out the demand of data cached process for it, also can at logic module 1043 inner configuration separately DDR memory (namely, the DDR of Fig. 2 bottom), special in video analysis unit and video compressing unit.In one embodiment, video analysis front end 10 also comprises one first Double Data Rate synchronous DRAM (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) and one second Double Data Rate synchronous DRAM.As shown in Figure 2, a DDR SDRAM is coupled to processing module 1041, and the 2nd DDR SDRAM is coupled to logic module 1043.
Fig. 3 illustrates that the intelligent video safety-protection system of Fig. 1 is applied to a specific embodiment of moving vehicle identification.
With reference to Fig. 3, need in traffic application to identify the vehicle of motion, extract movement locus, then judge vehicle whether more yellow line, retrograde, illegal parking etc.If confirm in violation of rules and regulations, then identify violation vehicle and identify car plate.This sequence of operations comprises moving target feature extraction, movement locus extracts and tracking, License Plate, License Plate Character Segmentation, optical character identification.In moving object detection algorithm, what the present embodiment adopted is follow-on Background difference and removes algorithm based on the background shadow of color space, by the extraction of background with more newly arrive and adapt to the change of background of complexity, better separation prospect and background.The Kalman Prediction algorithm adopting feature based in realization is followed the trail of at movement objective orbit.
Composition graphs 2 and Fig. 3, the process of the whole video analysis algorithm realization of this exemplary application is as follows:
Video pre-filtering part, achieves noise filtering and image enhaucament, and this preprocessing part is performed by IP kernel.After preliminary treatment completes, video data is stored in the DDR of system through VDMA.Then, video data reads video analysis unit through another VDMA under the control of system, is separated the algorithm after starting with the past background realized in Fig. 3.Particularly, front and back scape is separated and the algorithm of background characteristics Extraction parts needs to carry out computing to adjacent video frames, and now video data is stored in the Frame Buffer opened up in DDR buffer memory corresponding to FPGA-SOC chip after VDMA.IP kernel under the control of AXI4-Lite bus from Frame Buffer reading video data process.The attributive character data of vehicle pass through AXI4-Lite bus configuration to IP kernel by arm processor, the information of vehicles then being contrasted attributive character detection by IP kernel algorithm and extracted in video data.Algorithm in this process is also used Frame Buffer and Line Buffer loading video data and is carried out computing.At this, Frame Buffer and Line Buffer can carry out unifying process, realizes polyalgorithm and shares, and carrys out replacing of control algolithm, and then reduce the time delay of real time video processing by the switching between Frame Buffer and Line Buffer.Wherein Frame Buffer is frame of video buffer memory, is used for the computing done in algorithm between different frame.Line Buffer is video frame line picture element caching, is used for doing the computing of pixel window data between adjacent lines in algorithm.After computing completes, the video data stream containing spotting information of vehicles is transferred in the DDR of system through VDMA again, calls for arm processor.Arm processor reads and has demarcated the video data of target vehicle from the DDR of system, is then followed the trail of by the movement locus of software algorithm realize target vehicle and extracts and mark.And combine rule and the vehicle attribute storehouse of setting, judge the type etc. of vehicle whether violation and vehicle.After judging violation vehicle and characteristic, need to carry out Car license recognition to violation vehicle, now by VDMA, violation vehicle image is transferred to FPGA-SOC chip again, the orientation and segmentation to characters on license plate is realized by IP kernel, then get back in Installed System Memory through VDMA, contrast characters on license plate storehouse and character by arm processor, obtain the license plate number information of vehicle in violation of rules and regulations.Finally, after video analysis completes, a part for analysis result can be described in the target of original video, and another part (license plate number etc.) can send to centered video server with signaling method.The original video identifying analysis result needs to carry out video compression before Internet Transmission.What adopt in the present embodiment is H.264 compress mode, and after having compressed, video flowing is got back in Installed System Memory, carries out data packing by arm processor, sends to centered video server according to system protocol by mixed-media network modules mixed-media.
Fig. 4 illustrates the operation logic schematic diagram of the intelligent video safety-protection system of Fig. 1.With reference to Fig. 4, after the opening initialization of video analysis front end, each interface and module in running order, if now centered video server does not configure video analysis front end, then video analysis front end start according to acquiescence parameter preset start receive, process and send video data.In addition, centered video server carries out the monitoring of real-time video by client terminal, and receives the target information showing and break the rules.Meanwhile, centered video server can reset in the random time of video analysis front end work or upgrade rule and the parameter of target detection.
In the diagram, after default parameters or server configuration parameters, preliminary treatment is carried out to the video flowing of input, then successively the video analysis result of video analysis unit and the compression result of video compressing unit are cached in the DDR of system, finally by network, the IP video stream signal of standard are sent to centered video server by video output interface.
Fig. 5 illustrates according to another embodiment of the present invention, for the FB(flow block) of the signal processing method of intelligent video safety-protection system.
With reference to Fig. 5 composition graphs 1, Fig. 2, in this signal processing method, first perform step S11, the digital video stream signal that high speed SDI vision signal is unstringed as meeting BT.656 standard by video analysis front end 10.Then perform step S13,10 pairs, video analysis front end digital video stream signal carries out preliminary treatment and video behavioural analysis, and the IP video stream signal of standard after output processing.Then perform step S15, IP video stream signal is sent to centered video server 12 by video analysis front end 10.Finally, centered video server 12 receives IP video stream signal, and the random time that can work in video analysis front end 10 resets or the video analysis rule of Reconfigurations video analysis front end 10, and the comprehensive video stream after monitor video analysis front end 10 process.
At a specific embodiment, the logic module of FPGA-SOC chip is also for after video image preliminary treatment, by a VDMA IP kernel, video data is deposited in the DDR of system, then video analysis process is carried out to it by the 2nd VDMA IP kernel from the DDR reading video data of system, then by the video data after video analysis process again buffer memory to the DDR of system, again read the video data after analyzing and processing by the 3rd VDMA IP kernel from the DDR of system afterwards, thus the compression process of video data is carried out to it.
Adopt the intelligent video safety-protection system based on FPGA-SOC chip of the present invention and signal processing method thereof, the digital video stream signal that high speed SDI vision signal is unstringed as meeting BT.656 standard by the video input interface of video analysis front end, control module is connected with video input interface and carries out preliminary treatment and video behavioural analysis to digital video stream signal, the IP video stream signal of the standard after output processing, video output interface is connected with control module and IP video stream signal is sent to centered video server, and then centered video server receives IP video stream signal, the video analysis rule of configuration video analysis front end, and the comprehensive video stream after monitor video analysis front-end processing.Compared with prior art, the present invention effectively can realize multiple target, more rules for real-time high-definition video (1080P, 30fps/60fps) and carries out video analysis simultaneously.In addition, for effectively improving the implementation efficiency of video analysis algorithm, the realization of algorithm, except the parallel behavior utilizing FPGA, is used pile line operation by the present invention in a large number, and takes area to exchange the mode of speed for improve the data throughput of process.Moreover video analysis algorithm and embedded system control to be completed by a FPGA-SOC integrated chip, decrease hardware cost, reduce system power dissipation.The present invention is applicable to common monitoring field, as the occasion that traffic, community, airport, square, oil field, prison, museum etc. need Timeliness coverage anomalous event linkage to report to the police.In addition, the video analysis front end of safety-protection system of the present invention can be used for integrated intelligent video analysis camera shooting integrated machine.
Above, the specific embodiment of the present invention is described with reference to the accompanying drawings.But those skilled in the art can understand, when without departing from the spirit and scope of the present invention, various change and replacement can also be done to the specific embodiment of the present invention.These change and replace and all drop in claims of the present invention limited range.
Claims (14)
1. based on an intelligent video safety-protection system of FPGA-SOC, it is characterized in that, described intelligent video safety-protection system comprises video analysis front end and centered video server, and wherein, described video analysis front end comprises:
Video input interface, for the digital video stream signal unstringing high speed SDI vision signal for meeting BT.656 standard;
Control module, comprises FPGA-SOC chip, and described control module couples mutually with described video input interface, for carrying out preliminary treatment and video behavioural analysis to described digital video stream signal, and the IP video stream signal of standard after output processing;
Video output interface, couples mutually with described control module, for described IP video stream signal is sent to described centered video server,
Wherein, described centered video server, for receiving described IP video stream signal, configures the video analysis rule of described video analysis front end, and monitors the comprehensive video stream after described video analysis front-end processing.
2. intelligent video safety-protection system according to claim 1, is characterized in that, described FPGA-SOC chip also comprises logic module and processing module,
Wherein, described logic module for receiving described digital video stream signal, and carries out video image preliminary treatment and video behavioural analysis to described digital video stream signal, and by the memory of the video data after process stored in system;
Wherein, described processing module reads the video data after described process from described memory, movement locus extraction and judgement are carried out to it, and judged the legitimacy of motor behavior by comparing motion target trajectory and the video analysis rule configured, and then final IP video stream signal is sent to described centered video server by network.
3. intelligent video safety-protection system according to claim 2, is characterized in that, described processing module has arm processor, dma controller, first memory controller, interrupt control unit and peripheral interface module,
Wherein, described arm processor couples mutually with described interrupt control unit and described first memory controller respectively, and described peripheral interface module couples mutually with described dma controller and described interrupt control unit.
4. intelligent video safety-protection system according to claim 3, is characterized in that, described peripheral interface module for exporting described IP video stream signal, and sends and/or receive GPIO sensor alarm signal.
5. intelligent video safety-protection system according to claim 3, is characterized in that, described logic module has video image pretreatment unit, video analysis unit, video compressing unit, second memory controller and multiple VDMA IP kernel,
Wherein, described video image pretreatment unit is coupled to described first memory controller via a VDMA IP kernel, described video analysis unit is coupled to described video image pretreatment unit and is coupled to described first memory controller via the 2nd VDMA IP kernel, and described video compressing unit is coupled to described video image pretreatment unit and is coupled to described first memory controller via the 3rd VDMA IP kernel.
Wherein said video image pretreatment unit carries out image color space conversion, image enhaucament filtering, electronic steady image, noise filtering, the value process of image ash and/or binary conversion treatment to received video flowing; Described video analysis unit carries out the parallel processing of many videos rule of conduct to through pretreated digital video by intelligent vision algorithm; H.264, described video compressing unit compresses the video flowing including result.
6. intelligent video safety-protection system according to claim 3, is characterized in that, described peripheral interface module is I2C, UART, SPI, ETH or CAN communication interface.
7. intelligent video safety-protection system according to claim 3, is characterized in that, described arm processor for supporting ONVIF security protection interface protocol, and supports HTTP, FTP or RTP procotol.
8. intelligent video safety-protection system according to claim 2, it is characterized in that, described video analysis front end also comprises one the one DDR SDRAM and the 2nd DDR SDRAM, wherein, a described DDR SDRAM is coupled to described processing module, and described 2nd DDR SDRAM is coupled to described logic module.
9. intelligent video safety-protection system according to claim 5, it is characterized in that, when video stream data being transferred to memory by VDMA, set three different frame of video buffer memorys, VDMA is set to PARK mode of operation, thus passes through the switching between the operation of application program controlling DMA and different frame of video buffer memorys.
10. intelligent video safety-protection system according to claim 1, is characterized in that, the vision signal of SD-SDI, HD-SDI or 3G-SDI that described high speed SDI vision signal gathers for high definition industrial camera.
11. 1 kinds of signal processing methods for intelligent video safety-protection system, described intelligent video safety-protection system comprises video analysis front end and centered video server, it is characterized in that, described signal processing method comprises:
The digital video stream signal that high speed SDI vision signal is unstringed as meeting BT.656 standard by described video analysis front end;
Preliminary treatment and video behavioural analysis are carried out to described digital video stream signal in described video analysis front end, and the IP video stream signal of standard after output processing;
Described IP video stream signal is sent to described centered video server by described video analysis front end;
Described centered video server receives described IP video stream signal, configures the video analysis rule of described video analysis front end, and monitors the comprehensive video stream after described video analysis front-end processing.
12. signal processing methods according to claim 11, is characterized in that, described video analysis front end comprises FPGA-SOC chip, and described FPGA-SOC chip comprises logic module and processing module,
Wherein, described logic module for receiving described digital video stream signal, and carries out video image preliminary treatment and video behavioural analysis to described digital video stream signal, and by the memory of the video data after process stored in system;
Wherein, described processing module reads the video data after described process from described memory, movement locus extraction and judgement are carried out to it, and judged the legitimacy of motor behavior by comparing motion target trajectory and the video analysis rule configured, and then final IP video stream signal is sent to described centered video server by network.
13. signal processing methods according to claim 12, is characterized in that, described logic module is also for performing:
Pretreatment operation, for carrying out image color space conversion, image enhaucament filtering, electronic steady image, noise filtering, the value process of image ash and/or binary conversion treatment to received video flowing;
Video analysis operates, for carrying out the parallel processing of many videos rule of conduct to through pretreated digital video by intelligent vision algorithm;
H.264, video compression operation, for compressing the video flowing including result.
14. signal processing methods according to claim 12, it is characterized in that, described video analysis front end also comprises one the one DDR SDRAM and the 2nd DDR SDRAM, wherein, a described DDR SDRAM is coupled to described processing module, and described 2nd DDR SDRAM is coupled to described logic module.
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Cited By (14)
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| CN104836986A (en) * | 2015-04-15 | 2015-08-12 | 华东师范大学 | Video information intelligent display method and apparatus |
| CN105721780A (en) * | 2016-04-05 | 2016-06-29 | 华南理工大学 | Embedded image processing system and method based on SoC FPGA |
| CN105828041A (en) * | 2016-04-11 | 2016-08-03 | 上海大学 | Video acquisition system supporting parallel preprocessing |
| CN105979201A (en) * | 2016-04-11 | 2016-09-28 | 上海大学 | Intelligent wearable device based on parallel processor |
| CN106254795A (en) * | 2016-08-31 | 2016-12-21 | 成都市和平科技有限责任公司 | A kind of image-enhancing equipment based on spatial domain image enhancement technique and method |
| CN106324195A (en) * | 2016-08-17 | 2017-01-11 | 成都环球物讯科技有限责任公司 | Intelligent community comprehensive service security and protection system |
| CN106407522A (en) * | 2016-08-31 | 2017-02-15 | 德为显示科技股份有限公司 | FPGA-based logic IP bus interconnection realization device |
| WO2017181871A1 (en) * | 2016-04-19 | 2017-10-26 | 中兴通讯股份有限公司 | Video monitoring method, apparatus and system |
| CN107506773A (en) * | 2017-09-25 | 2017-12-22 | 郑州云海信息技术有限公司 | A kind of feature extracting method, apparatus and system |
| CN108712630A (en) * | 2018-04-19 | 2018-10-26 | 安凯(广州)微电子技术有限公司 | A kind of internet camera system and its implementation based on deep learning |
| CN110519497A (en) * | 2019-08-28 | 2019-11-29 | 中国大恒(集团)有限公司北京图像视觉技术分公司 | A kind of zero-copy triggering collection device and method based on VDMA |
| CN110769257A (en) * | 2018-07-25 | 2020-02-07 | 北京深鉴智能科技有限公司 | Intelligent video structured analysis device, method and system |
| WO2022011989A1 (en) * | 2020-07-16 | 2022-01-20 | 威创集团股份有限公司 | Video coding system |
| CN114489496A (en) * | 2022-01-14 | 2022-05-13 | 南京邮电大学 | Data storage and transmission method based on FPGA artificial intelligence accelerator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104836986A (en) * | 2015-04-15 | 2015-08-12 | 华东师范大学 | Video information intelligent display method and apparatus |
| CN105721780A (en) * | 2016-04-05 | 2016-06-29 | 华南理工大学 | Embedded image processing system and method based on SoC FPGA |
| CN105828041A (en) * | 2016-04-11 | 2016-08-03 | 上海大学 | Video acquisition system supporting parallel preprocessing |
| CN105979201A (en) * | 2016-04-11 | 2016-09-28 | 上海大学 | Intelligent wearable device based on parallel processor |
| WO2017181871A1 (en) * | 2016-04-19 | 2017-10-26 | 中兴通讯股份有限公司 | Video monitoring method, apparatus and system |
| CN106324195A (en) * | 2016-08-17 | 2017-01-11 | 成都环球物讯科技有限责任公司 | Intelligent community comprehensive service security and protection system |
| CN106407522B (en) * | 2016-08-31 | 2019-09-10 | 德为显示科技股份有限公司 | Logical ip bus bar realization device based on FPGA |
| CN106254795A (en) * | 2016-08-31 | 2016-12-21 | 成都市和平科技有限责任公司 | A kind of image-enhancing equipment based on spatial domain image enhancement technique and method |
| CN106407522A (en) * | 2016-08-31 | 2017-02-15 | 德为显示科技股份有限公司 | FPGA-based logic IP bus interconnection realization device |
| CN107506773A (en) * | 2017-09-25 | 2017-12-22 | 郑州云海信息技术有限公司 | A kind of feature extracting method, apparatus and system |
| CN108712630A (en) * | 2018-04-19 | 2018-10-26 | 安凯(广州)微电子技术有限公司 | A kind of internet camera system and its implementation based on deep learning |
| CN110769257A (en) * | 2018-07-25 | 2020-02-07 | 北京深鉴智能科技有限公司 | Intelligent video structured analysis device, method and system |
| CN110519497A (en) * | 2019-08-28 | 2019-11-29 | 中国大恒(集团)有限公司北京图像视觉技术分公司 | A kind of zero-copy triggering collection device and method based on VDMA |
| CN110519497B (en) * | 2019-08-28 | 2020-11-17 | 中国大恒(集团)有限公司北京图像视觉技术分公司 | Zero-copy trigger acquisition device and method based on VDMA |
| WO2022011989A1 (en) * | 2020-07-16 | 2022-01-20 | 威创集团股份有限公司 | Video coding system |
| CN114489496A (en) * | 2022-01-14 | 2022-05-13 | 南京邮电大学 | Data storage and transmission method based on FPGA artificial intelligence accelerator |
| CN114489496B (en) * | 2022-01-14 | 2024-05-21 | 南京邮电大学 | Data storage and transmission method based on FPGA artificial intelligent accelerator |
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