CN104318958A - Method for replacing integrated circuit storage device in application - Google Patents
Method for replacing integrated circuit storage device in application Download PDFInfo
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- CN104318958A CN104318958A CN201410577856.5A CN201410577856A CN104318958A CN 104318958 A CN104318958 A CN 104318958A CN 201410577856 A CN201410577856 A CN 201410577856A CN 104318958 A CN104318958 A CN 104318958A
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- identification code
- integrated circuit
- memory storage
- kenel
- memory device
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Abstract
The invention discloses a method for replacing an integrated circuit storage device in application. The method comprises the following steps: providing a system with configuration which is compatible with a pattern of a first integrated circuit storage device with a first storage device identification code; providing a pattern of a second integrated circuit storage device which does not have the first storage device identification code; configuring at least part of the first storage device identification code of the pattern of the second integrated circuit storage device; and integrating the pattern of the second integrated circuit storage device with the system. The storage device identification code disclosed by the invention is programmable. In some embodiments, the plurality of device identification codes are stored into an integrated circuit and a plurality of device identification selection codes are stored in the integrated circuit.
Description
The application is divisional application, the application number of female case: 201110072510.6, the applying date: on March 17th, 2011, title: integrated circuit memory device and replacement thereof and manufacture method.
Technical field
The invention relates to the identification code able to programme of an integrated circuit (IC) apparatus, especially a kind of integrated circuit memory device, in one application in replace the method for an integrated circuit memory device and manufacture the method for this integrated circuit memory device.
Background technology
Each memory storage has an identification code to represent the kenel of a storer, density, manufacturer or even other needs the important parameter understood by system.Typically, these identification codes are stored by antifuse and are unmodifiable.If this memory storage is replaced by another supplier or other kenel, this system or controller perhaps can cause inefficacy because of the identification code expecting the old storer be substituted.So can produce obstacle to using another different supplier and/or other kenel to replace current storer.For example, system or controller being upgraded its hardware or software, to make it have new recognition capability be a thing expending very much money and time.
Summary of the invention
In view of this, an object of the present invention is to provide a kind of integrated circuit memory device.This integrated circuit memory device comprise an IC substrate, multiple application memory unit on this IC substrate, multiple device identification nonvolatile memory cell on this IC substrate, multiple device identification selection nonvolatile memory cell is on this IC substrate and control circuit.
This control circuit, its (i) carries out the operation of multiple device identification code of the plurality of identification nonvolatile memory cell, the plurality of device identification code comprises the position of this integrated circuit memory device kenel of multiple identification, (ii) carry out the programming of the selection data of the plurality of identification selection nonvolatile memory cell, erasing and read operation, these selection data make difference in the plurality of device identification code.
In one embodiment, this control circuit, respond a device identification code reading command, and reading a device identification code from the plurality of identification nonvolatile memory cell, this device identification code makes difference by these selection data other device identification code in the plurality of identification nonvolatile memory cell of the plurality of identification selection nonvolatile memory cell.
In one embodiment, the kenel of this integrated circuit memory device is differentiated by a device identification code of the plurality of device identification code, and the plurality of device identification code comprises manufacturer's identification code of this integrated circuit memory device.
In one embodiment, the kenel of this integrated circuit memory device is differentiated by a device identification code of the plurality of device identification code, and the plurality of device identification code comprises the manufaturing data of this integrated circuit memory device.
In one embodiment, the kenel of this integrated circuit memory device is differentiated by a device identification code of the plurality of device identification code, and the plurality of device identification code comprises the product specification data of this integrated circuit memory device.
Another object of the present invention, for providing a kind of method replacing an integrated circuit memory device in an application, comprises:
A configuration is provided to be the system with the one first integrated circuit memory device kenel compatibility with one first memory storage identification code;
A second integrated circuit memory device kenel without the first memory storage identification code is provided;
This second integrated circuit memory device kenel of configuration has this this at least part of the first memory storage identification code; And
By this second integrated circuit memory device kenel and this system combination.
In one embodiment, this configuration comprises:
Multiple device identification nonvolatile memory cells of programming in this second integrated circuit memory device kenel have this this at least part of the first memory storage identification code, when device identification code in this second integrated circuit memory device kenel of reading like this operates, read this this at least part of the first memory storage identification code from the plurality of device identification nonvolatile memory cell.
In one embodiment, this configuration comprises:
Multiple device identification selection nonvolatile memory cells of programming in this second integrated circuit memory device kenel have selects data to distinguish this this at least part of the first memory storage identification code in the multiple memory storage identification codes in this second integrated circuit memory device kenel, when device identification code in this second integrated circuit memory device kenel of reading like this operates, read this this at least part of the first memory storage identification code from the plurality of device identification nonvolatile memory cell.
In one embodiment, this configuration comprises:
Multiple device identification nonvolatile memory cells of programming in this second integrated circuit memory device kenel have this this at least part of the first memory storage identification code, when device identification code in this second integrated circuit memory device kenel of reading like this operates, respond this this at least part of the first memory storage identification code to this system from the plurality of device identification nonvolatile memory cell.
In one embodiment, this configuration comprises:
Multiple device identification selection nonvolatile memory cells of programming in this second integrated circuit memory device kenel have selects data to distinguish this this at least part of the first memory storage identification code in the multiple memory storage identification codes in this second integrated circuit memory device kenel, when device identification code in this second integrated circuit memory device kenel of reading like this operates, respond this this at least part of the first memory storage identification code to this system from the plurality of device identification nonvolatile memory cell.
In one embodiment, before this configuration, this memory storage identification code read operation in this second integrated circuit memory device kenel cannot respond this this at least part of the first memory storage identification code.
In one embodiment, before this configuration, do not have this first memory storage identification code this second integrated circuit memory device kenel cannot with this system compatible.
In one embodiment, after this configuration, this memory storage identification code read operation in this second integrated circuit memory device kenel can respond this this at least part of the first memory storage identification code.
In one embodiment, after this configuration, do not have this first memory storage identification code this second integrated circuit memory device kenel can with this system compatible.
In one embodiment, this first device identification code comprises manufacturer's identification code of this integrated circuit memory device.
In one embodiment, this first device identification code comprises the manufaturing data of this integrated circuit memory device.
In one embodiment, this first device identification code comprises the product specification data of this integrated circuit memory device.
Another object of the present invention, for providing the method for a kind of manufacture one integrated circuit memory device, comprises:
One IC substrate is provided;
There is provided multiple application memory unit on this IC substrate;
There is provided multiple device identification nonvolatile memory cell on this IC substrate;
There is provided multiple device identification selection nonvolatile memory cell on this IC substrate; And
Control circuit is provided, its (i) carries out the operation of multiple device identification code of the plurality of identification nonvolatile memory cell, the plurality of device identification code comprises the position of this integrated circuit memory device kenel of multiple identification, (ii) carry out the programming of the selection data of the plurality of identification selection nonvolatile memory cell, erasing and read operation, these selection data make difference in the plurality of device identification code.
In one embodiment, this control circuit, respond a device identification code reading command, and reading a device identification code from the plurality of identification nonvolatile memory cell, this device identification code makes difference by these selection data other device identification code in the plurality of identification nonvolatile memory cell of the plurality of identification selection nonvolatile memory cell.
In one embodiment, the kenel of this integrated circuit memory device is differentiated by a device identification code of the plurality of device identification code, and the plurality of device identification code comprises manufacturer's identification code of this integrated circuit memory device.
In one embodiment, the kenel of this integrated circuit memory device is differentiated by a device identification code of the plurality of device identification code, and the plurality of device identification code comprises the manufaturing data of this integrated circuit memory device.
In one embodiment, the kenel of this integrated circuit memory device is differentiated by a device identification code of the plurality of device identification code, and the plurality of device identification code comprises the product specification data of this integrated circuit memory device.
In various embodiments, these storage unit can be non-volatile and/or volatile.
Accompanying drawing explanation
The present invention defined by right.These and other objects, feature, and embodiment, graphic being described of arranging in pairs or groups in the chapters and sections of following embodiments, wherein:
Figure 1A and Figure 1B shows the schematic diagram of the enforcement of a typical memory identification decoding circuit.
Fig. 2 A and Fig. 2 B shows schematic diagram and the process flow diagram of many different embodiments respectively.
Fig. 3 A and Fig. 3 B shows the schematic diagram of other embodiment.
How Fig. 4 display extracts and upgrades the process flow diagram that memory storage identification code chooses position.
How Fig. 5 display again extracts and upgrades the process flow diagram that memory storage identification code chooses position.
Fig. 6 shows the variable memory device identification selection code of an example and the application of variable memory device identification code.
Fig. 7 shows the rough schematic view of integrated circuit according to an embodiment of the invention.
[main element symbol description]
750: integrated circuit
700: the nonvolatile memory cell with application data
752: the nonvolatile memory cell with device identification code
754: there is the nonvolatile memory cell selecting data
701: column decoder
702: wordline
703: line decoder
704: bit line
705,707: bus
706: sensing amplifier/data input structure
709: programming, erasing and reading adjustment bias state mechanism
708: bias voltage adjustment supply voltage
711: Data In-Line
715: DOL Data Output Line
Embodiment
One nonvolatile memory cell (such as flash memory devices) is even still can not make stored Missing data when not having power supply.Use nonvolatile memory cell to carry out store identification code in different embodiments, and can be upgraded by programming or wiping array data so.In the case, memory identification code is programmable and can be adjusted neatly for the different system of expection different memory identification code.Otherwise different systems will need the identification code that the change of destructiveness and costliness could be new needed for the arrangement one of different memory storage.
Figure 1A and Figure 1B shows the schematic diagram of the enforcement of a typical memory identification decoding circuit.In figure ia, a recognition memory cell repeatedly comes across in one array architecture, and data export with byte mode or character pattern.The more detailed schematic diagram of recognition memory cell is shown in Figure 1B, and comprise the connection of dependence one metal level and the transistor of output bit-line BL to ground of being left behind by N-type metal oxide semiconductor transistor, or remain on supply voltage (Vdd) alternatively by the faint output bit-line BL that draws high of P-type mos transistor.Therefore, the identification code of a memory storage can be changed by the metal level of this memory storage of amendment.But, embodiment so is more not flexible, because its needs change the mask of metal level to different memory storage identification codes, and need the identification code (so the identification code of this memory storage cannot be revised after manufacturing) that just must determine this memory storage during fabrication.
Fig. 2 A and Fig. 2 B shows schematic diagram and the process flow diagram of many different embodiments respectively.In fig. 2, each memory storage identification code bit has and is connected with the nmos pass transistor of leaving behind of series connection, and is selected by the identical specific bit-position of different memory storage identification code selection to each nmos pass transistor of a specific bit-position in this serial.The position, position that the top row read storage device identification code ID0 of this nmos pass transistor is all, and the position, position that the below row read storage device identification code ID1 of this nmos pass transistor is all.For example, the most left person's correspondence of this series NMOS transistors exports memory storage identification code bit ID7, and within this serial, this higher nmos pass transistor is chosen by position, the position ID7 of memory storage identification code ID0, and this lower nmos pass transistor is chosen by position, the position ID7 of another memory storage identification code ID1.Point between higher nmos pass transistor and lower nmos pass transistor represents in different embodiments, and this circuit customizedly can turn to the memory storage identification code with a given number, the row of such as one different number.In addition, this circuit also customizedly can turn to the position, position in each memory storage identification code with a given number, the row of such as one different number.
Different memory storage identification code is selected to be stored in a nonvolatile memory and extract when power initiation reads to enter in buffer.For a specific bit-position, if when any memory storage identification code (such as memory storage identification code ID0 or ID1) is logic high, then the down transistor path of this position is opened.In the case, this integrated circuit can be stored in memory storage identification code in one or more nonvolatile memory cell and selects position to export one selected by Multiple storage device identification code according to one or more.Fig. 2 B shows the process flow diagram extracting memory storage identification selection code process, and extracts the memory storage identification code selected by memory storage identification selection code when power initiation reads afterwards.After the step 11 that power initiation reads, step 13 extracts memory storage identification selection code from nonvolatile memory cell.In step 15, use this memory storage identification selection code to choose one of Multiple storage device identification code.Then, in step 17, selected memory storage identification selection code is exported.
Fig. 3 A and Fig. 3 B shows the schematic diagram of other embodiment.Fig. 3 A is memory storage identification code cache array structure.The buffer of different memory storage identification code carrys out activation by different enable signals (EN#), and export data bus ID0 ~ ID7 to, and the buffer of other memory storage identification code still keeps closing owing to not receiving this enable signal.Fig. 3 B shows the schematic diagram of an example unit identification buffer, and it has one " Load (extraction) " signal will to read from the memory storage identification code bolt-lock of nonvolatile memory cell and this enable signal " EN " sets this bolt-lock starts.Because memory storage identification code stores and extracts from nonvolatile memory cell, this memory storage identification code can by programming or wiping this storage unit to revise.
How Fig. 4 display extracts and upgrades the process flow diagram that memory storage identification code chooses position.In step 21, send a memory storage identification selection code being about to be programmed.The step 23 that operates in of this program storage identification selection code starts.In the proving program of step 25, can determine to programme successfully or failure.If judge it is program fail, then can determine whether to reach maximum programming number of attempt in step 27.If not yet reach maximum programming number of attempt, then come back to step 23 and again carry out programming operation.If reached maximum programming number of attempt, then determine programming operation failure in step 29.If judge it is programme successfully in step 25, then this algorithm can advance to step 31 and carries out electric power starting reading.This memory storage identification selection code can extract in step 33 and enter nonvolatile memory cell.After there is memory storage identification selection code, a memory storage identification code can be chosen in step 35.Then this memory storage identification code identified by memory storage identification selection code exports in step 37.
How Fig. 5 display again extracts and upgrades the process flow diagram that memory storage identification code chooses position.In step 41, send a memory storage identification selection code being about to be programmed.The step 43 that operates in of this program storage identification selection code starts.In the proving program of step 45, can determine to programme successfully or failure.If judge it is program fail, then can determine whether to reach maximum programming number of attempt in step 47.If not yet reach maximum programming number of attempt, then come back to step 43 and again carry out programming operation.If reached maximum programming number of attempt, then determine programming operation failure in step 49.If judge it is programme successfully in step 45, then this algorithm can advance to step 51 and carries out electric power starting reading.This memory storage identification selection code can extract in step 53 and enter nonvolatile memory cell.Then this memory storage identification code exports in step 55.
Fig. 6 shows the variable memory device identification selection code of an example and the application of variable memory device identification code.A configuration is provided to be the system with the first integrated circuit memory device kenel compatibility with the first memory storage identification code in step 61.The example of this compatibility is, this system inquires after the first integrated circuit memory device kenel, and after receiving the first memory storage identification code from the first integrated circuit memory device kenel, this system can operate normally.A second integrated circuit memory device kenel without the first memory storage identification code is provided in step 63.At this moment, because the second integrated circuit memory device kenel does not have the first memory storage identification code, this system does not have configuration for compatible with the second integrated circuit memory device kenel.Although be lack compatibility, this system perhaps still can be arranged in pairs or groups with the second integrated circuit memory device kenel.For example, this system can configuration be interrupt normal operation, if when system inquires after the second integrated circuit memory device kenel not as expected as obtain the words of the first memory storage identification code.Do not have described technology at present, system so just must be revised and upgrade to accept the different memory storage identification codes relevant from the second integrated circuit memory device kenel.In step 65, this second integrated circuit memory device kenel is the first memory storage identification code at least with a part by configuration, and minimum is have desired the first memory storage identification code part continuing normal running of system.Configuration so is called variable memory device identification selection code and/or the variable memory device identification code of renewal second integrated circuit memory device kenel.In step 67, this second integrated circuit memory device kenel and system combination.Integration so can occur before or after the configuration of the second integrated circuit memory device kenel.
Fig. 7 shows the rough schematic view of integrated circuit according to an embodiment of the invention.Wherein integrated circuit 750 comprises the nonvolatile memory cell 754 using the nonvolatile memory cell 700 with application data, the nonvolatile memory cell 752 with device identification code and have selection data, utilizes mode described herein to be implemented in one or more storage array.One column decoder 701 couples with many wordline 702 along the arrangement of storage array column direction.Line decoder 703 couples to read the storage unit from array and the operation of programming data with the multiple bit lines 704 along the arrangement of storage array line direction.Address is supplied to line decoder 703 and column decoder 701 by bus 705.Sensing amplifier in square 706 and data input structure couple via data bus 707 and line decoder 703.Data are supplied to Data In-Line 711 by the input/output end port on integrated circuit 750, or by the data source of other inner/outer of integrated circuit 750, input to the data input structure in square 706.Controller used in the present embodiment is the use of bias voltage adjustment state machine 709, and the application of the bias voltage adjustment supply voltage being produced by voltage source of supply or square 708 or provide is provided, such as read, wipe, programme, erase verification and program verification voltage.This controller can utilize specific purposes logical circuit and apply, as well known to the skilled person.In alternative embodiments, this controller includes general object processor, and it can make in same integrated circuit, to perform the operation of a computer program and control device.In another embodiment, this controller is combined by specific purposes logical circuit and general object processor.
Different embodiment uses multi-form memory storage parameter such as identification code, kenel, density, specification etc.
This identification code method and apparatus able to programme according to the embodiment of the present invention is not limited in memory application, and can be applied to other and provide the circuit with elastic content data.
Except nonvolatile memory, the present invention also can be used in fuse or metal level is chosen in the device connecting kenel.Storage unit can be the medium of any kenel is such as that storage unit, fuse or metal level choose connection etc.
Although system of the present invention is described with reference to embodiment, right the present invention's creation is not limited to its detailed description.Substitute mode and amendment pattern advised in previously describing, and other substitute mode and revise pattern will be thought by those skilled in the art and.Particularly, all have be same as in fact component of the present invention combine and reach and the present invention identical result person in fact, neither depart from scope of the present invention.Therefore, these substitute modes all and amendment pattern are intended to drop among category that the present invention defines in appended claims and equipollent thereof.
Claims (8)
1. in an application, replace a method for an integrated circuit memory device, comprise:
A configuration is provided to be the system with the one first integrated circuit memory device kenel compatibility with one first memory storage identification code;
A second integrated circuit memory device kenel without the first memory storage identification code is provided;
This second integrated circuit memory device kenel of configuration has this this at least part of the first memory storage identification code; And
By this second integrated circuit memory device kenel and this system combination.
2. method according to claim 1, wherein this configuration comprises:
Multiple device identification nonvolatile memory cells of programming in this second integrated circuit memory device kenel have this this at least part of the first memory storage identification code, when device identification code in this second integrated circuit memory device kenel of reading like this operates, read this this at least part of the first memory storage identification code from the plurality of device identification nonvolatile memory cell.
3. method according to claim 1, wherein this configuration comprises:
Multiple device identification selection nonvolatile memory cells of programming in this second integrated circuit memory device kenel have selects data to distinguish this this at least part of the first memory storage identification code in the multiple memory storage identification codes in this second integrated circuit memory device kenel, when device identification code in this second integrated circuit memory device kenel of reading like this operates, read this this at least part of the first memory storage identification code from the plurality of device identification nonvolatile memory cell.
4. method according to claim 1, wherein before this configuration, the memory storage identification code read operation in this second integrated circuit memory device kenel cannot respond this this at least part of the first memory storage identification code.
5. method according to claim 1, wherein before this configuration, do not have this first memory storage identification code this second integrated circuit memory device kenel cannot with this system compatible.
6. method according to claim 1, wherein after this configuration, the memory storage identification code read operation in this second integrated circuit memory device kenel can respond this this at least part of the first memory storage identification code.
7. method according to claim 1, wherein after this configuration, do not have this first memory storage identification code this second integrated circuit memory device kenel can with this system compatible.
8. method according to claim 1, wherein this first device identification code comprise manufacturer's identification code of this integrated circuit memory device, manufaturing data and product specification data at least one of them.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410577856.5A CN104318958A (en) | 2011-03-17 | 2011-03-17 | Method for replacing integrated circuit storage device in application |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410577856.5A CN104318958A (en) | 2011-03-17 | 2011-03-17 | Method for replacing integrated circuit storage device in application |
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| CN201110072510.6A Division CN102682846B (en) | 2011-03-17 | 2011-03-17 | Integrated circuit memory device and replacement thereof and manufacture method |
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| CN104318958A true CN104318958A (en) | 2015-01-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060158916A1 (en) * | 2002-05-29 | 2006-07-20 | Micron Technology, Inc. | Programable identification circuitry |
| US20080245864A1 (en) * | 2007-04-05 | 2008-10-09 | Elpida Memory, Inc. | Device identification-code-information circuit and semiconductor integrated circuit having the device identification-code-information circuit |
| US7546498B1 (en) * | 2006-06-02 | 2009-06-09 | Lattice Semiconductor Corporation | Programmable logic devices with custom identification systems and methods |
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2011
- 2011-03-17 CN CN201410577856.5A patent/CN104318958A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060158916A1 (en) * | 2002-05-29 | 2006-07-20 | Micron Technology, Inc. | Programable identification circuitry |
| US7546498B1 (en) * | 2006-06-02 | 2009-06-09 | Lattice Semiconductor Corporation | Programmable logic devices with custom identification systems and methods |
| US20080245864A1 (en) * | 2007-04-05 | 2008-10-09 | Elpida Memory, Inc. | Device identification-code-information circuit and semiconductor integrated circuit having the device identification-code-information circuit |
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