CN104317774B - The apparatus and method that CM and butterfly computation are carried out using processor floating point unit - Google Patents
The apparatus and method that CM and butterfly computation are carried out using processor floating point unit Download PDFInfo
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Abstract
The invention provides a kind of apparatus and method that CM and butterfly computation are carried out using processor floating point unit, floating point unit is divided into float adding units and floating-point multiplication unit, increase a small amount of interconnection line by between float adding units and floating-point multiplication cell data port, make to form specific data path between float adding units and floating-point multiplication unit, real part and imaginary part are input to floating point unit FPDP according to the ordering rule of agreement, floating-point complex multiplication and floating-point complex butterfly computation can be realized under the decoded signal control that decoding unit is produced.Present invention saves hardware resource, flexibility is further increased than existing CM and dish-shaped calculation function unit, and can well realize the parallel and pipeline computing of mass data, obtain more preferable real-time performance and resource utilization.
Description
Technical field
The invention belongs to digital circuit technique field, it is adaptable to multiply and butterfly computation with floating-point complex in Digital Signal Processing
The quick calculating of the signal processing algorithms such as related FFT.
Background technology
In digital signal processing, it is related to substantial amounts of floating-point complex to multiply and butterfly computation.Due to data in signal transacting
Amount is big, complex disposal process, and digital signal processor can not well meet the requirement of real-time of data processing.With extensive
Integrated circuit technique is developed rapidly, and increasing signal processing algorithm is directly realized using example, in hardware, so as to improve
The real-time performance of data processing provides a kind of new way, not only reduces the delay of system processes data, and enhancing
System reliability, improves system operating efficiency.
Existing floating-point complex is multiplied and typically combined using some application specific integrated circuits with butterfly computation or use floating-point to grasp
Instruct and realized by software approach.Application specific integrated circuit combined method has that circuit complicated, volume and power consumption be big, very flexible
The shortcomings of, and circuit function fixes, and not can configure, it is low in most of occasion hardware resource utilizations；And use based on floating-point behaviour
The software approach that work is instructed, its arithmetic speed is slow, it is impossible to meet modern digital signal transacting requirement of real-time.
The content of the invention
In order to overcome the deficiencies in the prior art, the present invention to provide one kind and carry out CM and dish using existing floating point unit
The device of shape computing, by increasing a small amount of line between processor floating point unit, floating-point is constructed between floating point unit and is answered
Number multiplication and floating-point dish computing data path, realize floating-point complex is multiplied and floating-point dish computing support.The present invention
Circuit structure is simple, and it is few to occupy hardware resource, and execution efficiency is high, and flexibility is good.
The technical solution adopted for the present invention to solve the technical problems is：Floated including a decoding unit Decode, four
Point multiplication unit F mCell0~FmCell3, Mux0~Mux1 and four float adding units of two groups of data selection units
FaCell0~FaCell3.
For the floating-point complex X1+jY1 and X2+jY2 that are input into, operations of the decoding unit Decode according to input
Type C Type completes circuit decoding, produces and enables and control signal；
The floating-point multiplication unit F mCell0~FmCell3 performs multiplying part in plural multiplication；The floating-point
Data input DataA and data input the DataB port of multiplication unit FmCell0~FmCell3 sequentially input real part X1
With real part X2, imaginary part Y1 and imaginary part Y2, real part X1 and imaginary part Y2, imaginary part Y1 and plural number reality
Portion X2；The enable signal FmEn of the floating-point multiplication unit F mCell0~FmCell3 is decoded by decoding unit and produced；Work as operation
When arithmetic type CType is plural multiplication, decoding unit completes decoding, enables signal FmEn effectively, the floating-point multiplication list
First FmCell0~FmCell3 performs floating-point multiplication, believes by some timeticks output result of calculation Result and enable
Number EnOut, the result of calculation Result of the floating-point multiplication unit F mCell0~FmCell3 are followed successively by X1 × X2, Y1 × Y2,
X1 × Y2 and Y1 × X2, otherwise described floating-point multiplication unit F mCell0~FmCell3 does not perform any operation；When enable signal
When output EnOut is effective, the floating-point multiplication unit F mCell0~FmCell3 output floating-point multiplication results are represented, otherwise
The floating-point multiplication unitary operation result is invalid；
Data selection unit Mux0~the Mux1 is to being input into the data of float adding units FaCell0~FaCell1
Selected, selection control signal TypeEn is decoded by decoding unit and produced；The data selection unit Mux0 input datas are
Floating-point multiplication unit F mCell0 enables signal output EnOut, floating-point multiplication unit F mCell0 result of calculations X1 × X2, floating multiplication
Method unit F mCell1 result of calculations Y1 × Y2, enable signal FaEn, real part X1 and real part X2；The data selection
Unit Mux1 input datas are that floating-point multiplication unit F mCell1 enables signal output EnOut, floating-point multiplication unit F mCell2 meter
Calculate result X1 × Y2, floating-point multiplication unit F mCell3 result of calculations Y1 × X2, enable signal FaEn, imaginary part Y1 and plural number
Imaginary part Y2, enables signal FaEn and is produced by decoding unit, when operation Type C Type is for plural number dish computing, by translating
Code unit decoding, enables signal FaEn effectively, otherwise enables signal FaEn invalid；When arithmetic operation type for floating-point complex multiplies
When, in the presence of control signal TypeEn, data selection unit Mux0 output signals MEn, MDataA and MdataB according to
Secondary selection data are that floating-point multiplication unit F mCell0 enables signal output EnOut, floating-point multiplication unit F mCell0 result of calculations
X1 × X2 and floating-point multiplication unit F mCell1 result of calculations Y1 × Y2, otherwise, the data selection unit Mux0 output signals
MEn, MDataA and MdataB select data to enable signal FaEn, real part X1 and real part X2 for input successively；Work as fortune
Action type is calculated for floating-point complex is taken the opportunity, in the presence of control signal TypeEn, the data selection unit Mux1 outputs letter
Number MEn, MDataA and MdataB select data to enable signal output EnOut, floating multiplication for floating-point multiplication unit F mCell1 successively
Method unit F mCell2 result of calculations X1 × Y2 and floating-point multiplication unit F mCell3 result of calculations Y1 × X2, otherwise, the data
Select unit Mux1 output signals MEn, MDataA and MdataB select data to enable signal FaEn, imaginary part for input successively
Y1 and imaginary part Y2；
The float adding units FaCell0~FaCell3 performs floating addition reducing fortune in CM and dish-shaped computing
Calculate；Data input DataA and data input the DataB port of the float adding units FaCell2~FaCell3 sequentially input
Real part X1 and real part X2, imaginary part Y1 and imaginary part Y2；The float adding units FaCell2~
The enable signal FaEn and model selection Mode of FaCell3 are decoded by decoding unit and produced；When operation Type C Type is multiple
During number dish computing, decoding unit completes decoding, and the float adding units FaCell2~FaCell3 enables signal FaEn to be had
Effect, model selection Mode is floating-point subtraction operational pattern, and otherwise, the float adding units FaCell2~FaCell3 enables letter
Number FaEn is invalid；Enable signal FaEn, the data input DataA and data of the float adding units FaCell0~FaCell1
Input DataB ports sequentially input data MEn, MDataA and MdataB of the data selection unit Mux0~Mux1；Pattern
Selection Mode is decoded by decoding unit and produced；When operation Type C Type is for plural number dish computing, decoding unit completes to translate
Code, the float adding units FaCell0~FaCell1 model selections Mode is floating-point addition operation pattern, otherwise, described floating
Point adder unit FaCell0 model selections Mode is floating-point subtraction operational pattern, the float adding units FaCell1 patterns choosing
Mode is selected for floating-point addition operation pattern；The float adding units FaCell0~FaCell3 performs floating-point and adds deduct computing,
Result of calculation is exported by some timeticks.
The float adding units FaCell input signals include enable signal FaEn, operational pattern Mode, data input
DataA and data input DataB, when enabling signal FaEn and being effective, the float adding units perform floating addition reducing fortune
Calculate, do not perform any operation otherwise, operational pattern Mode carries out floating addition and floating-point subtraction computing selection；The floating add list
, comprising signal output EnOut and data output Result is enabled, when enabling, signal output EnOut is effective for first FaCell output signals
When, the float adding units output floating addition reducing operation result is represented, otherwise operation result is invalid.
The floating-point multiplication unit F mCell input signals are defeated comprising signal FmEn, data input DataA and data are enabled
Enter DataB, when signal FmEn is enabled effectively, the floating-point multiplication unit F mCell performs floating-point multiplication, otherwise described floating
Point multiplication unit F mCell does not perform any operation；The floating-point multiplication unit F mCell output signals include enable signal output
EnOut and data output Result, when enabling signal output EnOut and being effective, the floating-point multiplication unit F mCell outputs are floating
Point multiplication operation result, otherwise operation result are invalid.
The present invention also provides a kind of CM and dish-shaped operation method, realizes that step is as follows：
1) decoding unit completes to decode according to arithmetic operation type, produces related encoded control signal.
2) when arithmetic operation type for floating-point complex is taken the opportunity, execution floating-point complex multiplies fortune under the control of encoded control signal
Calculate, calculating process is divided into the calculating of two steps：The first step, completes floating-point complex multiplication multiplication part；By input operand X1+jY1
Real part and imaginary part with X2+jY2 take out X1, Y1, X2 and Y2 respectively, and then X1 is multiplied with X2 and obtains result X1 × X2, Y1 and Y2
Multiplication obtains result Y1 × Y2, X1 and Y2 and is multiplied to obtain result X1 × Y2, Y1 and X2 and be multiplied to obtain result Y1 × X2；Second step,
Complete floating-point multiplication plus-minus part；Above-mentioned multiplication result of calculation X1 × X2 and Y1 × Y2 are subtracted each other obtain X1 × X2-Y1 ×
Y2, X1 × Y2 are added with Y1 × X2 and obtain X1 × Y2+Y1 × X2, final floating-point complex multiply result of calculation for (X1 × X2-Y1 ×
Y2)+j(X1×Y2+Y1×X2)；
3) when arithmetic operation type is floating-point dish computing, by the real part and void of input operand X1+jY1 and X2+jY2
Take out in portion；X1 is added with X2 and obtains result X1+X2, Y1 and Y2 and be added to obtain result Y1+Y2；X1 and X2 subtract each other and obtain result
X1-X2, Y1 and Y2 subtract each other and obtain result Y1-Y2；It is (X1+X2)+j (Y1+Y2) to finally give plural dish and calculate addition results,
It is (X1-X2)+j (Y1-Y2) that plural dish calculates subtraction result.
The beneficial effects of the invention are as follows：Floating-point complex is realized using existing floating point unit module to multiply and dish-shaped computing.
Floating point unit is divided into float adding units and floating-point multiplication unit by the present invention, by float adding units and floating-point multiplication list
Increase a small amount of interconnection line between metadata port, make to be formed between float adding units and floating-point multiplication unit specific data and lead to
Road, floating point unit FPDP is input to by real part and imaginary part according to the ordering rule of agreement, is produced in decoding unit
Floating-point complex multiplication and floating-point complex butterfly computation can be realized under decoded signal control.The present invention utilizes basic floating-point operation list
Unit, a small amount of interconnection line is increased between floating point unit and constructs hardware data path, and floating point unit hardware is provided by time-space domain
Source be multiplexed, realize floating-point complex multiply with floating-point complex butterfly computation, hardware resource has been saved, than existing CM and dish
Calculation function unit further increases flexibility, and can well realize the parallel and pipeline computing of mass data, obtains
Obtain more preferable real-time performance and resource utilization.
Brief description of the drawings
Fig. 1 is float adding units internal structure schematic diagram.
Fig. 2 is floating-point multiplication unit internal structure schematic diagram.
Fig. 3 realizes electrical block diagram for floating-point complex multiplies with dish-shaped computing.
Electrical block diagram when Fig. 4 is floating-point complex multiplying.
Electrical block diagram when Fig. 5 is floating-point dish computing.
Specific embodiment
The present invention is further described with reference to the accompanying drawings and examples, and the present invention includes but are not limited to following implementations
Example.
Following circuit design is employed in the present invention：
First, floating point unit is designed as float adding units FaCell and floating-point multiplication unit F mCell in the present invention.
The float adding units FaCell input signals include enable signal FaEn, operational pattern Mode, data input
DataA and data input DataB, when enabling signal FaEn and being effective, the float adding units perform floating addition reducing fortune
Calculate, do not perform any operation otherwise, operational pattern Mode carries out floating addition and floating-point subtraction computing selection.The floating add list
, comprising signal output EnOut and data output Result is enabled, when enabling, signal output EnOut is effective for first FaCell output signals
When, the float adding units output floating addition reducing operation result is represented, otherwise operation result is invalid.Drawn in accompanying drawing 1
Internal structure schematic diagram by taking the float adding units FaCell of level Four flowing structure as an example.
The floating-point multiplication unit F mCell input signals are defeated comprising signal FmEn, data input DataA and data are enabled
Enter DataB, when signal FmEn is enabled effectively, the floating-point multiplication unit F mCell performs floating-point multiplication, otherwise described floating
Point multiplication unit F mCell does not perform any operation.The floating-point multiplication unit F mCell output signals include enable signal output
EnOut and data output Result, when enabling signal output EnOut and being effective, the floating-point multiplication unit F mCell outputs are floating
Point multiplication operation result, otherwise operation result are invalid.Depicted in accompanying drawing 2 with the floating-point multiplication unit of level Four flowing structure
Internal structure schematic diagram as a example by FmCell.
The present invention using processor floating point unit carry out floating-point complex multiply and dish computing method circuit structure include one
Individual decoding unit Decode, four floating-point multiplication unit F mCell0~FmCell3, two groups of data selection unit Mux0~Mux1,
FaCell0~FaCell3 and one groups of connection foregoing circuit line of four float adding units.
For convenience of description, assume that input operand is floating-point complex X1+jY1 and X2+jY2 in the present invention.
The decoding unit Decode completes circuit decoding according to the operation Type C Type of input, produces computing
The enable and control signal needed in journey.
The floating-point multiplication unit F mCell0~FmCell3 performs multiplying part in plural multiplication.The floating-point
Data input DataA and data input the DataB port of multiplication unit FmCell0~FmCell3 sequentially input real part X1
With real part X2, imaginary part Y1 and imaginary part Y2, real part X1 and imaginary part Y2, imaginary part Y1 and plural number reality
Portion X2.The enable signal FmEn of the floating-point multiplication unit F mCell0~FmCell3 is decoded by decoding unit and produced.Work as operation
When arithmetic type CType is plural multiplication, decoding unit completes decoding, enables signal FmEn effectively, the floating-point multiplication list
First FmCell0~FmCell3 performs floating-point multiplication, believes by some timeticks output result of calculation Result and enable
Number EnOut, the result of calculation Result of the floating-point multiplication unit F mCell0~FmCell3 are followed successively by X1 × X2, Y1 × Y2,
X1 × Y2 and Y1 × X2, otherwise described floating-point multiplication unit F mCell0~FmCell3 does not perform any operation.During specific execution
Clock beat number is divided by the floating-point multiplication pipeline within a cell structure and determined.When enabling signal output EnOut and being effective, represent
The floating-point multiplication unit F mCell0~FmCell3 output floating-point multiplication results, otherwise described floating-point multiplication unitary operation
Result is invalid.
Data selection unit Mux0~the Mux1 is to being input into the data of float adding units FaCell0~FaCell1
Selected, wherein selection control signal TypeEn is decoded by decoding unit producing.The data selection unit Mux0 is input into number
Signal output EnOut, floating-point multiplication unit F mCell0 result of calculations X1 × X2 are enabled according to for floating-point multiplication unit F mCell0, float
Point multiplication unit F mCell1 result of calculations Y1 × Y2, enable signal FaEn, real part X1 and real part X2；The data
Select unit Mux1 input datas are that floating-point multiplication unit F mCell1 enables signal output EnOut, floating-point multiplication unit
FmCell2 result of calculations X1 × Y2, floating-point multiplication unit F mCell3 result of calculations Y1 × X2, enable signal FaEn, imaginary part
Y1 and imaginary part Y2, wherein enable signal FaEn produced by decoding unit, when operation Type C Type is plural number dish fortune
During calculation, decoded by decoding unit, enable signal FaEn effectively, otherwise enable signal FaEn invalid.When arithmetic operation type is
Floating-point complex is taken the opportunity, in the presence of control signal TypeEn, data selection unit Mux0 output signals MEn, MDataA
Data are selected to enable signal output EnOut, floating-point multiplication unit for floating-point multiplication unit F mCell0 successively with MdataB
FmCell0 result of calculations X1 × X2 and floating-point multiplication unit F mCell1 result of calculations Y1 × Y2, otherwise, the data selection is single
First Mux0 output signals MEn, MDataA and MdataB select data for input enables signal FaEn, real part X1 and answers successively
Number real part X2；When arithmetic operation type for floating-point complex is taken the opportunity, in the presence of control signal TypeEn, the data selection is single
First Mux1 output signals MEn, MDataA and MdataB select data to enable signal output for floating-point multiplication unit F mCell1 successively
EnOut, floating-point multiplication unit F mCell2 result of calculations X1 × Y2 and floating-point multiplication unit F mCell3 result of calculations Y1 × X2, it is no
Then, data selection unit Mux1 output signals MEn, MDataA and MdataB select data to enable signal for input successively
FaEn, imaginary part Y1 and imaginary part Y2.
The float adding units FaCell0~FaCell3 performs floating addition reducing fortune in CM and dish-shaped computing
Calculate.Data input DataA and data input the DataB port of the float adding units FaCell2~FaCell3 sequentially input
Real part X1 and real part X2, imaginary part Y1 and imaginary part Y2.The float adding units FaCell2~
The enable signal FaEn and model selection Mode of FaCell3 are decoded by decoding unit and produced.When operation Type C Type is multiple
During number dish computing, decoding unit completes decoding, and the float adding units FaCell2~FaCell3 enables signal FaEn to be had
Effect, model selection Mode is floating-point subtraction operational pattern, and otherwise, the float adding units FaCell2~FaCell3 enables letter
Number FaEn is invalid.Enable signal FaEn, the data input DataA and data of the float adding units FaCell0~FaCell1
Input DataB ports sequentially input data MEn, MDataA and MdataB of the data selection unit Mux0~Mux1.Pattern
Selection Mode is decoded by decoding unit and produced.When operation Type C Type is for plural number dish computing, decoding unit completes to translate
Code, the float adding units FaCell0~FaCell1 model selections Mode is floating-point addition operation pattern, otherwise, described floating
Point adder unit FaCell0 model selections Mode is floating-point subtraction operational pattern, the float adding units FaCell1 patterns choosing
Mode is selected for floating-point addition operation pattern.The float adding units FaCell0~FaCell3 performs floating-point and adds deduct computing,
Result of calculation is exported by some timeticks, the specific timeticks number that performs is by float adding units inside flowing structure
Divide and determine.In the present invention shown in particular circuit configurations as accompanying drawing 3.
Heretofore described CM and dish-shaped operation method realize that step is as follows：
1) decoding unit completes to decode according to arithmetic operation type, produces related encoded control signal.
2) when arithmetic operation type for floating-point complex is taken the opportunity, execution floating-point complex multiplies fortune under the control of encoded control signal
Calculate, calculating process is divided into the calculating of two steps.The first step, completes floating-point complex multiplication multiplication part.By input operand X1+jY1
Real part and imaginary part with X2+jY2 take out X1, Y1, X2 and Y2 respectively, and then X1 is multiplied with X2 and obtains result X1 × X2, Y1 and Y2
Multiplication obtains result Y1 × Y2, X1 and Y2 and is multiplied to obtain result X1 × Y2, Y1 and X2 and be multiplied to obtain result Y1 × X2；Second step,
Complete floating-point multiplication plus-minus part.Above-mentioned multiplication result of calculation X1 × X2 and Y1 × Y2 are subtracted each other obtain X1 × X2-Y1 ×
Y2, X1 × Y2 are added with Y1 × X2 and obtain X1 × Y2+Y1 × X2, final floating-point complex multiply result of calculation for (X1 × X2-Y1 ×
Y2)+j(X1×Y2+Y1×X2)。
3) floating-point dish computing otherwise, is performed.The real part of input operand X1+jY1 and X2+jY2 and imaginary part are taken out：
X1, Y1, X2 and Y2.X1 is added with X2 and obtains result X1+X2, Y1 and Y2 and be added to obtain result Y1+Y2；X1 subtracts each other with X2 and obtains
As a result X1-X2, Y1 and Y2 subtract each other and obtain result Y1-Y2；It is (X1+X2)+j (Y1+ to finally give plural dish and calculate addition results
Y2), it is (X1-X2)+j (Y1-Y2) that plural number dish calculates subtraction result.
In the present embodiment by taking the level Four flowing structure of floating-point multiplication unit and float adding units as an example, specific embodiment
It is as follows：
1) decoding unit completes to decode according to arithmetic operation type, produces related encoded control signal.
2) when arithmetic operation type for floating-point complex is taken the opportunity, floating-point complex multiplication is performed under the control of decoded signal,
Calculating process is divided into the calculating of two steps.The first step, is input into two floating-point complex (X1+jY1) and (X2+jY2), by two floating-point complex
Real part and imaginary part be sequentially inputted to four floating-point multiplication unit operand ports in the following order：X1, Y1, X1 and Y1 distinguish
The input operand DataA ports of floating-point multiplication unit F mCell0~FmCell3 are input to, X2, Y2, Y2 and X2 are input into respectively
To the decoded signal that the input operand DataB ports of floating-point multiplication unit F mCell0~FmCell3, decoding unit produce
FmEn is input to the enable signal FmEn ports of floating-point multiplication unit F mCell0~FmCell3, and FmEn is ' 1 ' effective, by four
After individual processor clock cycle, four floating-point multiplication unit F mCell0~FmCell3 distinguish output result and are：X1×X2、Y1×
Y2, X1 × Y2 and Y1 × X2, enable output EnOut effective.Second step, it is ' 1 ' that decoding unit produces decoded signal TypeEn, number
According to select unit Mux0 under the control of decoded signal TypeEn, by EnOut, X1 of floating-point multiplication unit F mCell0 × X2 and
Y1 × Y2 transports to enable input FaEn, input operand A and the input operand B ports of float adding units FaCell0 respectively.
It is ' 1 ' that decoding unit produces decoded signal Mode, and the enable input FaEn of float adding units FaCell0 is ' 1 ' effective,
FaCell0 performs floating-point subtraction computing.Data selection unit Mux1 under the control of decoded signal TypeEn, by floating-point multiplication list
EnOut, X1 of first FmCell1 × Y2 and Y1 × X2 transport to enable input FaEn, the input of float adding units FaCell1 respectively
Operand A and input operand B ports.It is ' 0 ' that decoding unit produces decoded signal Mode, float adding units FaCell1's
It is ' 1 ' effective to enable input FaEn, and FaCell1 performs floating-point addition operation.By after four processor clock cycles, floating addition
Method unit F aCell0 exports the real part X1 × X2-Y1 × Y2 of floating-point complex multiplication result, and float adding units FaCell1 is defeated
Go out the imaginary part X1 × Y2+Y1 × X2 of floating-point complex multiplication result, final floating-point complex multiplication result is (X1 × X2-Y1 × Y2)
+j(X1×Y2+Y1×X2).Accompanying drawing 4 show electrical block diagram when performing floating-point complex multiplying.
3) floating-point dish computing otherwise, is performed.Input operand (X1+jY1) and (X2+jY2) real part and void are taken out respectively
Portion X1, Y1, X2 and Y2, data input DataA and data input the DataB port of float adding units FaCell2~FaCell3
Sequentially input real part X1 and real part X2, imaginary part Y1 and imaginary part Y2.Decoding unit completes decoding, pattern choosing
It is ' 1 ' to select Mode, and it is ' 1 ' effective to enable signal FaEn, and float adding units FaCell2~FaCell3 performs floating-point subtraction fortune
Calculate.It is ' 0 ' that decoding unit produces decoded signal TypeEn, data selection unit Mux0 under the control of decoded signal TypeEn,
The enable input that signal FaEn, real part X1 and real part X2 transport to float adding units FaCell0 respectively will be enabled
FaEn, input operand A and input operand B ports；Data selection unit Mux1, will under the control of decoded signal TypeEn
Enable signal FaEn, imaginary part Y1 and imaginary part Y2 transport to respectively float adding units FaCell1 enable input FaEn,
Input operand A and input operand B ports.Decoding unit completes decoding, and model selection Mode is ' 0 ', enables signal FaEn
For ' 1 ' effectively, float adding units FaCell0~FaCell1 performs floating-point addition operation.By four processor clock cycles
Afterwards, the real part X1+X2, float adding units FaCell1 of float adding units FaCell0 outputs floating-point dish computing addition results
The imaginary part Y1+Y2 of output floating-point dish computing addition results, float adding units FaCell2 output floating-point dish computing subtraction knot
The imaginary part Y1-Y2 of the real part X1-X2 of fruit, float adding units FaCell3 output floating-point dish computing subtraction result, finally gives
It is (X1+X2)+j (Y1+Y2) that plural dish calculates addition results, and it is (X1-X2)+j (Y1- that plural number dish calculates subtraction result
Y2).Accompanying drawing 5 show electrical block diagram when performing floating-point dish computing.
Claims (4)
1. a kind of device that CM and butterfly computation are carried out using processor floating point unit, an including decoding unit
Decode, four floating-point multiplication unit F mCell0~FmCell3, Mux0~Mux1 and four floating-point of two groups of data selection units
Adder unit FaCell0~FaCell3, it is characterised in that：
For the floating-point complex X1+jY1 and X2+jY2 that are input into, operation types of the decoding unit Decode according to input
CType completes circuit decoding, produces and enables and control signal；
The floating-point multiplication unit F mCell0~FmCell3 performs multiplying part in plural multiplication；The floating-point multiplication
Data input DataA and data input the DataB port of unit F mCell0~FmCell3 sequentially input real part X1 and answer
Number real part X2, imaginary part Y1 and imaginary part Y2, real part X1 and imaginary part Y2, imaginary part Y1 and real part
X2；The enable signal FmEn of the floating-point multiplication unit F mCell0~FmCell3 is decoded by decoding unit and produced；When operation is transported
When calculation Type C Type is for plural multiplication, decoding unit completes decoding, and enable signal FmEn is effective, the floating-point multiplication unit
FmCell0~FmCell3 performs floating-point multiplication, by some timeticks output result of calculation Result and enable signal
EnOut, the result of calculation Result of the floating-point multiplication unit F mCell0~FmCell3 is followed successively by X1 × X2, Y1 × Y2, X1
× Y2 and Y1 × X2, otherwise described floating-point multiplication unit F mCell0~FmCell3 does not perform any operation；When enabling, signal is defeated
Go out EnOut it is effective when, represent the floating-point multiplication unit F mCell0~FmCell3 output floating-point multiplication results, otherwise institute
State floating-point multiplication unitary operation result invalid；
Data selection unit Mux0~the Mux1 is carried out to the data being input into float adding units FaCell0~FaCell3
Selection, selection control signal TypeEn is decoded by decoding unit and produced；The data selection unit Mux0 input datas are floating-point
Multiplication unit FmCell0 enables signal output EnOut, floating-point multiplication unit F mCell0 result of calculations X1 × X2, floating-point multiplication list
First FmCell1 result of calculations Y1 × Y2, enable signal FaEn, real part X1 and real part X2；The data selection unit
Mux1 input datas are that floating-point multiplication unit F mCell1 enables signal output EnOut, floating-point multiplication unit F mCell2 calculating knot
Fruit X1 × Y2, floating-point multiplication unit F mCell3 result of calculations Y1 × X2, enable signal FaEn, imaginary part Y1 and imaginary part
Y2, enables signal FaEn and is produced by decoding unit, single by decoding when operation Type C Type is for plural number dish computing
Unit's decoding, enables signal FaEn effectively, otherwise enables signal FaEn invalid；When arithmetic operation type for floating-point complex is taken the opportunity,
In the presence of control signal TypeEn, data selection unit Mux0 output signals MEn, MDataA and MdataB are selected successively
Data are that floating-point multiplication unit F mCell0 enables signal output EnOut, floating-point multiplication unit F mCell0 result of calculations X1 × X2
With floating-point multiplication unit F mCell1 result of calculations Y1 × Y2, otherwise, the data selection unit Mux0 output signals MEn,
MDataA and MdataB select data to enable signal FaEn, real part X1 and real part X2 for input successively；As computing behaviour
Make type for floating-point complex is taken the opportunity, in the presence of control signal TypeEn, the data selection unit Mux1 output signals
MEn, MDataA and MdataB select data to enable signal output EnOut, floating-point multiplication for floating-point multiplication unit F mCell1 successively
Unit F mCell2 result of calculations X1 × Y2 and floating-point multiplication unit F mCell3 result of calculations Y1 × X2, otherwise, the data choosing
Select unit Mux1 output signals MEn, MDataA and MdataB selects data to enable signal FaEn, imaginary part Y1 for input successively
With imaginary part Y2；
The float adding units FaCell0~FaCell3 performs floating addition reducing computing in CM and dish-shaped computing；Institute
State float adding units FaCell2 data inputs DataA and data input DataB ports and sequentially input real part X2 and plural number
Real part X1；Float adding units FaCell3 data inputs DataA and data input DataB ports sequentially input imaginary part Y1
With imaginary part Y2；The enable signal FaEn and model selection Mode of the float adding units FaCell2~FaCell3 are by translating
Code unit decoding is produced；When operation Type C Type is for plural number dish computing, decoding unit completes decoding, the floating-point
Adder unit FaCell2~FaCell3 enables signal FaEn effectively, and model selection Mode is floating-point subtraction operational pattern, otherwise,
It is invalid that the float adding units FaCell2~FaCell3 enables signal FaEn；The float adding units FaCell0~
It is single that enable signal FaEn, the data input DataA of FaCell1 and data input DataB ports sequentially input the data selection
Data MEn, MDataA and MdataB of first Mux0~Mux1；Model selection Mode is decoded by decoding unit and produced；When operation is transported
When calculating Type C Type for plural number dish computing, decoding unit completes decoding, the float adding units FaCell0~FaCell1
Model selection Mode is floating-point addition operation pattern, and otherwise, the float adding units FaCell0 model selections Mode is floating-point
Subtraction pattern, the float adding units FaCell1 model selections Mode is floating-point addition operation pattern；The floating addition
Method unit F aCell0~FaCell3 performs floating-point and adds deduct computing, and result of calculation is exported by some timeticks.
2. the device that CM and butterfly computation are carried out using processor floating point unit according to claim 1, its feature
It is：The float adding units FaCell input signals include enable signal FaEn, operational pattern Mode, data input
DataA and data input DataB, when enabling signal FaEn and being effective, the float adding units perform floating addition reducing fortune
Calculate, do not perform any operation otherwise, operational pattern Mode carries out floating addition and floating-point subtraction computing selection；The floating add list
, comprising signal output EnOut and data output Result is enabled, when enabling, signal output EnOut is effective for first FaCell output signals
When, the float adding units output floating addition reducing operation result is represented, otherwise operation result is invalid.
3. the device that CM and butterfly computation are carried out using processor floating point unit according to claim 1, its feature
It is：The floating-point multiplication unit F mCell input signals include enable signal FmEn, data input DataA and data input
DataB, when signal FmEn is enabled effectively, the floating-point multiplication unit F mCell performs floating-point multiplication, otherwise described floating-point
Multiplication unit FmCell does not perform any operation；The floating-point multiplication unit F mCell output signals include enable signal output
EnOut and data output Result, when enabling signal output EnOut and being effective, the floating-point multiplication unit F mCell outputs are floating
Point multiplication operation result, otherwise operation result are invalid.
4. a kind of method for carrying out CM and butterfly computation using processor floating point unit using claim 1 described device,
It is characterized in that comprising the steps：
1) decoding unit completes to decode according to arithmetic operation type, produces related encoded control signal；
2) when arithmetic operation type for floating-point complex is taken the opportunity, floating-point complex multiplication is performed under the control of encoded control signal,
Calculating process is divided into the calculating of two steps：The first step, completes floating-point complex multiplication multiplication part；By input operand X1+jY1 and X2
The real part and imaginary part of+jY2 take out X1, Y1, X2 and Y2 respectively, and then X1 is multiplied with X2 and obtains result X1 × X2, and Y1 is multiplied with Y2
Obtain result Y1 × Y2, X1 and Y2 and be multiplied to obtain result X1 × Y2, Y1 and X2 and be multiplied to obtain result Y1 × X2；Second step, completes
Floating-point multiplication adds and subtracts part；Above-mentioned multiplication result of calculation X1 × X2 and Y1 × Y2 are subtracted each other and obtains X1 × X2-Y1 × Y2, X1
× Y2 is added with Y1 × X2 and obtains X1 × Y2+Y1 × X2, and final floating-point complex multiplies result of calculation for (X1 × X2-Y1 × Y2)+j
(X1×Y2+Y1×X2)；
3) when arithmetic operation type is floating-point dish computing, the real part and imaginary part of input operand X1+jY1 and X2+jY2 are taken
Go out；X1 is added with X2 and obtains result X1+X2, Y1 and Y2 and be added to obtain result Y1+Y2；X1 and X2 subtract each other and obtain result X1-X2,
Y1 and Y2 subtract each other and obtain result Y1-Y2；It is (X1+X2)+j (Y1+Y2), plural dish to finally give plural dish and calculate addition results
It is (X1-X2)+j (Y1-Y2) that shape calculates subtraction result.
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| CN1996235A (en) * | 2006-12-31 | 2007-07-11 | 武汉大学 | Floating-point complex multiplier |
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