CN104298158A - Intelligent device address encoding method based on input-output structure - Google Patents
Intelligent device address encoding method based on input-output structure Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2612—Data acquisition interface
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Abstract
The invention relates to an intelligent device address encoding method based on an input-output structure and belongs to the technical field of distributed type intelligent electric devices. Input ports and output ports are arranged at submodules. The submodules are connected in sequence in an input-output structure mode. Previous level submodule output is connected into next level submodule input. After the submodules receive address information, address codes corresponding to the address information are obtained by computing and are represented on an output position, after the next level submodule input receives the output position information with the address code information of the previous level submodule, address code information with scalar implicature is obtained and is represented at the output position, and accordingly address sequence setting is completed. The risk of repeated addresses is avoided, a system structure is not limited by a back plate structure, expansion capability is high, free expanding can be carried out in the range allowed by the input position and the output position, when the submodules are damaged, setting of address information is of no need when new modules corresponding to the modules replace the modules, and replacing is easy and convenient.
Description
Technical field
The present invention relates to a kind of intelligent apparatus address coding method based on input and output structure, belong to distributed intelligence electric device technical field.
Background technology
All be configured with programmable logic chip in primary module and submodule in the device of decentralized layout, its extended capability significantly strengthens relative to the device of existing centerized fusion.Primary module and submodule communication need to set up id information corresponding to each module, the id information of submodule generally adjusted has 2 kinds of modes, one is the id information of the submodule being set up each access by backboard and identification circuit, two is by submodule preset ID information, the id information of each submodule of artificial guarantee and its one_to_one corresponding.
1, the id information of submodule is set up by backboard and identification circuit
Chinese patent CN201310629396.1 describes a kind of intelligent power device, programmable logic controller (PLC) is introduced in submodule, significantly reduce the computing pressure of programmable logic controller (PLC) in primary module, set expandability significantly strengthens, primary module programmable logic controller (PLC) does not participate in the process in early stage of data simultaneously, decreases system resource, in the occasion that outside expansion demand is larger, can also consider that appropriateness reduces system cost with more rudimentary processor.Consisting of apparatus structure as shown in Figure 1.
In this device architecture, what adopt the coding of address is backboard coded system.The data bit that backboard information response is different, is realized by means such as gated fashion,
During submodule access device, by representing that No. ID of its on-position identifies, when plug-in unit accesses, this No. ID is activated, primary module by poll, submodule electrifying startup automatically on send the submodule detecting new access here, be its resource allocation in primary module.
ID implementation has three kinds: 1) realize in primary module, such as primary module accesses the position of backboard A, B, N respectively by chip selection signals such as CS0, CS1, CSn, as submodule access backboard A, CS0 is activated, primary module recognin module access backboard A position; 2) realize in backboard, such as, there is out entry loop in backboard, common port access 5V power supply, backboard A, B, N access position KR1, KR2, KRn position of primary module respectively, in submodule, corresponding tergal position is short-circuited terminal, when submodule access backboard A position, KR1 is activated, and represents backboard A position access submodule; 3) realize in submodule, such as, in submodule, have out entry loop, public termination 5V power supply, backboard correspondence position is short circuit state, and when submodule access backboard, corresponding loop is activated, corresponding KR accesses primary module and opens in entry loop, represents that this position module ID is activated.No. ID can also be transferred to primary module by communication data in submodule and realize.
The shortcoming of the method: the mode that the coded system of above three kinds No. ID all adopts backboard to be combined with submodule is carried out, no matter be realize in backboard or realize in primary module, also or in submodule realize, its basis set up is primary module and sets up communication relationship by backboard and submodule, and the shortcoming of backboard can not arbitrarily be expanded exactly, be limited to space layout's impact of existing backboard cabling, the submodule quantity of its expansion is restricted equally.
2, preset address coding mode information
In the submodule of distributed arrangement, people is the address information pre-setting device, to the submodule of each access according to certain regular method, carries out adjusting of the id information representing module's address information.
As shown in Figure 2, for a certain device to its submodule accessed respectively preset address be 1,2,3 its id informations corresponding, when anyon module or all submodule access, primary module all can be distinguished according to its id information.
The shortcoming of the method: id information of adjusting is cumbersome, and due to the impact of id information tuning process, there is the risk that initial address repeats, cause data collision, failure of apparatus.When submodule needs to change, its id information that needs to adjust with to be replaced submodule consistent, increase operation complexity and risk of error.
Summary of the invention
The object of this invention is to provide a kind of intelligent apparatus address coding method based on input and output structure, caused the problem expanded greatly and is not easily relied on to backboard to solve in prior art to be undertaken encoding by backboard mode.
The present invention is for solving the problems of the technologies described above and providing a kind of intelligent apparatus address coding method based on input and output structure, and this address coding method comprises the following steps:
1) in each submodule of intelligent apparatus, inbound port and output port is opened in configuration, is connected between each submodule by opening inbound port and outputing port order, prime submodule output that port accesses rear class submodule open inbound port;
2) prime submodule carries out address set operation to rear class submodule by opening into and output port, and set address information adopts differential processing mode to obtain.
Described step 2) in differential process can adopt the mode as the address of this module after differential for the address information of prime module process, the address information that also the prime module amount of outputing can be reflected, directly as the address of this module, adopts the amount of outputing to drive rear class submodule after this address date of differential process.
Described step 1) adopt hand-in-hand tandem, the submodule position one_to_one corresponding in order of address information and physical connection between each submodule.
Initial set acquisition is carried out by primary module in the address of the described submodule directly accessed with primary module.
Described step 2) be completed by the address encoding unit be arranged in each submodule, the input end of the address encoding unit in each submodule is connected with the port of outputing of prime submodule, output terminal is connected with the inbound port of opening of rear class submodule, described address encoding unit is for receiving the address information of prime submodule, and after differential calculating, draw the address of rear class submodule, and by the inbound port of opening of rear class submodule, adjusted information in rear class submodule transfer address.
Address latch unit is also provided with, for latching the address information of address encoding unit in this module in described each submodule.
Described address encoding unit can adopt DSP, CPU or adding circuit to realize.
Described opening inbound port and output port can adopt I/O port or GPIO mode to realize.
The invention has the beneficial effects as follows: the present invention arranges input and output structure at each submodule, by frame mode, submodule order is connected, prime submodule output access rear class submodule open into, after submodule receiver address information, computing draws address code corresponding with it, and embody outputing on position, rear class submodule open reception prime submodule with address code information output an information after, computing draws the address code information with differential implication, and output on position at it and embody, thus complete sequence of addresses and adjust.The present invention has evaded the risk of repeat to address (RA), and system architecture is not by the structural limitations of backboard, and extended capability is strong, can reach the object of arbitrarily expansion in the scope opening, output position permission; Submodule address is corresponding with the physical connection mode of module, is convenient to the renewal of configuration information; When submodule damages, change the setting operation that new module corresponding to this module does not need address information, Renewal process is simple and convenient.
Accompanying drawing explanation
Fig. 1 is the intelligent power device Organization Chart of master-slave controller modular structure;
Fig. 2 is the structural representation of preset ID information;
Fig. 3 is device code cell schematics in submodule of the present invention;
Fig. 4 is geocoding process flow diagram;
Fig. 5 is input and output structure self-identifying id information structural representation;
Fig. 6 is input and output structure self-identifying id information structural representation in the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described.
In the intelligent power device of decentralized layout, because each submodule containing programmable logic chip is relatively independent, need when primary module and submodule communication to carry out encoding operation to the address of submodule.Mode by backboard in prior art is encoded, comparatively large to the dependence of backboard, and system configuration flexibility ratio is limited to the layout structure of backboard, can not be applicable to the apparatus structure of the decentralized layout of arbitrary extension.
For this reason, the present invention proposes a kind of intelligent apparatus address coding method based on input and output structure, primary module is connected with submodule, submodule is connected with rear class submodule by designated lane, by preset input and output frame mode, submodule order is connected, prime submodule output access rear class submodule open into, after submodule receiver address information, computing draws address code corresponding with it, and embody outputing on position, rear class submodule open reception prime submodule with address code information output an information after, computing draws the address code information with differential implication, and output on position at it and embody, complete sequence of addresses to adjust, the submodule expanded function of sufficient amount can be met by this mode, and there is not the invalid or polyisomenism in address.The method comprises the following steps.
1. in each submodule, configuration is opened inbound port and is outputed port, opening inbound port and outputing port to adopt I/O structure to realize, be linked in sequence between submodule each in intelligent apparatus by input and output structural unit, connected mode is 1 to 1 mode, hand-in-hand tandem is adopted between each submodule, prime submodule is outputed access rear class submodule and is opened into, the submodule position one_to_one corresponding in order of address information and physical connection.Here input and output structure adopts the hardware circuit of the mode that is linked in sequence, and can be I/O structure, also can be other GPIO modes, the present invention be described for common I/O structure.
2. prime submodule carries out address set operation to rear class submodule, and set address information carries out differential process one by one.This process is completed by the address encoding unit be arranged in each submodule, the input end of the address encoding unit in each submodule is connected with the port of outputing of prime submodule, output terminal is connected with the inbound port of opening of rear class submodule, described address encoding unit is based on this module's address information, draw the address of rear class submodule after differential calculating, and address is sent to rear class submodule to adjust information by the inbound port of opening of rear class submodule.Also be provided with address latch unit in each submodule, at module's address after setting completed, put address latch signal, the address date after storage initialization and more new change.
The attached structural representation that Figure 3 shows that unit address coding unit in submodule, receives the intake data with address information by receiving element, and process draws address, and recycling is outputed signal and rear class submodule transmitted to the address information of adjusting, and its process is 3 steps.
What the first, receiving element (intake) received that prime module adjusts information with address outputs semaphore, submits to address encoding unit.
The second, address encoding unit extracts intake information, draws address information, stored in address latch unit, and the address tuning process of complete cost module.
Three, address encoding unit is based on this module's address information, the data of information of being adjusted with address to the transmission of rear class submodule by driver element after differential calculating.
Attachedly Figure 4 shows that geocoding process flow diagram, first judge whether to be in address latch state, adjusts Post RDBMS operation in address, and avoiding powers on again re-executes address and to adjust operation.
When address is in non-latch mode, executive address encoding operation, reads information in receiver module, is converted to the address of this module by address encoding unit.The I/O module of submodule can represent its address implication by coded system, and as the form of 8421 yards, 0001 represents first submodule address information accessed, and 0010 represents second submodule address information accessed.
Can after the address information receiving prime module, differential process obtains the address of this module; Also can after receiving prime module's address information, directly as the address of this module, as the amount of outputing information-driven rear class submodule after this address date of differential process.
To adjust information by transmitting address by driver module to rear class submodule after differential operation.Address information is worth by cumulative one-level difference into information by opening usually, is 1 as differential, when to open into an information be 0000 to submodule, level difference operation show that the address of this module is 1, draw by address the information of outputing, it is 0001 that address 1 correspondence outputs information, by that analogy.
The outputing position and can be connected into position with opening of first submodule of primary module, adjusting of initial bit address is carried out to this submodule, address as first submodule of adjusting is 10, the submodule sequence address be then connected with this submodule order is encoded by 10, and level difference operation draws respective address successively.
The address information computing of submodule, by geocoding processing unit, after the differential process of information of opening, draws the regular address information of tool, and is reflected in the information of outputing.Being equipped with geocoding processing unit in module can be DSP, CPU or other intelligent chips, also can be simple adding circuit, realizes opening to be converted to into signal outputing signal, and order adds step-length operation.
The method can be applicable to need to connect independently multiple device and consists of the occasion of a large scale system network, adjust by carrying out address to the primary module of each device, adjusting in the address that inside modules completes whole submodule, and then adjusts in the address completing whole device internal module.
The structure of 16 submodules is accessed below so that the detailed process of intelligent apparatus address provided by the present invention automatic coding to be described for a primary module, each submodule is configured with 4 tunnels and opens and output into, 4 roads, corresponding geocoding 0001-1111 and 0000 amounts to 16 modes according to 8421 coded systems, but 0000 is not counted in address transfer mode for initial bit, therefore can support the access of 15 submodules.
Implementation, prime is outputed access rear class and is opened into structure, and be connected in series successively, 4 roads are outputed 4 tunnels and opened into structure, submodule employing order access way, guarantees to open to connect into outputing with front stage arrangement.
Primary module preset address, as outputed position 0001, corresponding 8421 yards is 1, after then first submodule receives and opens information, address is taken as 1, and the address that arranges that differential process obtains rear class submodule is 1+1, and the address information that arranges according to rear class submodule drives the position of outputing of this submodule to be 0010;
After 2nd submodule reception prime submodule outputs information 0010, address is taken as 2, and the address that arranges that differential process obtains rear class submodule is 2+1, and the position of outputing driving this submodule is 0011;
After 3rd submodule reception prime submodule outputs information 0011, address is taken as 3, and the address that arranges that differential process obtains rear class submodule is 3+1, and the position of outputing driving this submodule is 0100;
By that analogy, the 15th submodule receives after prime submodule outputs information 1111, and address is taken as 15, accesses thereafter submodule again and there will be address polyisomenism, therefore 4 open into/output the expansion structure of structural support 15 submodules.
After completing geocoding, the geocoding of the distributed intelligence device submodule that physical connection mode as shown in Figure 4 realizes is embodied as 1,2,3 ... 15, be one-to-one relationship with physical connection.
Claims (8)
1. based on an intelligent apparatus address coding method for input and output structure, it is characterized in that, this address coding method comprises the following steps:
1) in each submodule of intelligent apparatus, inbound port and output port is opened in configuration, is connected between each submodule by opening inbound port and outputing port order, prime submodule output that port accesses rear class submodule open inbound port;
2) prime submodule carries out address set operation to rear class submodule by opening into and output port, and set address information adopts differential processing mode to obtain.
2. the intelligent apparatus address coding method based on input and output structure according to claim 1, it is characterized in that, described step 2) in differential process can adopt the mode as the address of this module after differential for the address information of prime module process, the address information that also the prime module amount of outputing can be reflected, directly as the address of this module, adopts the amount of outputing to drive rear class submodule after this address date of differential process.
3. the intelligent apparatus address coding method based on input and output structure according to claim 2, it is characterized in that, described step 1) adopt hand-in-hand tandem, the submodule position one_to_one corresponding in order of address information and physical connection between each submodule.
4. the intelligent apparatus address coding method based on input and output structure according to claim 3, is characterized in that, initial set acquisition is carried out by primary module in the address of the described submodule directly accessed with primary module.
5. the intelligent apparatus address coding method based on input and output structure according to claim 4, it is characterized in that, described step 2) be completed by the address encoding unit be arranged in each submodule, the input end of the address encoding unit in each submodule is connected with the port of outputing of prime submodule, output terminal is connected with the inbound port of opening of rear class submodule, described address encoding unit is for receiving the address information of prime submodule, and after differential calculating, draw the address of rear class submodule, and by the inbound port of opening of rear class submodule, adjusted information in rear class submodule transfer address.
6. the intelligent apparatus address coding method based on input and output structure according to claim 4, is characterized in that, is also provided with address latch unit in described each submodule, for latching the address information of address encoding unit in this module.
7. the intelligent apparatus address coding method based on input and output structure according to claim 4, is characterized in that, described address encoding unit can adopt DSP, CPU or adding circuit to realize.
8. the intelligent apparatus address coding method based on input and output structure according to claim 4, is characterized in that, described opening inbound port and output port can adopt I/O port or GPIO mode to realize.
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