CN104283740A - Method for online measurement of Ethernet frequency deviation - Google Patents
Method for online measurement of Ethernet frequency deviation Download PDFInfo
- Publication number
- CN104283740A CN104283740A CN201410570418.6A CN201410570418A CN104283740A CN 104283740 A CN104283740 A CN 104283740A CN 201410570418 A CN201410570418 A CN 201410570418A CN 104283740 A CN104283740 A CN 104283740A
- Authority
- CN
- China
- Prior art keywords
- frequency deviation
- clock
- value
- water level
- asynchronous fifo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Disclosed is a method for online measurement of Ethernet frequency deviation. According to the method, frequency deviation between an Ethernet line recovery clock and a reference clock is directly measured, and the core function is realized by means of an FPGA; a measurement controller controls an asynchronous FIFO to conduct write operation under the clock to be measured and conduct read operation under the reference clock; a cycle counter calculates the number of reference clock cycles needed for increasing or reducing the initial value of the reading water level of the FIFO to a decision value in real time; a decision depth calculator dynamically calculates the decision depth according to the number of cycles to enable basically same precision to be kept within the range of +/-100 ppm; a microprocessor reads the values of frequency deviation indication of the FPGA, decision depth and the number of cycles through an SPI and calculates the frequency deviation of the clock to be measured, so that whether requirements for +/-100 ppm defined by IEEE802.3 are met is judged and warning and statistics of abnormal conditions are conducted. The method can be implanted into an Ethernet test instrument to measure Ethernet frequency deviation in real time.
Description
Technical field
The invention belongs to ethernet test technical field, specifically, relate to a kind of On-line Measuring Method realizing Ethernet frequency deviation.
Background technology
In ethernet test field, need the online clock frequency deviation measuring Ethernet.IEEE 802.3 defines Ethernet frequency deviation should in ± 100 ppm.This proposes higher requirement to the precision of frequency deviation measurement.In engineering, two kinds of method of measurement that frequency meter is conventional: one is in a period of time T, counts clock to be measured, is worth for N, and calculating clock frequency to be measured is N/T.This method certainty of measurement is poor, and directly cannot measure frequency deviation; Another kind is the standard time clock by higher frequency, measures the cycle of clock to be measured, converts and obtains the frequency of clock to be measured.This method improves the clock signal that precision needs upper frequency, causes burden, and directly cannot measure frequency deviation to hardware designs.
Summary of the invention
The object of the invention is the sampled clock signal that will solve existing frequency deviation measurement low precision or need upper frequency, directly cannot measure the problem of frequency deviation, a kind of Ethernet frequency deviation On-line Measuring Method is provided.
The hardware components of Ethernet frequency deviation On-line Measuring Method foundation provided by the invention comprises microprocessor and FPGA, FPGA comprise asynchronous FIFO, cycle rate counter, Mersure Controler, water level output, frequency deviation instruction and dicision depth calculator.The write clock signal of asynchronous FIFO is inputted by clock to be measured, and read clock signal is inputted by reference clock, reset signal, write enable signal, reads enable signal and is inputted by Mersure Controler; The clock signal of cycle rate counter is inputted by reference clock, and clearing and the enable signal of cycle rate counter are inputted by Mersure Controler, and periodicity signal outputs to Mersure Controler and dicision depth calculator; Dicision depth calculator exports dicision depth value to water level output module; Water level output module output positively biased decision value and negative bias decision value are to Mersure Controler.
The concrete operation step of the inventive method is as follows:
1st, ethernet line recovered clock is as clock to be measured, directly inputs after FPGA, writes clock as asynchronous FIFO.When not starting frequency deviation measurement, Mersure Controler is in idle condition always; When Mersure Controler is in idle condition, Mersure Controler reset asynchronous FIFO and cycle rate counter; When after startup frequency deviation measurement, Mersure Controler jumps to init state by idle condition;
2nd, when Mersure Controler is in init state, writing of unlatching asynchronous FIFO is enable; Asynchronous FIFO carries out write operation under clock to be measured, and the water level of reading of asynchronous FIFO starts to rise; When asynchronous FIFO read water level equal water level initial value time, Mersure Controler jumps to measuring state by init state;
3rd, when Mersure Controler is in measuring state, open the enable of cycle rate counter, reference clock is counted; The read-write of simultaneously opening asynchronous FIFO is enable, and asynchronous FIFO carries out write operation under clock to be measured, under reference clock, carry out read operation; If there is difference on the frequency between clock to be measured and reference clock, so the reading water level unidirectional change will occur of asynchronous FIFO; When the water level of reading of asynchronous FIFO rises to positively biased decision value or drops to negative bias decision value, or when the periodicity that cycle rate counter exports is greater than permissible accuracy, epicycle measurement completes, and Mersure Controler jumps to idle condition by measuring state, and the periodicity that lock-up cycle counter exports;
If the water level of reading of the 4th asynchronous FIFO rises to positively biased decision value, frequency deviation indicated value is " just "; Or asynchronous FIFO read water level decreasing to negative bias decision value, frequency deviation indicated value is " bearing "; Otherwise frequency deviation indicated value is " zero ";
If the significant bit number of the 5th periodicity binary value is very few, certainty of measurement can be caused to reduce, and now dicision depth calculator carries out binary shift left to dicision depth value; If periodicity effective number of bits is too much, Measuring Time can be caused long, now binary shift right is carried out to dicision depth value; So both can ensure that measurement meets required precision, can reduce unnecessary Measuring Time again;
6th, water level output module calculates water level positively biased decision value and negative bias decision value according to dicision depth value, tests for next round; Wherein, water level positively biased decision value=water level initial value+dicision depth value, negative bias decision value=water level initial value-dicision depth value;
7th, microprocessor reads the periodicity of FPGA by SPI interface, and dicision depth value and frequency deviation indicated value carry out frequency deviation PPM calculating:
7.1st, frequency deviation indicated value is " zero ", and the frequency deviation between clock to be measured and reference clock equals 0, unit ppm;
7.2nd, frequency deviation indicated value is " just ", and the frequency deviation between clock to be measured and reference clock equals
;
7.3rd, frequency deviation indicated value is " bearing ", and the frequency deviation between clock to be measured and reference clock equals
.
advantage of the present invention and beneficial effect:the inventive method goes to calculate frequency deviation without the need to the concrete frequency values measuring clock to be measured and reference clock, but directly measures the frequency deviation between clock to be measured and reference clock.And without the need to high frequency sampling clock, just can have higher precision, and the precision that basic maintenance is identical in ± 100 ppm.
Accompanying drawing explanation
Fig. 1 is the structured flowchart realizing the frequency deviation measurement of 1000BASE-SX ethernet clock in the embodiment of the present invention.
Fig. 2 is the schematic diagram that in the embodiment of the present invention, asynchronous FIFO reads water level.
Fig. 3 is the state transition figure of Mersure Controler in the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, hereafter using the frequency deviation measurement of 1000BASE-SX ethernet clock as instantiation, by reference to the accompanying drawings a nearly step will be done to the technical program and describes in detail.Should be appreciated that instantiation described herein only in order to explain the present invention, be not limited to the present invention.
Adopt and support that 1000BASE-SX Ethernet light mouth PHY chip is recovered line clock.Under normal circumstances, recovered clock frequency is 125MHz ± 100 ppm.Recovered clock exceeds this frequency range, be then abnormal conditions.This implementation requirements does accurate measurement to the frequency deviation within the scope of the ppm of 125MHz ± 200, to being greater than ± and the frequency deviation of 200 ppm scopes only indicates it to be greater than or less than 200 ppm.The recovered clock of Ethernet light mouth PHY, as clock to be measured, directly inputs FPGA.Clock source exports 125MHz clock as with reference to clock, directly inputs FPGA.As shown in Figure 1, hardware components of the present invention comprises microprocessor and FPGA, FPGA are provided with lower component:
1) asynchronous FIFO a: width is 1 bit, the degree of depth is the asynchronous FIFO of 1024.Write clock signal is inputted by clock to be measured; Read clock signal is inputted by reference clock; Reset signal, write enable signal, reads enable signal and is inputted by Mersure Controler; Read waterline signal and output to Mersure Controler;
2) cycle rate counter: the counter of 29 bit bit wides.Clock signal is inputted by reference clock, and counting resets and count enable signal is inputted by Mersure Controler;
3) dicision depth calculator: periodicity signal is inputted by cycle rate counter, dicision depth value outputs to water level output module.Dicision depth is only provided with 3 values, and 16 hex value are respectively 0xF, 0x3C, 0xF0, and wherein default value is 0xF.If the effective number of bits of periodicity binary value is less than 23, then dicision depth binary value moves to left 2 bits; If the effective number of bits of periodicity is greater than 26, then dicision depth binary value moves to right 2 bits;
4) water level exports: according to dicision depth value, calculates positively biased decision value and negative bias decision value, outputs to Mersure Controler.Wherein, positively biased decision value=water level initial value+dicision depth value=511+ dicision depth value, negative bias decision value=water level initial value-dicision depth value=511-dicision depth value;
5) Mersure Controler: the initialization and the operation that control asynchronous FIFO and cycle rate counter.If open frequency is measured, Mersure Controler jumps to measuring state by idle condition.When measuring state, when the water level of reading of asynchronous FIFO rises to positively biased decision value or drops to negative bias decision value, or when the periodicity that cycle rate counter exports is greater than permissible accuracy, epicycle measurement completes, Mersure Controler jumps to idle condition by measuring state, and the periodicity that lock-up cycle counter exports.
6) deviation indicator: if the water level of reading of asynchronous FIFO rises to positively biased decision value, frequency deviation is designated as positively biased, and binary value is " 01 "; Or asynchronous FIFO read water level decreasing to negative bias decision value, frequency deviation is designated as negative bias, and binary value is " 10 "; Otherwise frequency deviation is designated as zero partially, and binary value is " 00 ";
The concrete steps measured the frequency deviation clock that is+10ppm are as follows:
1st, because the default value of dicision depth is 0xF, therefore, first round test will be measured under dicision depth, positively biased decision value and negative bias decision value are respectively 15,526 and 496 these group parameters;
When not starting frequency deviation measurement, Mersure Controler is in idle condition always; When Mersure Controler is in idle condition, Mersure Controler reset asynchronous FIFO and cycle rate counter; When after startup frequency deviation measurement, Mersure Controler jumps to init state by idle condition;
2nd, when Mersure Controler is in init state, writing of unlatching asynchronous FIFO is enable; Asynchronous FIFO carries out write operation under clock to be measured, and the water level of reading of asynchronous FIFO starts to rise; When asynchronous FIFO read water level equal water level initial value 511 time, Mersure Controler jumps to measuring state by init state;
3rd, when Mersure Controler is in measuring state, open the enable of cycle rate counter, reference clock is counted; The read-write of simultaneously opening asynchronous FIFO is enable, and asynchronous FIFO carries out write operation under clock to be measured, under reference clock, carry out read operation; If there is difference on the frequency+10 ppm between clock to be measured and reference clock, so the water level of reading of asynchronous FIFO slowly rises; When asynchronous FIFO read water level rise to positively biased decision value 526 time, epicycle measurement completes, and Mersure Controler jumps to idle condition by measuring state, and lock-up cycle counter export periodicity 0x15e799;
4th, the water level of reading of asynchronous FIFO rises to positively biased decision value, then frequency deviation indicated value is " 01 ";
5th, dicision depth calculator exports new dicision depth value according to the significant bit number of periodicity binary value, and now the effective number of bits of periodicity binary value is 21, then new dicision depth value is 0x3C, and namely 60;
6th, water level output module calculates water level positively biased decision value and negative bias decision value according to dicision depth value, is respectively 571 and 451, tests for next round;
7th, test under this new group parameter, step is constant.Due to the increase of dicision depth, periodicity will increase, and measurement result periodicity is 0x585A76.Significant bit number is 23, and new dicision depth is still 0x3C, tests for next round;
8th, microprocessor reads the periodicity 0x585A76 of FPGA by SPI interface, and dicision depth value 0x3C and frequency deviation indicated value " 01 ", carry out frequency deviation PPM calculating: frequency deviation is
Microprocessor according to frequency offset calculation result, can show frequency deviation value, frequency deviation alarm in real time, and frequency deviation alarm statistics etc., carry out corresponding man-machine interaction.
Claims (1)
1. an Ethernet frequency deviation On-line Measuring Method, is characterized in that, the hardware components of the method foundation comprises microprocessor and FPGA, FPGA comprise asynchronous FIFO, cycle rate counter, Mersure Controler, water level output, frequency deviation instruction and dicision depth calculator; The write clock signal of asynchronous FIFO is inputted by clock to be measured, and read clock signal is inputted by reference clock, reset signal, write enable signal, reads enable signal and is inputted by Mersure Controler; The clock signal of cycle rate counter is inputted by reference clock, and clearing and the enable signal of cycle rate counter are inputted by Mersure Controler, and periodicity signal outputs to Mersure Controler and dicision depth calculator; Dicision depth calculator exports dicision depth value to water level output module; Water level output module output positively biased decision value and negative bias decision value are to Mersure Controler;
The inventive method comprises the following steps:
1st, ethernet line recovered clock is as clock to be measured, directly inputs after FPGA, writes clock as asynchronous FIFO; When not starting frequency deviation measurement, Mersure Controler is in idle condition always; When Mersure Controler is in idle condition, Mersure Controler reset asynchronous FIFO and cycle rate counter; When after startup frequency deviation measurement, Mersure Controler jumps to init state by idle condition;
2nd, when Mersure Controler is in init state, writing of unlatching asynchronous FIFO is enable; Asynchronous FIFO carries out write operation under clock to be measured, and the water level of reading of asynchronous FIFO starts to rise; When asynchronous FIFO read water level equal water level initial value time, Mersure Controler jumps to measuring state by init state;
3rd, when Mersure Controler is in measuring state, open the enable of cycle rate counter, reference clock is counted; The read-write of simultaneously opening asynchronous FIFO is enable, and asynchronous FIFO carries out write operation under clock to be measured, under reference clock, carry out read operation; If there is difference on the frequency between clock to be measured and reference clock, so the reading water level unidirectional change will occur of asynchronous FIFO; When the water level of reading of asynchronous FIFO rises to positively biased decision value or drops to negative bias decision value, or when the periodicity that cycle rate counter exports is greater than permissible accuracy, epicycle measurement completes, and Mersure Controler jumps to idle condition by measuring state, and the periodicity that lock-up cycle counter exports;
If the water level of reading of the 4th asynchronous FIFO rises to positively biased decision value, frequency deviation indicated value is " just "; Or asynchronous FIFO read water level decreasing to negative bias decision value, frequency deviation indicated value is " bearing "; Otherwise frequency deviation indicated value is " zero ";
If the significant bit number of the 5th periodicity binary value is very few, certainty of measurement can be caused to reduce, and now dicision depth calculator carries out binary shift left to dicision depth value; If periodicity effective number of bits is too much, Measuring Time can be caused long, now binary shift right is carried out to dicision depth value; So both can ensure that measurement meets required precision, can reduce unnecessary Measuring Time again;
6th, water level output module calculates water level positively biased decision value and negative bias decision value according to dicision depth value, wherein, and water level positively biased decision value=water level initial value+dicision depth value, negative bias decision value=water level initial value-dicision depth value;
7th, microprocessor reads the periodicity of FPGA, dicision depth value and frequency deviation indicated value by SPI interface, carries out frequency deviation PPM calculating:
7.1st, frequency deviation indicated value is " zero ", and the frequency deviation between clock to be measured and reference clock equals 0, unit ppm;
7.2nd, frequency deviation indicated value is " just ", and the frequency deviation between clock to be measured and reference clock equals
;
7.3rd, frequency deviation indicated value is " bearing ", and the frequency deviation between clock to be measured and reference clock equals
.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410570418.6A CN104283740A (en) | 2014-10-23 | 2014-10-23 | Method for online measurement of Ethernet frequency deviation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410570418.6A CN104283740A (en) | 2014-10-23 | 2014-10-23 | Method for online measurement of Ethernet frequency deviation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104283740A true CN104283740A (en) | 2015-01-14 |
Family
ID=52258246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410570418.6A Pending CN104283740A (en) | 2014-10-23 | 2014-10-23 | Method for online measurement of Ethernet frequency deviation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104283740A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104660461A (en) * | 2015-01-15 | 2015-05-27 | 北京奥普维尔科技有限公司 | Ethernet test instrument based on 100G communication and test method thereof |
| CN111008002A (en) * | 2019-12-06 | 2020-04-14 | 盛科网络（苏州）有限公司 | Apparatus and method for automatically calculating and updating FIFO depth |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1578197A (en) * | 2003-07-28 | 2005-02-09 | 华为技术有限公司 | Clock source frequency shift detecting method |
| US20070140398A1 (en) * | 2004-03-10 | 2007-06-21 | Sadayuki Inoue | Data receiving device and data receiving method |
| CN101447859A (en) * | 2008-12-26 | 2009-06-03 | 华为技术有限公司 | Method and device for detecting frequency deviation of clock |
| CN103312307A (en) * | 2013-05-13 | 2013-09-18 | 华为技术有限公司 | Clock frequency deviation detection method and device |
| CN103595588A (en) * | 2013-11-26 | 2014-02-19 | 北京奥普维尔科技有限公司 | Method for accurately measuring asynchronous Ethernet circuit time delay |
-
2014
- 2014-10-23 CN CN201410570418.6A patent/CN104283740A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1578197A (en) * | 2003-07-28 | 2005-02-09 | 华为技术有限公司 | Clock source frequency shift detecting method |
| US20070140398A1 (en) * | 2004-03-10 | 2007-06-21 | Sadayuki Inoue | Data receiving device and data receiving method |
| CN101447859A (en) * | 2008-12-26 | 2009-06-03 | 华为技术有限公司 | Method and device for detecting frequency deviation of clock |
| CN103312307A (en) * | 2013-05-13 | 2013-09-18 | 华为技术有限公司 | Clock frequency deviation detection method and device |
| CN103595588A (en) * | 2013-11-26 | 2014-02-19 | 北京奥普维尔科技有限公司 | Method for accurately measuring asynchronous Ethernet circuit time delay |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104660461A (en) * | 2015-01-15 | 2015-05-27 | 北京奥普维尔科技有限公司 | Ethernet test instrument based on 100G communication and test method thereof |
| CN111008002A (en) * | 2019-12-06 | 2020-04-14 | 盛科网络（苏州）有限公司 | Apparatus and method for automatically calculating and updating FIFO depth |
| CN111008002B (en) * | 2019-12-06 | 2022-04-08 | 苏州盛科通信股份有限公司 | Apparatus and method for automatically calculating and updating FIFO depth |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102035455B (en) | M/T speed measuring method for frequency converter | |
| CN102610996B (en) | Method and device for rapidly calibrating luminous power | |
| CN103558407A (en) | Real-time low speed detection device and method based on DSP quadrature encoding | |
| CN100443898C (en) | Apparatus and method for measuring rotation-axis speed by impulse | |
| CN104422500A (en) | Flow calibrating method and flow calibrating system for flow sensors of anaesthesia machines | |
| CN106645780B (en) | DSP-based rotating speed detection method and system | |
| CN105466928A (en) | Calibration treatment method of turbidity sensor | |
| CN109471154B (en) | Small-size GM count pipe wide range monitoring instrument | |
| CN104283740A (en) | Method for online measurement of Ethernet frequency deviation | |
| CN103645379B (en) | TTL signal frequency saltus step monitoring system and method | |
| CN112325967A (en) | Intelligent Internet of things water meter working state early warning method and system | |
| CN101975724B (en) | Method and system for dynamically metering tobacco shred consumption of single cigarette making machine | |
| CN101813494B (en) | Method for eliminating interference of sensor and outside thereof | |
| CN105866542A (en) | High-accuracy sliding frequency measurement method | |
| CN103558454B (en) | A kind of Puled input frequency measurement method | |
| CN104598361B (en) | A kind of method for monitoring performance and device | |
| CN202998070U (en) | Digital frequency voltage conversion circuit | |
| CN108999902A (en) | A kind of measurement method and device improving crane brake downslide accuracy of measurement | |
| CN105467396A (en) | Pulse laser range finding control system and range finding operation method thereof | |
| CN103364055B (en) | Automatic correcting method and device for flow meter impulse | |
| CN203587606U (en) | Real-time low speed detection device based on DSP quadrature encoding | |
| CN106092341B (en) | A kind of intelligent temperature sensor system | |
| CN204087498U (en) | A kind of triple coil vehicle speed measuring system | |
| CN208383910U (en) | A kind of monitoring device of the revolving speed for high rotation speed servo motor | |
| CN211777784U (en) | Unit efficiency monitoring device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150114 |
|
| WD01 | Invention patent application deemed withdrawn after publication |