CN104283199A - Inrush control with multiple switches - Google Patents
Inrush control with multiple switches Download PDFInfo
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- CN104283199A CN104283199A CN201410329021.8A CN201410329021A CN104283199A CN 104283199 A CN104283199 A CN 104283199A CN 201410329021 A CN201410329021 A CN 201410329021A CN 104283199 A CN104283199 A CN 104283199A
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- electric current
- limiting circuit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/001—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection limiting speed of change of electric quantities, e.g. soft switching on or off
- H02H9/004—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection limiting speed of change of electric quantities, e.g. soft switching on or off in connection with live-insertion of plug-in units
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/025—Disconnection after limiting, e.g. when limiting is not sufficient or for facilitating disconnection
Abstract
A novel system is offered for supplying power from an input node to a load coupled to an output node. The system may have multiple switches coupled between the input node and the output node. One or more limiting circuits may be configured for controlling the switches so as to limit outputs of the switches. For example, the limiting circuits may limit current through the respective switches. One or more timers may set a delay period for indicating a fault condition after the limiting is initiated.
Description
The U.S. Provisional Patent Application No.61/845 being entitled as " INRUSH CONTROL WITH MULTIPLE SWITCHES " that application claims was submitted on July 12nd, 2013, the priority of 491, its full content is incorporated herein by reference.
Technical field
The present invention relates in general to the circuit limiting inrush current (inrush current) and fault current in electrical system.Especially, the present invention proposes the method limiting inrush current and fault current in high power system by operating multiple paralleling switch.
Background technology
Power is provided to load from input source in controlled and shielded mode by plug-and-play circuit.A function of this controller, for when first time applies electric power or when increasing suddenly at supply voltage, limits by power supply to the inrush current of load (particularly load capacitance).Another function is (when such as load is shorted) Limited Current when load is attempted to draw multiple current.
Fig. 1 shows common plug-and-play circuit, which employs the single MOSFET100 (Q1) and the control circuit for Limited Current that connect with current sensing resistor 102 (RS1).Many such circuit are all commercially available.When current limliting, limiting amplifier 104 regulates voltage between MOSFET grid and source electrode thus Limited Current detects the voltage at resistor 102 two ends, and limits the electric current through MOSFET100 thus.The voltage VLIMIT that the voltage and voltage source 106 that represent electric current in current sensing resistor 102 produce is compared the grid of control MOSFET100 by this limiting amplifier 104, thus reduces output current when detection electric current exceedes the maximum determined by voltage VLIMIT.There is provided current source 108 to draw high grid voltage.There is provided transistor 110 to open or close this plug-and-play circuit.
During this period, all can be very large by the voltage and current of MOSFET100, cause the power loss in MOSFET100 very high.If this power loss continues, MOSFET100 can reach the temperature that can cause damaging.MOSFET voltage, electric current and the safety margins of time are expressed as the curve being called as " ESD protection area (SOA) " by MOSFET manufacturer.Usually, timer circuit 112 sets the maximum time that MOSFET operates under limiting current.The status pin that timer circuit 112 is connected to limiting amplifier 104 starts to carry out the time point of current limliting with detectability stream amplifier 104.When exhausting the time of delay set by timer circuit 112, close MOSFET100 to prevent it overheated.Thus load power-off and hot-swapping controller can indicate and there occurs fault.
High power hot plug application needs the large by-pass capacitor 126 (C to load usually
l) charge.In order to reduce the pressure of MOSFET100, load can keep closed condition until by-pass capacitor 126 is charged.Little charging current for capacitor charging keeps the power in MOSFET100 enough low thus prevents temperature from rising to dangerous degree.A kind of method reducing charging current adopts two ends to be connected to capacitor 125 between MOSFET grid and ground to limit the voltage change ratio of gate lead.Grid voltage is driven high by the electric current (being generally 10-50 μ A) from current source 108.When charging to load capacitor, MOSFET100 plays the effect of source follower.Another kind method adopts limiting amplifier 104 to set the electric current charged to load capacitor.Wherein any one method all can reduce inrush current, within the SOA making to be between the starting period MOSFET100.When charging at the end of, the output that hot-swapping controller can provide indicated horsepower passage to open (PATH_ON) thus represent can provide total current to load.The open mode of switch can be determined by the control signal of pilot switch.Such as, for switch mosfet 100, by hysteresis comparator 118, the grid-source voltage of MOSFET100 and the threshold voltage (far above MOSFET threshold voltage, such as, 4.5V) produced by voltage source 116 are compared thus complete the determination of above-mentioned on off state.
Hot plug switch itself has resistance, and this is also the source of power loss in system.In switch mosfet, this resistance is called as conducting resistance.The high power system with large load current has the great power loss that conducting resistance is thus brought.Usually, as shown in Figure 2, traditional high electric current plug-and-play circuit adopts the MOSFET200 of multiple parallel connection, 203 (Q1 and Q2) to obtain low conducting resistance, and this adopts single MOSFET inaccessiable.In the electric current that plug-and-play circuit in Fig. 2 adopts and power control circuit element 202,204,206,208,210,212,216,218,225,226 and Fig. 1, counter element is similar.
When high power levels, be difficult to find the MOSFET not only having sufficient SOA performance but also have an enough low conducting resistance to be used as hot plug switch.In high SOA performance and MOSFET can the amount of die area (die area) of loss power closely related.A lot of MOSFET produces to pay close attention to and reduces die area and reduce conducting resistance now, equally also just reduces SOA performance.The MOSFET with high SOA has high conducting resistance usually in per unit die area.On the contrary, the MOSFET with low SOA tends to have low on-resistance in per unit die area.For high power applications, in single MOSFET, reaching the SOA of demand, normally neither reality is also uneconomic.
Adopt the MOSFET of multiple parallel connection to reduce combination conducting resistance, but not necessarily can increase SOA.Because MOSFET conducting resistance has positive temperature coefficient, therefore when the raceway groove of each MOSFET strengthens comprehensively, paralleling MOS FET has shared electric current well.But, under the paralleling MOS FET when current limliting with high dram-source voltage is usually operated at saturation condition.Threshold voltage due to these MOSFET does not mate and has negative temperature coefficient, therefore can not share electric current well between them.This makes the electric current of the MOSFET carrying with lowest threshold voltage be greater than the electric current of other MOSFET carrying.Because this MOSFET generates heat, therefore along with its threshold voltage reduces further, the electric current causing it to carry is larger.Therefore, all load currents may deliver by single MOSFET.For this reason, when operation one group of paralleling MOS FET is with current limliting, them can only be look to have the SOA of single MOSFET.
And not all load all in startup and can pour in period closedown.Restriction is flowed into the inrush current of load capacitor by grid capacitor.But it does not limit and flows into the electric current that the electric current of ohmic load or inflow are connected across the Resistance Fault in load.This extra electric current adds the pressure that puts on switch mosfet and adds required SOA.
Therefore, need develop inrush current control circuit and for control multiple switch method to solve the problem.
Summary of the invention
Present disclosure proposes a kind of novel system for carrying out powering from input node to the load being connected to output node.
System according to an aspect of the present disclosure comprises: the first switch and second switch, and it is all connected between input node and output node; First limiting circuit, it is configured to for controlling the first switch thus the output of restriction the first switch; And second limiting circuit, it is configured to for controlling second switch thus the output of restriction second switch.Second limiting circuit is configured to work independently with the first limiting circuit.Such as, the first limiting circuit can limit the electric current flowing through the first switch, and the second limiting circuit can limit the electric current flowing through second switch.There is provided logical circuit to produce output signal in response to the first status signal and the second status signal.First status signal indicates the first limiting circuit limiting the output of the first switch, and the second status signal indicates the second limiting circuit limiting the output of second switch.Logical circuit produces output signal after receiving both the first status signal and the second status signal.
To the output signal of logical circuit make response timer circuit can after exhausting time of delay indication fault situation.
The first current measuring element can be arranged, for detecting the electric current in the first switch; And the second current measuring element can be set, for detecting the electric current in second switch.
First limiting circuit can make response to the electric current that the first detecting element detects, the second limiting circuit can make response to the electric current that the second detecting element detects.
This system can also comprise indicating circuit, and it is for generation of passage opening signal, and this passage opening signal instruction power channel be provided between input node and output node is opened.This indicating circuit can comprise the first testing circuit being in open mode for detecting the first switch, and is in the second testing circuit of open mode for detecting second switch.
The current-limiting circuit that this indicating circuit one of can be configured to when the first switch and second switch are all in open mode or in the first switch and second switch is in open mode and is associated with another switch produces passage opening signal when being in current-limit mode.
In the exemplary embodiment, the first switch can be connected between input node and output node, second switch can and the first switch in parallel be connected between input node and output node.First switch and second switch can open or close simultaneously.First switch and second switch all can be closed after time of delay is depleted.
According to another aspect of the present disclosure, a kind of for comprising from input node to the system of the load supplying be connected with output node: the first switch and second switch, it is all connected between input node and output node; First current-limiting circuit, it is configured to for controlling the first switch thus is the first value by the current limit flowing through the first switch; Second current-limiting circuit, it is configured to for controlling second switch thus is the second value being greater than the first value by the current limit flowing through second switch.
Second switch can be made to maintain closed condition when the first switch opens, and the signal that second switch can be open mode in response to instruction first switch is opened.The load current that second switch can be configured to around to the first switch provides low-resistance channel.
The first current measuring element can being provided for detecting the electric current in the first switch, the second current measuring element can being provided for detecting the electric current in second switch.The sensitivity of the first current measuring element can be greater than the sensitivity of the second current measuring element, and wherein current measuring element can correspond to the resistance of each resistor for detecting resistor and sensitivity.First current-limiting circuit can make response to the electric current that the first detecting element detects, the second current-limiting circuit can make response to the electric current that the second detecting element detects.
This system can have timer circuit further, this timer circuit comprises: the first timer, it is configured to the initializing first delay time in response to the first status signal, and the first status signal indicates the first current-limiting circuit to begin operating under current-limit mode with the electric current of restricted passage first switch; And second timer, it to be configured in response to the second status signal initialization second time of delay, and the second status signal indicates the second current-limiting circuit to begin operating under current-limit mode with the electric current of restricted passage second switch.First time of delay can be greater than for the second time of delay.Timer circuit can be configured to indication fault situation after exhausting the first time of delay or the second time of delay.
Indicating circuit can be configured to produce passage opening signal when second switch is open mode, and does not detect the state of the first switch.
According to another aspect of the present disclosure, it is a kind of for can the first switch and second switch be comprised from input node to the system of the load supplying be connected with output node, it is all connected between input node and output node, and wherein the first switch is configured to the more power of loss ratio second switch.Single limiting circuit can be configured to control first switch thus the output of restriction the first switch, and does not regulate and control the output of second switch.Such as, this single limiting circuit can be configured to control first switch thus close at second switch the electric current that limit flows through the first switch.
Second switch can be made when the first switch opens to maintain closed condition, and can be open mode at the first switch and the voltage at second switch two ends is opened lower than second switch during threshold level.The load current that second switch can be configured to around to the first switch provides low-resistance channel.Threshold level can be exceeded at the voltage at second switch two ends, the grid-source voltage of the first switch drops to below threshold level or the first switch close time second switch is closed.
Indicating circuit can be configured to produce passage opening signal when the first switch is open mode, and does not detect the state of second switch.
According to the following detailed description, other advantage of the present disclosure and aspect will become apparent to those skilled in the art, in the following description by illustrating the mode for realizing optimal mode of the present disclosure, illustrate and describe embodiment of the present disclosure.As described below, when not departing from disclosure spirit, the present invention can be embodied as other and different embodiments, and some details wherein can be modified in some are obvious.Therefore, accompanying drawing and illustrate in fact only as illustrating, and and unrestricted.
Accompanying drawing explanation
Can understand hereinafter to the detailed description of embodiment of the present disclosure by reference to the accompanying drawings better, the feature in accompanying drawing be not necessarily described in proportion, its object is to better correlated characteristic is shown, wherein:
Fig. 1 and 2 shows traditional hot-swapping controller.
Fig. 3 shows the first exemplary embodiment according to hot-swapping controller of the present disclosure.
Fig. 4 shows the second exemplary embodiment according to hot-swapping controller of the present disclosure.
Fig. 5 shows the 3rd exemplary embodiment according to hot-swapping controller of the present disclosure.
Embodiment
Present disclose provides the multiple independent controling circuits for controlling multiple MOSFET.This control allows multiple MOSFET, and operation or the stage of pressing start in parallel simultaneously, have time delay between each stage.Heated pressure on MOSFET is side by side dispersed on multiple MOSFET by such permission, or separates in time.
According to the present invention, the independent controling circuit of each switch can by power loss allocation to each switch.More effectively can use the SOA performance of each switch.Open when switch allows to pour in period in startup, input voltage step pours in period and open load current in the different time and adopt different MOSFET.Relative to needing the MOSFET processing all operations pattern, the MOSFET be optimized for different operation modes can be more cheap.
The instantiation of the hot-swapping controller adopted as shown in Fig. 3, Fig. 4 and Fig. 5 is described the disclosure.But the disclosure is applicable to any switching circuit for load supplying.
Fig. 3 shows the exemplary embodiment of the hot-swapping controller of two MOSFET300 and 302 with parallel operation simultaneously.Adopt respective current sensing resistor 301 and 303 and respective limiting amplifier 304 and 305 control MOSFET300 and 302 independently.Current sensing resistor 301 is connected to and represents between the positive node SENSE+1 of MOSFET300 and negative nodal point SENSE-1, and current sensing resistor 303 is connected to and represents between the positive node SENSE+2 of MOSFET302 and negative nodal point SENSE-2.Limiting amplifier 304 and 305 controls the grid of respective MOSFET300 and 302 independently of one another, during the lowest high-current value that the VLIMIT voltage that the electric current detected in respective resistor 301 and 303 is exceeded to be provided by respective voltage source 306 and 307 limits, the electric current of the output of MOSFET300 or 302 is limited.Current source 308 and 309 provides electric current to draw high the grid voltage of MOSFET300 and 302 respectively.There is provided transistor 310 and 311 to open and close respective MOSFET300 and 302.
Signal LIMITING1 and LIMITING2 produced at the state output end place of limiting amplifier 304 and 305 is respectively provided to the respective input with (AND) door 313, this AND door 313 produces and outputs signal and be supplied to timer 312, and the setting of this timer 312 is used to indicate the time of delay of overcurrent fault situation.
When current limliting, the independent gates provided by limiting amplifier 304 and 305 controls electric current and pressure accurately to divide between MOSFET300 and 302, and does not consider that between them, threshold voltage or temperature have any not mating.Therefore, for given bearing power, the MOSFET that two less and more cheap can be adopted.The impact of plate resistance (board resistance), amplifier offset and mismatch can cause one in limiting amplifier 304 and 305 by current limit at the level lower than second limiting amplifier.Because the MOSFET be associated with above-mentioned second limiting amplifier keeps standard-sized sheet, keep the dram-source voltage (VDS) of both MOSFET300 and 302 lower, therefore two MOSFET all can not suffer obvious heating in this case simultaneously.The combined impedance of switch 300 and 302 is still lower and load can continuous firing.
Only have when load current be increased to MOSFET300 and 302 all start current limliting time, VDS and loss power just start increase, need close MOSFET to provide protection.Due to the effect of AND door 313, therefore only have when LIMITING1 and LIMITING2 signal produces all (when current amplifier 304 and 305 all starts current limliting) just can start timer 312.When the time of delay that timer 312 is set up, meter was full, producing overcurrent fault signal all needs to close to indicate MOSFET300 and 302.
In addition, the plug-and-play circuit in Fig. 3 can comprise the circuit of the PATH_ON signal opened for generation of instruction power channel, thus represents and can provide total current to load.This circuit comprises: threshold voltage source 316,317; Hysteresis comparator 318,319; AND door 320,321,322; And OR door 323.When the grid-source voltage that MOSFET300 monitored by comparator 318 exceedes the threshold voltage produced by voltage source 316, and comparator 319 indicates the grid-source voltage of MOSFET302 when to exceed the threshold voltage produced by voltage source 317.Two threshold voltages all can be set as the threshold voltage far surpassing MOSFET, such as, are set to 4.5V.
An input of AND door 320 receives the output signal of comparator 318, and another input of AND door 320 receives LIMITING2 signal.AND door 321 receives the output signal of comparator 318 and 319.An input of AND door 322 receives the output signal of comparator 319, and another input of AND door 322 receives LIMITING1 signal.The output of AND door 320,321,322 is connected to or the respective input of (OR) door 323 respectively.Therefore, when two MOSFET are standard-sized sheet or a MOSFET standard-sized sheet and another MOSFET is operated under current-limit mode, this OR door 323 sends PATH_ON signal.If a closedown in MOSFET300 and 302, then PATH_ON signal will be low.Equally, Fig. 3 shows the by-pass capacitor 326 arranged in load place.
As the hot-swapping controller with paralleling MOS FET400 and 402 has been shown in Fig. 4 exemplary embodiment as shown in, can be restricted in more low level application at inrush current, paralleling MOS FET can operate stage by stage.The power of MOSFET400 loss can be less than MOSFET402.Especially, MOSFET400 works as startup MOSFET to take up load voltage when load being remained low current condition and to charge for load capacitor 426.Allow that MOSFET400 has high conducting resistance, little current limitation and low SOA like this.Therefore, MOSFET400 can be very little and cheap.As described below, MOSFET402 works as paralleling MOS FET, and it only just can open after startup MOSFET400 opens completely.
In Fig. 4, hot-swapping controller comprises current sense resistor 401,403, and corresponding limiting amplifier 404 and 405.Current sense resistor 401 is connected to measure the electric current flowing through MOSFET400 between positive node SENSE+1 and negative nodal point SENSE-1, and current sense resistor 403 is connected between positive node SENSE+2 and negative nodal point SENSE-2 to measure the electric current flowing through MOSFET402.The resistance of current sense resistor 401 can, much larger than the resistance of current sense resistor 403, make to operate MOSFET400 under the current limitation being less than MOSFET402.
Limiting amplifier 404 and 405 controls the grid of respective MOSFET400 and 402, thus the electric current detected in resistance 401 and 403 exceedes the electric current of the output of the lowest high-current value limit MOSFET400 and 402 limited by respective VLIMIT406 and 407.Current source 408 and 409 provides electric current to draw high the grid voltage of MOSFET400 and 402 respectively.Control transistor 410 and 411 with opening/closing MOSFET400 and 402 separately.
Circuit in Fig. 4 also can comprise timer 412 and 414, OR door 413, RS latch cicuit 415, voltage source 416 and 417, hysteresis comparator 418 and 419.Grid capacitor 425 can be connected between the grid of MOSFET400 and ground to obtain low charging current.Bypass load capacitor 426 can be connected to load two ends.
Signal LIMITING1 and LIMITING2 produced at the state output end place of limiting amplifier 404 and 405 is respectively provided to timer 412 and 414.The time of delay limited by the timer 412 be associated with startup MOSFET400 can be greater than the time of delay limited by the timer 414 be associated with MOSFET402.
After startup MOSFET400 opens completely, paralleling MOS FET402 is opened.Latch cicuit 415 keeps MOSFET402 to close until comparator 418 by determining that the grid-source voltage of MOSFET400 has exceeded threshold voltage thus till detecting that MOSFET400 opens.Paralleling MOS FET402 is that the load current around MOSFET400 provides low-resistance channel.
Because paralleling MOS FET402 opens when its VDS is less, therefore do not need large SOA.Correspond to less SOA, the time of delay that timer 414 provides shorter may be needed.By utilizing two MOSFET400 and 402 to apply electric power by stages, require all to reduce to the SOA of two MOSFET and conducting resistance needed for MOSFET400 can be larger.When the grid-source voltage of paralleling MOS FET402 exceedes threshold voltage, comparator 419 produces the PATH_ON signal indicating power channel to open, thus instruction low-resistance channel is opened completely and can holding load electric current.
Some application always have the load that (or even in start-up course) is in open mode, or experienced by as hot plug MOSFET brings the input step of extra pressure and output surge.In these cases, can operate the paralleling MOS FET in hot-swapping controller by stages, as shown in Figure 5, the figure shows a kind of exemplary embodiment of hot-swapping controller, this hot-swapping controller comprises: MOSFET500 and 502; The single detection resistance 501 simultaneously shared by MOSFET500 and 502; And single limiting amplifier 504, it is based on detecting grid of VLIMIT voltage control MOSFET500 thus the output current of restriction MOSFET500 that the voltage at resistor 501 two ends and voltage source 506 produce.Current source 508 and 509 provides electric current to draw high the grid voltage of MOSFET500 and 502 respectively.Control transistor 510 and 511 with opening/closing MOSFET500 and 502 separately.Timer 512 is connected to limiting amplifier 504 to detect the time that it enters current-limit mode, thus after the time of delay set by timer 512 exhausts, send overcurrent fault situation signal.
Hot-swapping controller in Fig. 5 also comprises hysteresis comparator 518, and its monitoring is relative to the grid-source voltage of the MOSFET500 of the threshold voltage produced by voltage source 516.The output of the generation PATH_ON signal of comparator 518 is connected to inverter 520, and this inverter 520 provides GATE1_OFF signal to the input of OR door 521.The output of OR door 521 produces STRESS signal, and this STRESS signal is provided to an input of OR door 522 and the grid for controlling transistor 511.Another input for OR door 522 provides the OFF/ON# signal for opening/closing MOSFET500.Hysteresis comparator 524 monitors the dram-source voltage of the MOSFET500 and 502 relative to the threshold voltage produced by voltage source 523, and provides the input outputing signal to OR door 521 to produce STRESS signal.
MOSFET500 works as pressure MOSFET to charge to load capacitance 526 and to take up load voltage.It provides load current during having the transient state of finite duration (such as, startup and input voltage change).The power loss of MOSFET500 is higher than the power loss of MOSFET502.Work under the state that MOSFET500 has high electric current and high VDS at the same time, and there is high SOA grade.But because MOSFET500 only provides load current during having the transient state of finite duration, therefore it does not need low conducting resistance.It also may need to provide long time of delay by timer 512.
MOSFET502 works as paralleling MOS FET, its when situation is stablized and is not changed for the load current around MOSFET500 provides low-resistance channel.The threshold voltage provided lower than voltage source 516 when VDS exceedes the threshold voltage that voltage source 523 provides or at the grid-source voltage of MOSFET500 (such as; under MOSFET500 is operated in current-limit mode) time, close MOSFET502 to protect it by signal STRESS.The threshold voltage limited by voltage source 523 can be set to (such as) 200mV, and the threshold voltage limited by voltage source 516 can be set to (such as) 4.5V.
MOSFET502 only just can open when STRESS signal is low, STRESS signal be the low MOSFET500 of showing open completely and VDS lower than the threshold voltage limited by voltage source 523.Therefore, MOSFET502 can have very low conducting resistance.Because MOSFET502 opens when low VDS, therefore it does not need large SOA.MSOFET502 can not work in the saturated condition, and multiple paralleling MOS FET therefore can be used to replace MOSFET502 to obtain low on-resistance.The PATH_ON signal that comparator 528 produces is obtained by the open mode of pressure MOSFET500.When MOSFET500 opens, load is allowed to obtain electric power.
Therefore, the disclosure adopts the paralleling MOS FET controlled separately to make the SOA performance improving hot-swapping controller become possibility.
The condition whether the grid-source voltage level of MOSFET is opened as the switch determined in hot-swapping controller can be adopted.Selectively, the condition whether the dram-source voltage level of MOSFET is opened as the switch determined in hot-swapping controller can be adopted.Whether the combination of opening signal may be used for producing PATH_ON signal and can open to indicate load current.
Although illustrated 2 switching channels in the exemplary embodiment in Fig. 3-Fig. 5, the configuration of hot-swapping controller can expand to multiple paralleling switch passage.
Equally, in Fig. 3-Fig. 5, illustrated that each passage has single switch mosfet.But each in these passages all can adopt multiple paralleling MOS FET switch.
In addition, although have employed N-type switch mosfet in exemplary embodiment shown in this, other device can also be utilized to realize these switches, such as, PMOS transistor, bipolar transistor, IGBT or relay.
In addition, can by the grid-source voltage in monitor force MOSFET, dram-source voltage or detection current limitation and/or the STRESS signal being generated the exemplary embodiment in Fig. 5 by monitoring paralleling MOS FET temperature.
The instruction that MOSFET opens can be obtained by its grid-source voltage of monitoring and/or its dram-source voltage.And the independent switch control circuit shown in Fig. 3, Fig. 4 and Fig. 5 may be used for the switch controlling arranged in series, instead of the switch be arranged in parallel as shown in the example embodiments.
More than illustrate and illustrate and describe many aspects of the present invention.Additionally, the disclosure only illustrate and describes preferred embodiment, but as described above, it will be appreciated that the present invention can use under other combinations various, amendment and environment, and the scope of inventive concept that can be expressed herein scope that is interior, that be equal to above-mentioned instruction is interior and/or carry out changing and revising in the scope of the skills or knowledge of association area.
Enforcement best pattern of the present invention known to embodiment described herein is also intended to explain, and be intended to make those skilled in the art can with described (or other) embodiment and together with the mode of special applications of the present invention or the various amendments needed for using to adopt the present invention.Therefore, the present invention is not limited to form disclosed in this article.
Claims (27)
1. the system for carrying out powering from input node to the load being connected to output node, comprising:
First switch and second switch, it is all connected between described input node and described output node;
First limiting circuit, it is configured to for controlling described first switch to limit the output of described first switch;
Second limiting circuit, it is configured to for controlling described second switch to limit the output of described second switch, and described second limiting circuit is configured to work independently with described first limiting circuit; And
Logical circuit, it makes response to the first status signal that described first limiting circuit of instruction is limiting the output of described first switch, and makes response to the second status signal indicating described second limiting circuit limiting the output of described second switch,
Described logical circuit is configured to produce output signal after receiving described first status signal and described both second status signals.
2. the system as claimed in claim 1, wherein said first limiting circuit restriction flows through the electric current of described first switch, and described in state the electric current that the second limiting circuit restriction flows through described second switch.
3. the system as claimed in claim 1, also comprises timer circuit, and it makes response to the output signal of described logical circuit, for indication fault situation after time of delay exhausts.
4. the system as claimed in claim 1, also comprise the first current measuring element and the second current measuring element, described first current measuring element is for detecting the electric current in described first switch, and described second current measuring element is for detecting the electric current in described second switch.
5. system as claimed in claim 4, wherein said first limiting circuit makes response to the electric current that described first detecting element detects, and described second limiting circuit makes response to the electric current that described second detecting element detects.
6. system as claimed in claim 5, also comprise indicating circuit, it is for generation of passage opening signal, and the described passage opening signal instruction power channel be provided between described input node and described output node is opened, and described indicating circuit comprises:
First testing circuit, it is in open mode for detecting described first switch; And
Second testing circuit, it is in open mode for detecting described second switch.
7. system as claimed in claim 6, produces described passage opening signal when wherein said indicating circuit one of being configured to when described first switch and described second switch are all in open mode or in described first switch and described second switch is in open mode and is limiting to inductive switch output with another limiting circuit be associated in described first switch and described second switch.
8. the system as claimed in claim 1, wherein said first switch is connected between described input node and described output node, and described second switch and described first switch in parallel be connected between described input node and described output node.
9. the system as claimed in claim 1, wherein said first switch and described second switch open or close simultaneously.
10. system as claimed in claim 3, wherein said first switch and described second switch are all closed after described time of delay is depleted.
11. 1 kinds for from input node to the system of the load supplying be connected with output node, comprising:
First switch and second switch, it is all connected between described input node and described output node;
First current-limiting circuit, it is configured to for controlling described first switch thus is the first value by the current limit flowing through described first switch; And
Second current-limiting circuit, it is configured to for controlling described second switch thus is the second value being greater than described first value by the current limit flowing through described second switch.
12. systems as claimed in claim 11, wherein make described second switch maintain closed condition when described first switch opens, and described second switch is opened in response to the signal that described first switch of instruction is open mode.
13. systems as claimed in claim 12, the load current that wherein said second switch is configured to around to described first switch provides low-resistance channel.
14. systems as claimed in claim 11, also comprise the first current measuring element for detecting the electric current in described first switch and for detecting electric current second current measuring element in described second switch, the sensitivity of wherein said first current measuring element is greater than the sensitivity of described second current measuring element.
15. systems as claimed in claim 14, wherein said first current-limiting circuit makes response to the electric current that described first current measuring element detects, described second current-limiting circuit makes response to the electric current that described second current measuring element detects.
16. systems as claimed in claim 11, also comprise timer circuit, described timer circuit comprises:
First timer, it is configured to the initializing first delay time in response to the first status signal, and described first current-limiting circuit of described first status signal instruction begins operating under current-limit mode with the electric current of the first switch described in restricted passage; And
Second timer, it to be configured in response to the second status signal initialization second time of delay, and described second current-limiting circuit of described second status signal instruction begins operating under current-limit mode with the electric current of second switch described in restricted passage.
17. systems as claimed in claim 16, wherein said timer circuit is configured to indication fault situation after exhausting described first time of delay or described second time of delay.
18. systems as claimed in claim 11, also comprise indicating circuit, it is for generation of passage opening signal, the described passage opening signal instruction power channel be provided between described input node and described output node is opened, described indicating circuit is configured to produce described passage opening signal when described second switch is open mode, and does not detect the state of described first switch.
19. 1 kinds for from input node to the system of the load supplying be connected with output node, comprising:
First switch and second switch, it is all connected between described input node and described output node, and described first switch is configured to the more power of second switch described in loss ratio; And
Limiting circuit, it is configured to control described first switch thus the output limiting described first switch, and does not regulate and control the output of described second switch.
20. systems as claimed in claim 19, the electric current of the first switch described in wherein said limiting circuit restricted passage.
21. systems as claimed in claim 20, wherein said limiting circuit is configured to control described first switch thus closes at described second switch the electric current that limit flows through described first switch.
22. systems as claimed in claim 19, wherein make when described first switch opens described second switch maintain closed condition, and be open mode and the voltage at described second switch two ends is opened lower than second switch described during threshold level at described first switch.
23. systems as claimed in claim 19, the load current that wherein said second switch is configured to around to described first switch provides low-resistance channel.
24. systems as claimed in claim 19, wherein when the voltage at described second switch two ends exceedes threshold level, described second switch is closed.
25. systems as claimed in claim 19, wherein when the grid-source voltage of described first switch drops to below threshold level, described second switch is closed.
26. systems as claimed in claim 19, wherein when described first switch cuts out, described second switch is closed.
27. systems as claimed in claim 19, also comprise indicating circuit, it is for generation of passage opening signal, the described passage opening signal instruction power channel be provided between described input node and described output node is opened, described indicating circuit is configured to produce described passage opening signal when described first switch is open mode, and does not detect the state of described second switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910132284.2A CN109830947A (en) | 2013-07-12 | 2014-07-11 | Control is poured in using Multi- Switch |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361845491P | 2013-07-12 | 2013-07-12 | |
| US61/845,491 | 2013-07-12 | ||
| US14/300,999 | 2014-06-10 | ||
| US14/300,999 US10003190B2 (en) | 2013-07-12 | 2014-06-10 | Inrush control with multiple switches |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910132284.2A Division CN109830947A (en) | 2013-07-12 | 2014-07-11 | Control is poured in using Multi- Switch |
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| CN104283199A true CN104283199A (en) | 2015-01-14 |
| CN104283199B CN104283199B (en) | 2019-03-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910132284.2A Pending CN109830947A (en) | 2013-07-12 | 2014-07-11 | Control is poured in using Multi- Switch |
| CN201410329021.8A Active CN104283199B (en) | 2013-07-12 | 2014-07-11 | Control is poured in using Multi- Switch |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910132284.2A Pending CN109830947A (en) | 2013-07-12 | 2014-07-11 | Control is poured in using Multi- Switch |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106486989A (en) * | 2015-08-31 | 2017-03-08 | 英飞凌科技股份有限公司 | It is the load supplying with surge current behavior |
| CN112350288A (en) * | 2019-08-09 | 2021-02-09 | 亚德诺半导体国际无限责任公司 | Communication terminal for hot-plug controller |
Families Citing this family (3)
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| EP3748794A1 (en) * | 2019-06-05 | 2020-12-09 | Siemens Aktiengesellschaft | Electronic fuse for a power supply |
| JP7199325B2 (en) * | 2019-09-02 | 2023-01-05 | 株式会社東芝 | switch circuit |
| CN116324666A (en) * | 2020-09-29 | 2023-06-23 | 瑞典爱立信有限公司 | Current limiter, operation method thereof and hot plug module |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN104283199B (en) | 2019-03-12 |
| CN109830947A (en) | 2019-05-31 |
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