CN104241238B - Semiconductor die package based on lead frame - Google Patents
Semiconductor die package based on lead frame Download PDFInfo
- Publication number
- CN104241238B CN104241238B CN201310230768.3A CN201310230768A CN104241238B CN 104241238 B CN104241238 B CN 104241238B CN 201310230768 A CN201310230768 A CN 201310230768A CN 104241238 B CN104241238 B CN 104241238B
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- Prior art keywords
- lead finger
- group
- lead
- semiconductor die
- die package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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- H01L23/49575—Assemblies of semiconductor devices on lead frames
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Abstract
The invention discloses a kind of semiconductor die package based on lead frame, including:Lead frame with the pipe core welding disc for supporting semiconductor element and the lead finger for surrounding tube core and pipe core welding disc.Tube core is electrically connected with being bonded silk thread with lead finger.Tube core and bonding silk thread are covered with sealant, and the end of lead finger is protruding from sealant.One group of lead finger is bent and is extended downwardly, and another group of lead finger is bent and inwardly stretched out, and under the basal surface of sealant.Sealant includes being used for the groove or groove for accommodating second group of lead finger.
Description
Technical field
The present invention relates to integrated antenna package, and relate more particularly to encapsulate the semiconductor element envelope based on lead frame
Dress.
Background technology
Semiconductor element is formed at semiconductor wafer(For example, silicon wafer)On Small Scale Integration.Such tube core
Usually cut into by chip and encapsulated using lead frame.Lead frame is support tube core and is provided for packaged tube core outer
The metal frame that portion is electrically connected, is usually copper or nickel alloy.Lead frame generally includes Ji Dao(flag)(Pipe core welding disc)And
Relevant lead finger(Lead).Semiconductor element is attached at Ji Dao, and bonding on tube core or contact pad are with bonding wire
Line is electrically connected with the lead finger of lead frame.Tube core and bonding silk thread are covered with sealant, to form semiconductor die package.Lead
Refer to protruding or at least flushed with encapsulation from encapsulating so that they can act as terminal, so as to allow semiconductor element to seal
Dress is directly electrically coupled to other devices or printed circuit board(PCB).
Semiconductor die package is just being manufactured with the increased packaging pin number of institute(pin count)(Outside terminal or
I/O numbers)Function.This is partially due to the improved silicon die manufacturing technology of institute for allowing die-size to reduce.But the number of lead finger
Amount is limited to the size of encapsulation and the spacing of lead finger.At this point, the lead finger spacing of diminution can generally increase short circuit
Possibility, especially when encapsulation is installed on circuit board.
A solution that the circuit board short circuit caused by the lead finger spacing reduced can be overcome or alleviated by is by phase
Adjacent lead finger is spaced in different planes.Installation foot in the end that adjacent legs refer to(mounting foot)With difference
Distance be spaced apart with package casing, and this is so as to increasing the spacing of installation foot welding board pads thereon.Although
Effectively, but by adjacent lead finger the complexity of manufacturing process can be increased by being spaced in different planes, and be needed accurately
Fixture(jig)Alignment and accurate lead bending.
Brief description of the drawings
Description by reference to the preferred embodiment carried out together below along with attached drawing, can best the present invention and its mesh
And advantage, in the accompanying drawings:
Fig. 1 is a kind of plan of the conductive lead frame of preferred embodiment according to the present invention;
Fig. 2 is that a kind of being formed at for preferred embodiment according to the present invention is partly assembled in the conductive lead frame of Fig. 1
The plan of encapsulation;
Fig. 3 is the part that a kind of partly assembled encapsulation from Fig. 2 of preferred embodiment according to the present invention is formed
The plan of the electric coupling encapsulation of assembling;
Fig. 4 is a kind of plan of the packaged semiconductor die package of preferred embodiment according to the present invention;
Fig. 5 is that a kind of preferred embodiment according to the present invention makes the frame parts point of the lead frame of lead finger and Fig. 1
From the plan of the semiconductor die package of the singulation produced afterwards;
Fig. 6 is that a kind of according to the present invention preferred embodiment bends the lead finger of the encapsulation of Fig. 5(Shaping)Afterwards
Semiconductor die package plan;
Fig. 7 is the side view of a part for the semiconductor die package of Fig. 6;
Fig. 8 is that the semiconductor die package of Fig. 6 passes through the sectional view of 6-6 ';And
Fig. 9 is the flow chart of the method for the encapsulation semiconductor element for showing a kind of preferred embodiment according to the present invention.
Embodiment
The description to currently preferred embodiments of the present invention is intended as below in conjunction with the detailed description that attached drawing illustrates, rather than
It is intended to indicate that the present invention can be to the unique forms implemented.It should be appreciated that identical or of equal value function can be by meaning to wrap
The different embodiments within the spirit and scope of the present invention are contained in complete.In whole attached drawings, referred to using identical numeral
Show identical element.Moreover, word " comprising ", "comprising" or its any other variant mean to cover including for nonexcludability, make
Must include module, circuit, device, component, method and step and the structure of series of elements not only includes those elements, but also wraps
Include that other are not explicitly listed or for this kind of module, circuit, step or the intrinsic element of device components.By " comprising " institute
The element or step of introducing do not exclude the presence of other identical member comprising the element or step in the absence of more restrictions
Element or step.
Some features in the accompanying drawings exaggerate for the ease of showing, and attached drawing and its element might not be by
According to appropriate ratio.Moreover, the present invention is shown as with quad-flat-pack(QFP)Type encapsulates.But those skilled in the art
It should be readily appreciated that the present invention details and present invention can apply to institute's leaded package type and their variation.
In one embodiment, the present invention provides a kind of method for encapsulating semiconductor element.This method includes carrying
For the conductive lead frame with least one pipe core welding disc, the frame parts for surrounding pipe core welding disc.In the presence of being attached at frame section
Part and be arranged in multiple lead finger between frame parts and pipe core welding disc so that each lead finger has close to tube core
The near-end of pad and the distal end being located remotely from place of pipe core welding disc.This method is further included is attached at tube core weldering by semiconductor element
Disk and make contact pad on a semiconductor die and corresponding lead finger near-end electric coupling.Also perform and sealed with encapsulating material
It is filled to the process of the near-end of education and correction for juvenile offenders core, pipe core welding disc and lead finger.Encapsulating material, which provides, has lead finger from the side that it extends
The shell of edge, and shell is interior with least one groove with it(slot)Bottom surface.This method, which further includes, makes lead finger and frame
Frame isolation of components and lead finger is set to bend to first group and second group of lead finger.The distal end of first group of lead finger is located remotely from outer
In place of shell, and the distal end of second group of lead finger is at least partially disposed in groove.
In another embodiment, the present invention provides semiconductor die package, including pipe core welding disc and welded with tube core
Disk separates and from its outwardly directed first group of lead finger.Lead finger has the near-end and and pipe core welding disc close to pipe core welding disc
The distal end separated.In the presence of being separated with pipe core welding disc and from its outwardly directed second group of lead finger.Second group of lead finger equally has
The distal end for having the near-end of close pipe core welding disc and being separated with pipe core welding disc.Semiconductor element is attached at pipe core welding disc, and
Bonding welding pad on semiconductor element(bonding pad)First and second group of lead is electrically coupled to bonding wire line options
The near-end of finger.In the presence of the encapsulating material of the near-end of covering bonding silk thread, semiconductor element and first and second group of lead finger.Envelope
Package material provides the shell from the edge that it extends with first group and second group of lead finger.Shell is interior with least with it
The bottom surface of one groove, and the distal end of wherein first group lead finger is located remotely from place of shell, and the distal end of second group of lead finger
It is at least partially disposed in groove.
Referring now to Fig. 1, a kind of plane of the conductive lead frame 100 of preferred embodiment according to the present invention is shown in figure
Figure.Lead frame 100 is a part for leadframe sheet, and lead frame 100 has pipe core welding disc 102, surrounds pipe core welding disc 102
Frame parts 104 and be attached at multiple lead finger 106 of frame parts 104.In this particular embodiment, lead frame
100 have two groups of diacritic lead finger 106, this two groups of lead finger 106 are first group of lead finger 108 and second group of lead finger
110。
Lead finger 106 is arranged between frame parts 104 and pipe core welding disc 102 so that each lead finger 106 has
Close to the near-end 112,114 of pipe core welding disc 102, and it is located remotely from the distal end 116,118 of the part of pipe core welding disc 102.Such as this
Shown in specific embodiment, each component of second group of lead finger 110 is shorter than each component of first group of lead finger 108, and
First group of lead finger 108 has the distal end 116 at frame parts 104.In contrast, second group of lead finger 110 has and frame
The distal end 118 spaced apart of frame component 104.In addition, in this embodiment, the near-end 112 of first group of lead finger 108 and second group draw
The near-end 114 that line refers to 110 is spaced apart the distance of approximately constant with pipe core welding disc.
Pillar extends from frame parts 104, so that pipe core welding disc 102 is attached at frame parts 104 and supports pipe
Core pad 102.Pillar 120 combines dam body rod(dam bars)122 support first and second group of lead finger 108,110 and make it
It is attached at frame parts 104.It is used to make pipe core welding disc 102 underlying relative to lead finger 106 moreover, each pillar 120 has
(downset)Corner(angled section)124, what this will be apparent to those skilled in the art.
With reference to Fig. 2, a kind of being formed in conductive lead frame 100 for preferred embodiment according to the present invention is shown in figure
Partly assembled encapsulation 200.Partly assembled encapsulation 200 includes usually passing through bonding agent(It is not shown)It is attached at pipe core welding disc
102 semiconductor element 202.Further, since the semiconductor element of various sizes is known, it is thus to be understood that tube core welds
The size and shape of disk 102 will depend on specific semiconductor element 202.Semiconductor element 202 have as input, output or
The contact pad 204 of power supply node(It can be circuit electrode).These contact pads 204 are arranged in semiconductor element 202
Upper surface or active surface 204 on, what this will be apparent to those skilled in the art.
Fig. 3 is a kind of part group formed by partly assembled encapsulation 200 of preferred embodiment according to the present invention
The plan of the electric coupling encapsulation 300 of dress.As shown in the figure, partly assembled electric coupling encapsulation 300 has by being bonded silk thread 302
Optionally electric coupling(Connection)To connecing for the near-end 112 of first group of lead finger 108 and the near-end of second group of lead finger 110 114
Touch pad 204.
Fig. 4 is a kind of plan of the semiconductor die package 400 encapsulated of preferred embodiment according to the present invention.
The semiconductor die package 400 of encapsulating, which is included in, is completed after thread bonded all required contact pad 204
Encapsulation 300.The semiconductor die package 400 encapsulated includes encapsulating material, which provides and be overmolded to conductive lead wire
Refer to 100 shell 402 so that shell 402 encapsulates semiconductor element 202, pipe core welding disc 102, bonding silk thread 302 and lead finger
106 near-end 112,114.
Shell 402 has first group of lead finger 108 and second group of lead finger 110 from the edge that it extends 404.In addition,
The bottom surface of shell has groove 406(Shown after having concealed details, wherein each groove 406 is adjacent to a corresponding edge 404).
Moreover, there are recess 408 in each edge 404 of shell 402, and each recess 408 and corresponding groove 406 to its, by
This provides raceway groove 410 for second group of lead finger 110.As shown by magnification region, recess is tapered, this causes
The shaping that will be described below(Bending)Period easily leads to second group of lead finger 110.
Fig. 5 is that a kind of according to the present invention preferred embodiment makes lead finger 106 be separated with the frame parts 104 of Fig. 1
The plan of the semiconductor die package 500 of the singulation produced afterwards.As shown in the figure, lead finger 106 passes through in dam body rod 122
Notch 502 of the interior position between adjacent lead finger 106 and be separated from each other.In this particular embodiment, dam body rod 122
Some parts be retained as laterally projecting portion 504 in lead finger 106, still, laterally projecting portion 504 can make lead finger
106 separated with frame parts 104 during pass through suitable finishing(Punching press)All to remove.
Fig. 6 is that a kind of according to the present invention preferred embodiment bends lead finger 106(Shaping)Semiconductor afterwards
The plan of die package 600.As shown in the figure, first group of lead finger 108 interweaves with second group of lead finger 110.More specifically, the
The component of the component of one group of lead finger 108 and second group of lead finger 110 is into being alternately arranged.In this particular example, it is laterally prominent
Go out portion 504 to remove by suitable finishing, but since adjacent legs refer to 106 warp architecture, thus if retained prominent
Go out portion, there will not be the problem of making the short circuit of adjacent laterally projecting portion 504.
Fig. 7 is the side view of a part for semiconductor die package 600.As shown in the figure, bent in lead finger 106(Shaping)
Afterwards, the distal end 116 of first group of lead finger 106 is located remotely from the part of shell 402, and the distal end 118 of second group of lead finger 108 to
Small part is located in corresponding groove 406.First group of lead finger 108 is bent so that they have the installation at its distal end 116
Foot 702, and second group of lead finger 110 is equally bent so that their same installation feet 704 having at its distal end 116.Peace
Dress foot 702,704 is arranged in the face of being located in(seating plane)In 406, and since installation foot 704 is located at the bottom of shell 402
In groove 406 in face, thus the height encapsulated can somewhat reduce.
With reference to Fig. 8, the sectional view through 6-6 ' of a part for semiconductor die package 600 is shown in figure.In the reality
To apply in example, each lead finger in first group of lead finger 108 is spaced apart and protruding from its with pipe core welding disc 102, and
Near-end 112 is close to pipe core welding disc 102, and distal end 116(Installation foot 702)It is spaced apart with pipe core welding disc 102.Second group of lead
Each lead finger referred in 110 is spaced apart and protruding from its with pipe core welding disc 102, and near-end 114 is close to tube core
Pad 102, and distal end(Installation foot 704)It is spaced apart with pipe core welding disc 102.It is more specifically, every in first group of lead finger 108
One lead finger is bent to have from shell 402 and extends out to the first area 802 in corresponding recess 408, corresponding
Upright intermediate region 804 in recess 408 and the distal end 118 in corresponding groove 406(Installation foot 704).
With reference to Fig. 9, a kind of preferred embodiment according to the present invention is shown in figure is used to illustrate encapsulation semiconductor element
Method 900 flow chart.When necessary, method 900 will be described referring to figs. 1 to 8, but those skilled in the art should be clear
Chu's this method is not restricted to the specific embodiment of Fig. 1 to 8.Method 900 includes:At block 910, there is provided conductive lead frame 100.
At block 920, perform and semiconductor element 202 is attached at pipe core welding disc 102, be consequently formed partly assembled encapsulation 200.In block
At 930, the respective near-end 112 for making the contact pad 204 of semiconductor element 202 with lead finger 106, the mistake of 114 electric couplings are performed
Journey.The electric coupling is usually performed by conventional thread bonded technique, and results in partly assembled electric coupling encapsulation
300。
At block 940, method 900 is performed comes package die 202, pipe core welding disc 102 and lead finger 106 with encapsulating material
Near-end 112,114, so as to provide shell 402.Shell 402 includes lead finger 106 from the edge that it extends 404, and
There may be individual groove in bottom surface 706(Groove 406), each individual lead finger for second group of lead finger.Alternatively, the bottom of at
There may be continuous single groove on face 706, or there may be single groove on each edge of bottom surface.
At block 950, execution makes lead finger with 104 separated process of frame parts to provide the semiconductor element of singulation
Encapsulation 500.Then, at block 960, method 900, which performs, makes lead finger bend to first group of lead finger 108 and second group of lead finger
110, to provide the semiconductor die package 600 for being typically the encapsulation of square flat flat pattern.
Advantageously, the present invention potentially reduces or alleviates the possibility for referring to the short trouble between 106 in adjacent legs, because
For for the groove 406 and recess 408 that form raceway groove 410 make adjacent lead finger 106 separate and adjacent lead finger 106 it
Between insulation barrier is provided.Groove 406 also has the advantages that another:Increase installation foot is welded in the spacing of the board pads at it, and
And groove can also potentially reduce the height or area occupied of semiconductor die package 600(footprint).
The present invention provides a kind of method for encapsulating semiconductor element, comprise the following steps:
Conductive lead frame is provided, it has:At least one pipe core welding disc, around the pipe core welding disc frame parts with
And multiple lead finger of the frame parts are attached to, the multiple lead finger is arranged in the frame parts and pipe core welding disc
Between so that the lead finger each have close to the pipe core welding disc near-end and be located remotely from the position of the pipe core welding disc
The distal end put;
Semiconductor element is attached into the pipe core welding disc;
By the contact pad on the semiconductor element and the respective near-end electric coupling of the lead finger;
The near-end of the tube core, the pipe core welding disc and the lead finger, the encapsulation are at least encapsulated with encapsulating material
Material forms shell, and shell has the lead finger from the edge that it extends, and the shell has bottom surface, contains in the bottom surface
At least one groove;
The lead finger is separated with the frame parts;And
The lead finger is bent into first and second group of lead finger, wherein the distal end of first group of lead finger is positioned at remote
From the position of the shell, and the distal end of second group of lead finger is at least partially disposed in the groove.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein the separating step is included institute
Lead finger is stated to be separated from each other.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein first and second group of lead
Finger, which is woven into, to be alternately arranged.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein second group of lead finger is every
The distal end of a lead finger is all located in the groove.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein at least one in the lead finger
A distal end is located in the groove.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein there is multiple grooves, and
And the distal end of a lead finger is placed with each groove.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein at each edge of the shell
Inside there are multiple recesses, and the upright intermediate region of each lead of second group of lead finger is recessed positioned at respective one
In portion.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein the recess each with it is corresponding
The groove alignment, thus provides raceway groove for second group of lead finger.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein in second group of lead finger
Each lead finger has extending from the shell and extends to the first area in a respective recess, positioned at institute
State the upright intermediate region in a respective recess and the distal end in the groove.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein second group of lead finger is every
A component is all shorter than each component of first group of lead finger.
One embodiment of above-mentioned semiconductor die package method according to the present invention, wherein second group of lead finger is remote
End is separated with the frame parts.
Description provides for purposes of illustration and description as described in the preferred embodiment of the present invention, but is not meant as
It is exhaustive or limits the invention to disclosed form.It will be appreciated by those skilled in the art that this hair is not being departed from
It can modify in the case of bright extensive inventive concept to embodiments described above.It is it will thus be appreciated that of the invention
Be not restricted to disclosed specific embodiment, but cover in spirit of the invention as defined in appended claims and
Within the scope of modification.
Claims (9)
1. a kind of semiconductor die package, including:
Pipe core welding disc;
Separate with the pipe core welding disc and from its outwardly directed first group of lead finger, leaned on wherein first group of lead finger has
The near-end of the nearly pipe core welding disc and the distal end separated with the tube core;
Separate with the pipe core welding disc and from its outwardly directed second group of lead finger, leaned on wherein second group of lead finger has
The near-end of the nearly pipe core welding disc and the distal end separated with the tube core;
The semiconductor element of the pipe core welding disc is attached to, wherein the bonding welding pad on the semiconductor element is to be bonded silk thread
Optionally it is electrically coupled to the near-end of first and second group of lead finger;And
Cover the encapsulation of the near-end of the bonding silk thread, the semiconductor chip and first and second group of lead finger
Material, wherein the encapsulating material forms the shell with edge, first and second group of lead finger extends from the shell,
The shell has bottom surface, and the bottom surface has at least one groove formed therein, and wherein described first group of lead finger
The distal end be located remotely from the position of the shell, and the distal end of second group of lead finger is at least partially situated at institute
State in groove.
2. semiconductor die package according to claim 1, wherein first and second group of lead finger is to interweave.
3. semiconductor die package according to claim 2, wherein the component and described second of first group of lead finger
The component of group lead finger is into being alternately arranged.
4. semiconductor die package according to claim 1, wherein each lead of second group of lead finger is located at institute
State in groove.
5. semiconductor die package according to claim 4, wherein at least one remote in second group of lead finger
End is in the groove.
6. semiconductor die package according to claim 4, wherein there are the more than one groove, and in each groove
The distal end for a lead finger being placed with second group of lead finger.
7. semiconductor die package according to claim 6, wherein each edge of the shell includes recess, and institute
The intermediate region for stating each lead of second group of lead finger is located in a respective recess.
8. semiconductor die package according to claim 7, wherein the recess each aligns with the corresponding groove, by
This provides raceway groove for second group of lead finger.
9. semiconductor die package according to claim 1, wherein each in second group of lead finger is bent
With with from the first area that the shell extends, upright intermediate region and the distal end in the groove.
Priority Applications (2)
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CN201310230768.3A CN104241238B (en) | 2013-06-09 | 2013-06-09 | Semiconductor die package based on lead frame |
US13/972,885 US8901721B1 (en) | 2013-06-09 | 2013-08-21 | Lead frame based semiconductor die package |
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CN201310230768.3A CN104241238B (en) | 2013-06-09 | 2013-06-09 | Semiconductor die package based on lead frame |
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CN104241238B true CN104241238B (en) | 2018-05-11 |
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Families Citing this family (9)
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---|---|---|---|---|
CN104795377B (en) * | 2014-01-17 | 2019-02-19 | 恩智浦美国有限公司 | Semiconductor devices with lead net |
US9978669B2 (en) | 2016-06-30 | 2018-05-22 | Nxp Usa, Inc. | Packaged semiconductor device having a lead frame and inner and outer leads and method for forming |
US10573581B2 (en) * | 2016-09-29 | 2020-02-25 | Texas Instruments Incorporated | Leadframe |
CN108735701B (en) | 2017-04-13 | 2021-12-24 | 恩智浦美国有限公司 | Lead frame with dummy leads for glitch mitigation during encapsulation |
US10325837B2 (en) | 2017-11-07 | 2019-06-18 | Infineon Technologies Ag | Molded semiconductor package with C-wing and gull-wing leads |
CN109841590A (en) | 2017-11-28 | 2019-06-04 | 恩智浦美国有限公司 | Lead frame for the IC apparatus with J lead and gull wing lead |
CN109904136A (en) * | 2017-12-07 | 2019-06-18 | 恩智浦美国有限公司 | Lead frame for the IC apparatus with J lead and gull wing lead |
US10515880B2 (en) | 2018-03-16 | 2019-12-24 | Nxp Usa, Inc | Lead frame with bendable leads |
US10840171B2 (en) * | 2018-11-28 | 2020-11-17 | Texas Instruments Incorporated | Integrated circuit package including inward bent leads |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5250841A (en) * | 1992-04-06 | 1993-10-05 | Motorola, Inc. | Semiconductor device with test-only leads |
US5266834A (en) * | 1989-03-13 | 1993-11-30 | Hitachi Ltd. | Semiconductor device and an electronic device with the semiconductor devices mounted thereon |
US5375320A (en) * | 1991-08-13 | 1994-12-27 | Micron Technology, Inc. | Method of forming "J" leads on a semiconductor device |
CN101312177A (en) * | 2007-05-22 | 2008-11-26 | 飞思卡尔半导体(中国)有限公司 | Lead frame for semiconductor device |
CN102403298A (en) * | 2010-09-07 | 2012-04-04 | 飞思卡尔半导体公司 | Lead frame for semiconductor devices |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04180668A (en) | 1990-11-15 | 1992-06-26 | Nec Kyushu Ltd | Lead frame for semiconductor device |
US6339191B1 (en) | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
US5640746A (en) | 1995-08-15 | 1997-06-24 | Motorola, Inc. | Method of hermetically encapsulating a crystal oscillator using a thermoplastic shell |
US6707135B2 (en) | 2000-11-28 | 2004-03-16 | Texas Instruments Incorporated | Semiconductor leadframe for staggered board attach |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
US20040201080A1 (en) | 2003-04-08 | 2004-10-14 | Suresh Basoor | Leadless leadframe electronic package and IR transceiver incorporating same |
KR101297645B1 (en) | 2005-06-30 | 2013-08-20 | 페어차일드 세미컨덕터 코포레이션 | Semiconductor die package and method for making the same |
JP4628996B2 (en) | 2006-06-01 | 2011-02-09 | 新光電気工業株式会社 | Lead frame, manufacturing method thereof, and semiconductor device |
JP5130566B2 (en) * | 2008-07-01 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2013
- 2013-06-09 CN CN201310230768.3A patent/CN104241238B/en active Active
- 2013-08-21 US US13/972,885 patent/US8901721B1/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5266834A (en) * | 1989-03-13 | 1993-11-30 | Hitachi Ltd. | Semiconductor device and an electronic device with the semiconductor devices mounted thereon |
US5375320A (en) * | 1991-08-13 | 1994-12-27 | Micron Technology, Inc. | Method of forming "J" leads on a semiconductor device |
US5250841A (en) * | 1992-04-06 | 1993-10-05 | Motorola, Inc. | Semiconductor device with test-only leads |
CN101312177A (en) * | 2007-05-22 | 2008-11-26 | 飞思卡尔半导体(中国)有限公司 | Lead frame for semiconductor device |
CN102403298A (en) * | 2010-09-07 | 2012-04-04 | 飞思卡尔半导体公司 | Lead frame for semiconductor devices |
Also Published As
Publication number | Publication date |
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US20140361421A1 (en) | 2014-12-11 |
CN104241238A (en) | 2014-12-24 |
US8901721B1 (en) | 2014-12-02 |
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