CN104241099A - Self-aligning dual-graph process - Google Patents
Self-aligning dual-graph process Download PDFInfo
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- CN104241099A CN104241099A CN201310232002.9A CN201310232002A CN104241099A CN 104241099 A CN104241099 A CN 104241099A CN 201310232002 A CN201310232002 A CN 201310232002A CN 104241099 A CN104241099 A CN 104241099A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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Abstract
The invention provides a self-aligning dual-graph process. Protective layers are formed on the surface of a semiconductor substrate and the surface of a second mask layer graph before the two ends of the second mask layer graph are removed and after a layer strip to be etched is formed. Due to the fact that the protective layers can shield the semiconductor substrate, the semiconductor substrate can be protected when the two ends of the second mask layer graph are removed and can be prevented from being damaged by etching, and the yield of a semiconductor wafer is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of self-aligned double patterning shape technique.
Background technology
In the manufacture process of semiconductor element, need to apply multiple independent technique, such as, photoetching, deposition, etching, cleaning etc.At present, along with the increase of the integration density of composed component in semiconductor device, the layout design rules of this class component reduces gradually and its tolerance also becomes extremely strict, and the design rule reduced requires the spacing of such as used in a lithographic process pattern to reduce could to etch the higher semiconductor element of formation integration density.Design rule and pattern-pitch reduce the resolution accuracy starting to challenge conventional lithographic equipment, in fact, the photoetching resolution precision required by design rule used now has exceeded the precision that some common process equipment can provide.Now, just need to be realized by the means of lifting process to produce the higher semiconductor element of integration density.
At present, self-aligned double patterning shape technique is usually adopted to realize above-mentioned purpose.Concrete, please refer to Fig. 1 a to Fig. 1 d, existing self-aligned double patterning shape technique comprises the following steps:
First, provide Semiconductor substrate 10, described Semiconductor substrate 10 forms layer to be etched 11; The first mask layer figure 20 that density is lower is formed, as shown in Fig. 1 a and 2a on described layer to be etched 11;
Then, the second mask layer 30 is formed in the side of the described surface of layer to be etched 11 and described first mask layer figure 20 and end face, as shown in Fig. 1 b and 2b, wherein, in the first mask layer figure 20(figure in Fig. 2 b shown in dotted line) in fact all surrounded by described second mask layer 30;
Then, etching is removed described first mask layer figure 20 and the second mask layer 30 of its end face and second mask layer 30 on described 11 surfaces layer to be etched and is formed the second mask layer figure 31, described second mask layer figure 31 i.e. the second mask layer of described first mask layer figure 20 side, known, the density of the second mask layer figure 31 is relatively high, as shown in Fig. 1 c and 2c;
Next, with the second mask layer figure 31 for mask, etch described layer to be etched 11, form the bar layer to be etched 12 that density is higher, as Fig. 1 d;
After forming the higher bar layer to be etched 12 of density, need the two ends etching the connection of removal second mask layer figure 31, because follow-up needs form filler between described bar 12 layer to be etched, stop that filler is filled between described bar layer to be etched 12 in order to avoid the two ends that the second mask layer figure 31 connects on the one hand, on the other hand in order to the filler pattern of follow-up formation meets technological requirement, therefore need the two ends of removing the second mask layer figure 31 connection along Fig. 2 c dotted line, obtain vertical view as shown in Figure 2 d.
But, to study for a long period of time discovery through present inventor, when carrying out the two ends etching the connection of removal second mask layer figure 31, because Semiconductor substrate 10 comes out, as shown in Figure 1 d, etching can damage described Semiconductor substrate 10, thus affects the yield of whole semiconductor element.
Summary of the invention
The object of the present invention is to provide a kind of self-aligned double patterning shape technique, Semiconductor substrate can be protected not to be etched damage.
To achieve these goals, the present invention proposes a kind of self-aligned double patterning shape technique, comprises step:
Semiconductor substrate is provided;
Formed layer to be etched and by the first mask layer figure of the first density distribution on the semiconductor substrate;
The second mask layer is formed at the end face of described surface layer to be etched and the first mask layer figure and side;
Etching is removed the second mask layer of described first mask layer and its end face and is formed in part second mask layer on described surface layer to be etched, obtains the second mask layer figure, and described second mask layer figure is by the second density distribution;
With described second mask layer figure for mask, etch described layer to be etched, form bar layer to be etched;
Protective layer is formed on the surface of described Semiconductor substrate and the second mask layer figure;
With described protective layer for mask, the two ends of etching removal second mask layer figure, make the second mask layer figure independent of one another;
Remove described protective layer.
Further, described first density is less than the second density.
Further, etching described layer to be etched after, before forming described protective layer, between described bar layer to be etched, form side wall.
Further, the material of described side wall is the combination of silicon nitride, silica or silicon nitride and silica.
Further, after formation protective layer, before the two ends of etching removal second mask layer figure, etching is adopted back to remove partial protection layer.
Further, described time etching is dry etching or wet etching.
Further, described protective layer is organic substance or dielectric medium.
Further, described organic material is bottom anti-reflection layer or photoresistance.
Further, described organic substance adopts spin coating mode to be formed.
Further, the material of described dielectric medium is silica, silicon nitride or carborundum.
Further, after formation protective layer, before adopting back etching, chemical mechanical milling tech is used to grind described protective layer.
Further, described dielectric medium adopts chemical vapour deposition (CVD) mode to be formed.
Further, be provided with in described Semiconductor substrate shallow trench isolation from.
Further, the material of described first mask layer is photoresistance.
Further, the material of described second mask layer is silicon nitride.
Further, described material layer to be etched is polysilicon.
Further, cineration technics or etching technics is adopted to remove described protective layer
Compared with prior art; beneficial effect of the present invention is mainly reflected in: after formation bar layer to be etched; before removing the two ends of the second mask layer figure; first form protective layer on the surface of described Semiconductor substrate and the second mask layer figure; because protective layer can shelter from described Semiconductor substrate; therefore, it is possible to play a protective role to described Semiconductor substrate when the two ends of removal second mask layer figure; thus avoid etching to cause damage to Semiconductor substrate, improve the yield of semiconductor crystal wafer.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 d is the generalized section of the structure in prior art self-aligned double patterning shape technical process;
Fig. 2 a is the vertical view forming the first mask pattern in prior art self-aligned double patterning shape technical process;
Fig. 2 b is the vertical view forming the second mask layer in prior art in self-aligned double patterning shape technical process;
Fig. 2 c is the vertical view after forming the second mask layer figure in prior art in self-aligned double patterning shape technical process;
Fig. 2 d is the vertical view after removing the second mask layer figure two ends in prior art self-aligned double patterning shape technical process;
The flow chart of self-aligned double patterning shape technique in Fig. 3 embodiment of the present invention one;
Fig. 4 a to Fig. 4 g is the generalized section of the structure in the embodiment of the present invention one in self-aligned double patterning shape technical process;
Fig. 5 a to Fig. 5 d is the generalized section of the structure in the embodiment of the present invention two in self-aligned double patterning shape technical process.
Embodiment
Below in conjunction with the drawings and specific embodiments, the self-aligned double patterning shape technique that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Embodiment one
Please refer to Fig. 3, propose a kind of self-aligned double patterning shape technique in the present embodiment, comprise step:
S100: Semiconductor substrate 100 is provided;
Wherein, the material of described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc., doped region etc. can also be formed in Semiconductor substrate 100, in addition, shallow trench isolation can also be provided with from (not shown) in Semiconductor substrate 100.
S200: form layer to be etched 110 and the first mask layer figure 200 by the first density distribution successively in described Semiconductor substrate 100, as shown in fig. 4 a;
In the present embodiment, the material of layer to be etched 110 is polysilicon, is formed by chemical vapor deposition method; The material of described first mask layer figure 110 is photoresistance, be convenient to the described first mask layer figure 110 of follow-up removal, described first mask layer figure 110 adopts the conventional mode such as spin coating, exposure, development to be formed, and described in the present embodiment, the first mask layer figure 11 is equally distributed strip array.
S300: form the second mask layer 300 at the end face of the described surface of layer to be etched 110 and the first mask layer figure 200 and side, make described second mask layer 300 surround described first mask layer figure 200, as shown in Figure 4 b;
Wherein, the material of described second mask layer 300 is such as silicon nitride, is formed, for follow-up as etching mask layer by chemical vapor deposition method.
S400: etching is removed the second mask layer of described first mask layer figure 200 and its end face and is formed in part second mask layer 300 on described 110 surfaces layer to be etched, second mask layer of remaining second mask layer and described first mask layer figure 200 side is then retained formation second mask layer figure 310, described second mask layer figure 310 is by the second density arrangement, because etching only removes described first mask layer figure 200 and part second mask layer 300 on described 110 surfaces layer to be etched, there is situation about connecting in the two ends that therefore can there is described second mask layer figure 310, as illustrated in fig. 4 c,
Wherein, the first density of described first mask layer figure 200 is less than the second density of the second mask layer figure 310, by the means of Optimization Technology, can increase the integration density of composed component in semiconductor device thus.
S500: using the second mask layer figure 310 as mask, etches described layer to be etched 110, forms bar 111 layer to be etched, as shown in figure 4d;
Wherein it is to be noted, second density of the second mask layer figure 310 determines the density of the bar layer to be etched 111 etched, because the second density is comparatively large, thus the density of the etch layer bar 111 etched is also comparatively large, can increase the integration density of composed component in semiconductor device.
S600: form protective layer 400 on the surface of described Semiconductor substrate 100 and the second mask layer figure 310, as shown in fig 4e;
Wherein, described protective layer 400 is the organic substance adopting spin coating mode to be formed, such as, be bottom anti-reflection layer (BARC) or photoresistance, be preferably BARC, meanwhile, described protective layer 400 can for the dielectric medium adopting chemical vapour deposition (CVD) to be formed, such as, be also silica, silicon nitride or carborundum; Described protective layer 400 can be filled between described bar layer to be etched 111; and shelter from described Semiconductor substrate 100 surface and be formed in shallow trench isolation in described Semiconductor substrate 100 from; in subsequent etching processes, make described Semiconductor substrate 100 and shallow trench isolation from avoiding being damaged.
In the present embodiment, can, after formation protective layer, use chemical mechanical milling tech to grind described protective layer 400, make whole semiconductor device surface more level and smooth and expose the top of remaining second mask layer 300.
After described protective layer 400 is ground, then etching technics is adopted back to remove partial protection layer 400, as shown in fig. 4f, the integral thickness of described protective layer 400 is reduced, the two ends making subsequent etching remove the second mask layer figure 310 connection are like this more prone to realize; Wherein, described time etching is dry etching or wet etching.
S700: with described protective layer 400 for mask, the two ends that etching removal second mask layer figure 310 connects are until the second mask layer figure 310 two ends are no longer connected;
Wherein, the two ends of removing described second mask layer figure 310 are the demands based on subsequent technique; After the two ends of removing described second mask layer figure 310; cineration technics or etching technics is adopted to remove described protective layer 400 again; as shown in figure 4g; thus complete whole self-aligned double patterning shape technique; realize the semiconductor element of more high density of integration; because protective layer can shelter from described Semiconductor substrate; therefore, it is possible to play a protective role to described Semiconductor substrate when removing the two ends of remaining second mask layer; thus avoid etching to cause damage to Semiconductor substrate, improve the yield of semiconductor crystal wafer.
Embodiment two
Because embodiment two is consistent with the step that embodiment one forms bar layer to be etched, do not repeat them here, concrete steps please refer to embodiment one.
Unlike, in the present embodiment, after formation bar 111 layer to be etched, before forming described protective layer 400, between described bar 111 layer to be etched, form side wall 500, as shown in Figure 5 a, the material of described side wall 500 is the combination of silicon nitride, silica or silicon nitride and silica;
Because the gap between described bar 111 layer to be etched is uneven, some can be filled full by described side wall 500, some then can not be filled full by described side wall 500, that is can expose described Semiconductor substrate 100, equally also there is the danger that subsequent etching damages described Semiconductor substrate 100; Therefore, also need to form protective layer 400 to protect described Semiconductor substrate 100;
Then, protective layer 400 is formed on the surface of described Semiconductor substrate 100, second mask layer figure 310 and described side wall 500, as shown in Figure 5 b;
Same, described protective layer 400 can adopt cmp, return the techniques such as etching after being formed, the concrete correlation step that please refer in embodiment one, does not repeat them here;
After adopting back etching, the residual part of described protective layer 400, for the protection of described Semiconductor substrate 100, please refer to Fig. 5 c;
Then, adopt cineration technics or etching technics to remove described protective layer 400, please refer to Fig. 5 d.
To sum up; in the self-aligned double patterning shape technique that the embodiment of the present invention provides; after formation bar layer to be etched; before removing the two ends of remaining second mask layer; first form protective layer on the surface of described Semiconductor substrate and remaining second mask layer; because protective layer can shelter from described Semiconductor substrate, therefore, it is possible to play a protective role to described Semiconductor substrate when removing the two ends of remaining second mask layer, thus avoid
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (17)
1. a self-aligned double patterning shape technique, comprises step:
Semiconductor substrate is provided;
Formed layer to be etched and by the first mask layer figure of the first density distribution on the semiconductor substrate;
The second mask layer is formed at the end face of described surface layer to be etched and the first mask layer figure and side;
Etching is removed the second mask layer of described first mask layer and its end face and is formed in part second mask layer on described surface layer to be etched, obtains the second mask layer figure, and described second mask layer figure is by the second density distribution;
With described second mask layer figure for mask, etch described layer to be etched, form bar layer to be etched;
Protective layer is formed on the surface of described Semiconductor substrate and the second mask layer figure;
With described protective layer for mask, the two ends of etching removal second mask layer figure, make the second mask layer figure independent of one another;
Remove described protective layer.
2. self-aligned double patterning shape technique as claimed in claim 1, it is characterized in that, described first density is less than the second density.
3. self-aligned double patterning shape technique as claimed in claim 1, is characterized in that, etching described layer to be etched after, before forming described protective layer, between described bar layer to be etched, form side wall.
4. self-aligned double patterning shape technique as claimed in claim 3, it is characterized in that, the material of described side wall is the combination of silicon nitride, silica or silicon nitride and silica.
5. self-aligned double patterning shape technique as claimed in claim 1, is characterized in that, after formation protective layer, before the two ends of etching removal second mask layer figure, adopts back etching to remove partial protection layer.
6. self-aligned double patterning shape technique as claimed in claim 5, is characterized in that, described time etching is dry etching or wet etching.
7. self-aligned double patterning shape technique as claimed in claim 5, it is characterized in that, described protective layer is organic substance or dielectric medium.
8. self-aligned double patterning shape technique as claimed in claim 7, it is characterized in that, described organic material is bottom anti-reflection layer or photoresistance.
9. self-aligned double patterning shape technique as claimed in claim 8, is characterized in that, described organic substance adopts spin coating mode to be formed.
10. self-aligned double patterning shape technique as claimed in claim 7, it is characterized in that, the material of described dielectric medium is silica, silicon nitride or carborundum.
11. self-aligned double patterning shape techniques as claimed in claim 10, is characterized in that, after formation protective layer, before adopting back etching, use chemical mechanical milling tech to grind described protective layer.
12. self-aligned double patterning shape techniques as claimed in claim 10, is characterized in that, described dielectric medium adopts chemical vapour deposition (CVD) mode to be formed.
13. self-aligned double patterning shape techniques as claimed in claim 1, is characterized in that, be provided with in described Semiconductor substrate shallow trench isolation from.
14. self-aligned double patterning shape techniques as claimed in claim 1, is characterized in that, the material of described first mask layer is photoresistance.
15. self-aligned double patterning shape techniques as claimed in claim 1, is characterized in that, the material of described second mask layer is silicon nitride.
16. self-aligned double patterning shape techniques as claimed in claim 1, it is characterized in that, described material layer to be etched is polysilicon.
17. self-aligned double patterning shape techniques as claimed in claim 1, is characterized in that, adopt cineration technics or etching technics to remove described protective layer.
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| CN201310232002.9A CN104241099B (en) | 2013-06-09 | 2013-06-09 | Self-aligned double patterning shape technique |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111986983A (en) * | 2019-05-21 | 2020-11-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112563409A (en) * | 2019-09-10 | 2021-03-26 | 浙江驰拓科技有限公司 | Magnetic memory based on spin orbit torque and preparation method thereof |
| US12106964B2 (en) | 2020-06-16 | 2024-10-01 | Winbond Electronics Corp. | Double-patterning method to improve sidewall uniformity |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100829606B1 (en) * | 2006-09-07 | 2008-05-14 | 삼성전자주식회사 | Method of forming fine pattern in a semiconductor device fabricating |
| KR100827534B1 (en) * | 2006-12-28 | 2008-05-06 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming fine pattern of the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111986983A (en) * | 2019-05-21 | 2020-11-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112563409A (en) * | 2019-09-10 | 2021-03-26 | 浙江驰拓科技有限公司 | Magnetic memory based on spin orbit torque and preparation method thereof |
| US12106964B2 (en) | 2020-06-16 | 2024-10-01 | Winbond Electronics Corp. | Double-patterning method to improve sidewall uniformity |
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