CN104240750B - Dynamic random access memory means - Google Patents
Dynamic random access memory means Download PDFInfo
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- CN104240750B CN104240750B CN201310224973.9A CN201310224973A CN104240750B CN 104240750 B CN104240750 B CN 104240750B CN 201310224973 A CN201310224973 A CN 201310224973A CN 104240750 B CN104240750 B CN 104240750B
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Abstract
Include multiple memory cell array blocks, multiple sensing amplifiers and multiple data buffer circuits the invention discloses a kind of dynamic random access memory means.Sensing amplifier is adjacent to memory cell array block respectively, and is respectively coupled to a plurality of bit line of memory cell array block.Data buffer circuit is arranged adjacent one another along the bearing of trend of data wire, and data buffer circuit couples sensing amplifier by a plurality of data lines respectively.Wherein, segment data line is mutually coupled across the surface of data buffer circuit of Part I with the data buffer circuit of Part II.
Description
Technical field
The invention relates to a kind of storage arrangement, and in particular to a kind of dynamic random access memory dress
Put.
Background technology
With the progress of electronics technology, electronic product can not obtain scarce instrument in having turned into people's life.For height can be provided
Fast and substantial amounts of data storage and treatment action, Large Copacity and efficient storage arrangement turn into one in electronic product
Important element.
In existing technical field, in dynamic random access memory means, each data base (bank) at most may be used
To provide 64 accesses of bit, and each data base is made up of 8 row sections (column segment), that is to say, that
Each row section can simultaneously provide 8 data accesses of bit.In the action being read out, there is a word in each row section
Line (word line) and row select line (column selecting line) are opened, and 8 data of bit can be by phase
Corresponding data buffer circuit, is written back in the sensing amplifier in storage arrangement.
It is worth noting that, the layout of data buffer circuit can coordinate the circuit size that the row corresponding to it is saved to carry out.
And under the framework of prior art, the access frequency range of storage arrangement is locked, when being provided with bigger access efficiency
Demand when, then can produce difficulty.
The content of the invention
It is an object of the invention to provide a kind of dynamic random access memory means, can effectively accelerate its access speed.
Dynamic random access memory means of the invention, including multiple memory cell array blocks, multiple sensings amplify
Device and multiple data buffer circuits.Sensing amplifier is adjacent to memory cell array block respectively, and is respectively coupled to deposit
The a plurality of bit line of storage unit array block.Data buffer circuit is each other along the bearing of trend arranged adjacent of data wire, and data
Buffer circuit couples sensing amplifier by a plurality of data lines respectively.Wherein, segment data line delays across the data of Part I
The data buffer circuit on the surface and Part II that rush circuit is mutually coupled.
Based on above-mentioned, multiple sensing amplifiers of present invention offer cooperation memory cell array block, and provide and sensing
The corresponding multiple data buffer circuits of amplifier.Consequently, it is possible to multiple memory cell array blocks can be actuated to simultaneously into
Line access, the effective access speed for accelerating storage arrangement, goes forward side by side to lift the efficiency of said system.
It is that features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Brief description of the drawings
Fig. 1 illustrates the schematic diagram of the storage arrangement of one embodiment of the invention.
Fig. 2A illustrates the layout type schematic diagram of one embodiment of the invention data buffer circuit.
Fig. 2 B illustrate the memory cell array block, sensing amplifier and data buffer circuit of one embodiment of the invention
Layout relationship schematic diagram.
Fig. 3 illustrates the schematic diagram of the implementation method of the data buffer circuit of the embodiment of the present invention.
Wherein, description of reference numerals is as follows：
100：Dynamic random access memory means
111、112：Memory cell array block
131、132：Data buffer circuit
121、122：Sensing amplifier
BL11~BL1N, BL21~BL2N：Bit line
MDQ11~MDQ1M, MDQ21~MDQ2M, MDQ, bMDQ：Data wire
1211、1212：Sub- sensing amplifier
300：Data buffer circuit
WCTRL：Write control signal
RCTRL：Read control signal
RWD：Data line
Specific embodiment
Fig. 1 is refer to, Fig. 1 illustrates the schematic diagram of the dynamic random access memory means 100 of one embodiment of the invention.It is dynamic
State random access memory device 100 includes multiple memory cell array blocks 111,112, multiple sensing amplifiers 121,122
And multiple data buffer circuits 131 and 132.Sensing amplifier 121,122 correspond to respectively memory cell array block 111,
112, also, sensing amplifier 121 is coupled to memory cell array block 111 by bit line BL11~BL1N, and sensing is put
Big device 122 is coupled to memory cell array block 112 by bit line BL21~BL2N.Additionally, to reduce circuit layout when institute
The race line area of needs, sensing amplifier 121 and 122 respectively with the memory cell array block 111 and 112 corresponding to it
Adjoining configuration.
Data buffer circuit 131 and 132 is mutually coupled with sensing amplifier 122 and 121 respectively, also, data buffer circuit
131 and 132 is arranged adjacent one another.Wherein, data buffer circuit 131 is coupled to sensing and amplifies by data wire MDQ11~MDQ1M
Device 122, and data buffer circuit 132 is then coupled to sensing amplifier 121 by data wire MDQ21~MDQ2M.
On circuit layout, in the case of being configured as integrated circuit with storage arrangement 100, data wire MDQ21~MDQ2M
Can cross over data buffer circuit 131 surface, and not with data buffer circuit 131 in circuit be short-circuited in the case of
Mutually to be coupled with data buffer circuit 132.
In the operation of dynamic random access memory means 100, memory cell array block 111 and 112 can lead to
Different row selection signals (column selecting signal) are crossed while being activated, so that memory cell array block
111 and 112 actions that can simultaneously carry out standby access.That is, working as memory cell array block 111 and 112 simultaneously
Row selection signal belonging to and when being activated, memory cell array block 111 can be amplified by the sensing corresponding to it
Device 121 and data buffer circuit 132 carry out the action of data access, and the same time, and memory cell array block 112 then may be used
To carry out the action of data access by the sensing amplifier 122 and data buffer circuit 131 corresponding to it.Based on sensing
Amplifier 121,122 and data buffer circuit 131 and 132 are all independent circuits, therefore, memory cell array block 111
And 112 access action will not be interfered.That is, the data access frequency range of dynamic random access memory means 100
Can effectively increase.
64 data access capabilities of bit can be simultaneously provided so that each memory cell array block 111 and 112 is each
It is example, in embodiments of the present invention, by starting two memory cell array blocks 111 and 112 simultaneously to enter line access, just
Can make the dynamic random access memory means 100 can be while providing 128 data access capabilities of bit.Certainly, if simultaneously
Start more memory cell array blocks to enter line access, then can more lift the data access frequency range of storage arrangement 100.
Each memory cell array block 111 and 112 is operable in data read mode or data write mode.To store
Cell array block 111 is example, when memory cell array block 111 operates in data write mode, memory cell array
Data buffer circuit 132 corresponding to block 111 receives write-in data, and single by the 121 pairs of storages of corresponding sensing amplifier
Element array block 111 carries out data write activity.Wherein, data buffer circuit 132 will be write by data wire MDQ21~MDQ2M
Enter data and be sent to sensing amplifier 121, and data are carried out with to memory cell array block 111 by sensing amplifier 121
Write activity.
Relative, when memory cell array block 111 operates in data read mode, memory cell array block 111
Corresponding data buffer circuit 132 is produced according to the sensing result of corresponding sensing amplifier 121 and reads data.Wherein, sense
Amplifier 121 is sensed according to data read-out in memory cell array block 111, and sensing result is passed through into data
Line MDQ21~MDQ2M is sent in data buffer circuit 132, and reading data are produced by data buffer circuit 132.
Subsidiary one carries, in the present embodiment, while the memory cell array block 111 and 112 being activated can be respectively
Carry out the action of digital independent or data write-in.Carefully illustrate, memory cell array block 111 and 112 can carry out simultaneously
The action of data write-in, or the action that can also simultaneously carry out data read-out.
It is noted that in the layout of circuit, by the bit that data buffer circuit 131 and 132 is processed
Number is identical, therefore, the width of the circuit of data buffer circuit 131 and 132 is identical.It is integrated in storage arrangement 100
When circuit, data buffer circuit 131 and 132 can be with arranged adjacent one another being laid out.
Fig. 2A is below refer to, Fig. 2A illustrates the layout type schematic diagram of the data buffer circuit of one embodiment of the invention.
In fig. 2, sequentially the prolonging along data wire MDQ11~MDQ1M and MDQ21~MDQ2M of data buffer circuit 131 and 132
Stretch direction and carry out arranged adjacent.Wherein, in fig. 2, data wire MDQ11~MDQ1M is mutually coupled with data buffer circuit 131, and
MDQ21~MDQ2M is then mutually coupled across the surface of data buffer circuit 131 with data buffer circuit 132.
Hereinafter memory cell array block, sensing amplifier that Fig. 2 B, Fig. 2 B illustrate one embodiment of the invention are refer to again
And the layout relationship schematic diagram of data buffer circuit.Wherein, sensing amplifier include two sub- sensing amplifiers 1211 and
1212, and sub- sensing amplifier 1211 and 1212 is laid out in two sides of memory cell array block 111 respectively.Specifically
It is bright, part bit line and the phase of memory cell array block 111 that sub- sensing amplifier 1211 passes through memory cell array block 111
Coupling, and sub- sensing amplifier 1212 then can by the bit line that is not coupled mutually with sub- sensing amplifier 1211 come with memory cell
Array block 111 is mutually coupled.Wherein, the quantity of the bit line that sub- sensing amplifier 1211 and 1212 is respectively coupled to can be
Identical.Subsidiary one is carried, and above-mentioned bit line can be made up of multiple paired bit line pairs, each bit line pair may be used to
Transmit complementary differential wave.
Data buffer circuit 131 is then coupled to sub- sensing by data wire MDQ11, MDQ13, MDQ15 and MDQ17 and put
Big device 1211, and sub- sensing amplifier 1212 is coupled to by data wire MDQ12, MDQ14, MDQ16 and MDQ18.Each number
According to the data wire pair that line MDQ11~MDQ18 can include being made up of two data lines, wherein, each data wire is complementary to transmission
Data-signal.
In the present embodiment, sub- sensing amplifier 1211 may be used to the odd number position for the treatment of memory cell array block 111
The data of unit, and sub- sensing amplifier 1212 then may be used to process the data of the even number bit of memory cell array block 111.
In the layout of integrated circuit, data wire MDQ12, MDQ14, MDQ16 and MDQ18 can cross over memory cell array block
111 and the top of sub- sensing amplifier 1211, and not with memory cell array block 111 and sub- sensing amplifier 1211
In circuit element short circuit in the case of, be connected to data buffer circuit 131.
Fig. 3 is below refer to, Fig. 3 illustrates the schematic diagram of the implementation method of the data buffer circuit of the embodiment of the present invention.Number
Include write buffer 310 and sense buffer 320 according to buffer circuit 300.Write buffer 310 is coupled by data wire MDQ
And the data wire pair and data line RWD that bMDQ is constituted.Write buffer 310 simultaneously receives write control signal
WCTRL.Data on data line RWD are sent to data wire by write buffer 310 according to write control signal WCTRL
MDQ and bMDQ.Wherein, the data on data wire MDQ and bMDQ are complementary.
Sense buffer 320 couples the data wire pair being made up of data wire MDQ and bMDQ, and receives reading control letter
Number RCTRL.The data of data wire MDQ and bMDQ are sent to data by sense buffer 320 according to control signal RCTRL is read
Transmission line RWD.
In terms of the action details of data buffer circuit 300, the corresponding memory cell array of data buffer circuit 300
Block is actuated to during into line access, and the wordline (word line) of memory cell array block is opened, and in digital independent mould
Under formula, by being enabled for row selection signal (column selecting signal), the data in memory cell array block
Be sent out and by the sensing amplifier corresponding to data buffer circuit 300 to be amplified, go forward side by side so that data wire MDQ and
Voltage quasi position on bMDQ is opened and produces potential difference.Sense buffer 320 then carrys out foundation according to reading control signal RCTRL
Data are read in the generation that changes state to of the voltage quasi position on data wire MDQ and bMDQ, and are sent to data by data are read
Transmission line RWD.
Under data write mode, by being enabled for row selection signal, write buffer 310 is according to write control signal
Be sent to data on data line RWD in the way of differential wave on data wire MDQ and bMDQ by WCTRL, and is led to
Corresponding sensing amplifier is crossed to write to the memory cell battle array being actuated into line access the data on data line RWD
In row block.
In sum, the present invention passes through multiple sensing amplifiers corresponding with multiple memory cell array blocks respectively, then
Coordinate multiple data buffer circuits corresponding with multiple sensing amplifiers respectively multiple while being actuated into line access to make
Memory cell array block can carry out access action simultaneously in the case of non-interference, effectively lift storage arrangement
Reading and writing bandwidth, goes forward side by side to lift the efficiency of said system.
Claims (7)
1. a kind of dynamic random access memory means, including：
Multiple memory cell array blocks；
Multiple sensing amplifiers, are adjacent to, and be respectively coupled to the plurality of storage with the plurality of memory cell array block respectively
The a plurality of bit line of cell array block；And
Multiple data buffer circuits, the plurality of data buffer circuit couples the plurality of sensing and amplifies by a plurality of data lines respectively
Device, the plurality of data buffer circuit is each other along the bearing of trend arranged adjacent of a plurality of data lines；
Wherein, part a plurality of data lines across Part I the plurality of data buffer circuit surface with Part II
The plurality of data buffer circuit is mutually coupled.
2. dynamic random access memory means as claimed in claim 1, wherein the plurality of memory cell array block is simultaneously
It is actuated to carry out access action.
3. dynamic random access memory means as claimed in claim 1, wherein when each memory cell array block is in
During one data read mode, respectively the corresponding respectively data buffer circuit of the memory cell array block is according to corresponding respectively sensing
The sensing result of amplifier produces one to read data.
4. dynamic random access memory means as claimed in claim 1, wherein when each memory cell array block is in
During one data write mode, respectively the corresponding respectively data buffer circuit of the memory cell array block receives one and writes data, and
Data write activity is carried out to the respectively memory cell array block by corresponding respectively sensing amplifier.
5. dynamic random access memory means as claimed in claim 1, the wherein a plurality of data lines include multiple data wires
Right, respectively the data wire is to transmitting complementary data-signal.
6. dynamic random access memory means as claimed in claim 5, wherein respectively the data buffer circuit includes：
One write buffer, couples the respectively data wire pair and a data line, and receive a write control signal, the write-in
Data on the data line are sent to the respectively data wire pair by buffer according to the write control signal；And
One sense buffer, couples the respectively data wire pair and the data line, and receive a reading control signal, the reading
The respectively data wire is sent to the data line by buffer according to the reading control signal to upper data.
7. dynamic random access memory means as claimed in claim 1, wherein respectively the sensing amplifier includes：
One first sub- sensing amplifier；And
One second sub- sensing amplifier,
Wherein, first and second sub- sensing amplifier configuration is in two sides of the corresponding memory cell array block, and is somebody's turn to do
First sub- sensing amplifier couples a plurality of bit line of the part of the corresponding memory cell array block, the second son sensing
Amplifier couples a plurality of bit line that the corresponding memory cell array block is not coupled with the first sub- sensing amplifier.
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| CN201310224973.9A CN104240750B (en) | 2013-06-07 | 2013-06-07 | Dynamic random access memory means |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310224973.9A CN104240750B (en) | 2013-06-07 | 2013-06-07 | Dynamic random access memory means |
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| CN104240750A CN104240750A (en) | 2014-12-24 |
| CN104240750B true CN104240750B (en) | 2017-06-23 |
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| US10262701B2 (en) | 2017-06-07 | 2019-04-16 | Micron Technology, Inc. | Data transfer between subarrays in memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1505048A (en) * | 2002-11-29 | 2004-06-16 | ��ʽ���綫֥ | Precharge time modified semiconductor storage apparatus |
| CN101388242A (en) * | 2007-09-13 | 2009-03-18 | 恩益禧电子股份有限公司 | Semiconductor storage device containing antinoise generator and control method thereof |
| US7764565B2 (en) * | 2008-03-14 | 2010-07-27 | Promos Technologies Pte.Ltd. | Multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banks |
-
2013
- 2013-06-07 CN CN201310224973.9A patent/CN104240750B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1505048A (en) * | 2002-11-29 | 2004-06-16 | ��ʽ���綫֥ | Precharge time modified semiconductor storage apparatus |
| CN101388242A (en) * | 2007-09-13 | 2009-03-18 | 恩益禧电子股份有限公司 | Semiconductor storage device containing antinoise generator and control method thereof |
| US7764565B2 (en) * | 2008-03-14 | 2010-07-27 | Promos Technologies Pte.Ltd. | Multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banks |
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