CN104240750B - Dynamic Random Access Memory Device - Google Patents

Abstract

The present invention discloses a dynamic random access memory device including a plurality of memory cell array blocks, a plurality of sense amplifiers and a plurality of data buffer circuits. The sense amplifiers are respectively arranged adjacent to the memory cell array blocks and are respectively coupled to a plurality of bit lines of the memory cell array blocks. The data buffer circuits are arranged adjacent to each other along the extension direction of the data lines, and the data buffer circuits are respectively coupled to the sense amplifiers through a plurality of data lines. Part of the data lines cross the surface of the first part of the data buffer circuit and are coupled to the second part of the data buffer circuit.

Description

Dynamic Random Access Memory Device

technical field

The present invention relates to a memory device, and more particularly to a dynamic random access memory device.

Background technique

With the advancement of electronic technology, electronic products have become an indispensable tool in people's life. In order to provide high-speed and massive data storage and processing operations, large-capacity and high-efficiency memory devices have become an important component in electronic products.

In the existing technical field, in the DRAM device, each memory bank (bank) can provide at most 64-bit access, and each memory bank is composed of 8 row segments (column segment) , That is to say, each row section can provide 8 bits of data access at the same time. When reading, a word line and a column selecting line are turned on in each row, and 8 bits of data are written through the corresponding data buffer circuit. back into the sense amplifier in the memory device.

It should be noted that the layout of the data buffer circuit will be carried out in accordance with the circuit size of the corresponding row section. However, under the framework of the prior art, the access bandwidth of the memory device is limited, and when there is a need to provide greater access efficiency, difficulties will arise.

Contents of the invention

The object of the present invention is to provide a dynamic random access memory device, which can effectively speed up its access speed.

The DRAM device of the present invention includes a plurality of memory cell array blocks, a plurality of sense amplifiers and a plurality of data buffer circuits. The sense amplifiers are respectively arranged adjacent to the memory cell array block, and are respectively coupled to a plurality of bit lines of the memory cell array block. The data buffer circuits are arranged adjacent to each other along the extending direction of the data lines, and the data buffer circuits are respectively coupled to the sense amplifiers through a plurality of data lines. Wherein, part of the data lines crosses the surface of the first part of the data buffer circuit and is coupled with the second part of the data buffer circuit.

Based on the above, the present invention provides a plurality of sense amplifiers matching the memory cell array blocks, and provides a plurality of data buffer circuits corresponding to the sense amplifiers. In this way, a plurality of memory cell array blocks can be activated simultaneously for access, effectively speeding up the access speed of the memory device, and further improving the performance of the associated system.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention.

FIG. 2A is a schematic diagram of a layout of a data buffer circuit according to an embodiment of the present invention.

FIG. 2B is a schematic diagram illustrating the layout relationship among the memory cell array block, the sense amplifier and the data buffer circuit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of an implementation of a data buffer circuit according to an embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100: dynamic random access memory device

111, 112: memory cell array block

131, 132: data buffer circuit

121, 122: Sense amplifier

BL11～BL1N, BL21～BL2N: bit lines

MDQ11～MDQ1M, MDQ21～MDQ2M, MDQ, bMDQ: data line

1211, 1212: sub-sense amplifiers

300: data buffer circuit

WCTRL: write control signal

RCTRL: read control signal

RWD: data transmission line

detailed description

Please refer to FIG. 1 , which is a schematic diagram of a DRAM device 100 according to an embodiment of the present invention. The DRAM device 100 includes a plurality of memory cell array blocks 111 , 112 , a plurality of sense amplifiers 121 , 122 and a plurality of data buffer circuits 131 and 132 . The sense amplifiers 121 and 122 correspond to the memory cell array blocks 111 and 112 respectively, and the sense amplifier 121 is coupled to the memory cell array block 111 through the bit lines BL11-BL1N, and the sense amplifier 122 is coupled to the memory cell array block 111 through the bit line BL21. ˜BL2N is coupled to the memory cell array block 112 . In addition, in order to reduce the running area required for circuit layout, the sense amplifiers 121 and 122 are arranged adjacent to the corresponding memory cell array blocks 111 and 112 respectively.

The data buffer circuits 131 and 132 are coupled to the sense amplifiers 122 and 121 respectively, and the data buffer circuits 131 and 132 are arranged adjacent to each other. Wherein, the data buffer circuit 131 is coupled to the sense amplifier 122 through the data lines MDQ11˜MDQ1M, and the data buffer circuit 132 is coupled to the sense amplifier 121 through the data lines MDQ21˜MDQ2M.

In terms of circuit layout, when the memory device 100 is constructed as an integrated circuit, the data lines MDQ21˜MDQ2M can cross the surface of the data buffer circuit 131 and communicate with the data buffer without short circuiting with the lines in the data buffer circuit 131. Circuitry 132 is coupled.

In the operation of the DRAM device 100, the memory cell array blocks 111 and 112 can be activated simultaneously through different row selection signals (column selecting signal), so that the memory cell array blocks 111 and 112 can be simultaneously activated. The action of backup and retrieval. That is to say, when the memory cell array blocks 111 and 112 are simultaneously activated according to the corresponding row selection signal, the memory cell array block 111 can perform data storage through its corresponding sense amplifier 121 and data buffer circuit 132 . At the same time, the memory cell array block 112 can perform data access through its corresponding sense amplifier 122 and data buffer circuit 131 . Since the sense amplifiers 121 and 122 and the data buffer circuits 131 and 132 are independent circuits, the access operations of the memory cell array blocks 111 and 112 will not interfere with each other. That is to say, the data access bandwidth of the DRAM device 100 can be effectively increased.

Taking each of the memory cell array blocks 111 and 112 as an example, which can provide 64 bits of data access capability at the same time, in the embodiment of the present invention, two memory cell array blocks 111 and 112 are activated simultaneously for storage fetching, the DRAM device 100 can simultaneously provide 128-bit data access capability. Of course, if more memory cell array blocks are enabled for access at the same time, the data access bandwidth of the memory device 100 can be further improved.

Each memory cell array block 111 and 112 can operate in a data read mode or a data write mode. Taking the memory cell array block 111 as an example, when the memory cell array block 111 operates in the data writing mode, the data buffer circuit 132 corresponding to the memory cell array block 111 receives the write data, and passes the corresponding sense amplifier 121 performs a data writing operation on the memory cell array block 111 . Wherein, the data buffer circuit 132 transmits the writing data to the sense amplifier 121 through the data lines MDQ21˜MDQ2M, and performs data writing operation on the memory cell array block 111 through the sense amplifier 121 .

In contrast, when the memory cell array block 111 operates in the data read mode, the data buffer circuit 132 corresponding to the memory cell array block 111 generates read data according to the sensing result of the corresponding sense amplifier 121 . Wherein, the sense amplifier 121 performs sensing according to the data read out from the memory cell array block 111, and transmits the sensing result to the data buffer circuit 132 through the data lines MDQ21˜MDQ2M, and transmits the sensing result through the data buffer circuit 132. Generate read data.

Incidentally, in this embodiment, the simultaneously activated memory cell array blocks 111 and 112 can respectively perform data reading or data writing operations. To explain in detail, the memory cell array blocks 111 and 112 can simultaneously perform data writing operations, or can also simultaneously perform data reading operations.

It should be noted that in terms of circuit layout, since the data buffer circuits 131 and 132 can process the same number of bits, the circuit widths of the data buffer circuits 131 and 132 are the same. When the memory device 100 is integrated, the data buffer circuits 131 and 132 can be arranged adjacent to each other for layout.

Please refer to FIG. 2A below. FIG. 2A is a schematic diagram of a layout of a data buffer circuit according to an embodiment of the present invention. In FIG. 2A , the data buffer circuits 131 and 132 are arranged adjacently along the extending direction of the data lines MDQ11 ˜ MDQ1M and MDQ21 ˜ MDQ2M in sequence. Wherein, in FIG. 2A , data lines MDQ11 ˜ MDQ1M are coupled to the data buffer circuit 131 , while MDQ21 ˜ MDQ2M are coupled to the data buffer circuit 132 across the surface of the data buffer circuit 131 .

Please refer to FIG. 2B again below. FIG. 2B is a schematic diagram showing the layout relationship among the memory cell array block, the sense amplifier and the data buffer circuit according to an embodiment of the present invention. Wherein, the sense amplifier includes two sub-sense amplifiers 1211 and 1212 , and the sub-sense amplifiers 1211 and 1212 are arranged on two sides of the memory cell array block 111 respectively. Specifically, the sub-sense amplifier 1211 is coupled to the memory cell array block 111 through a part of the bit lines of the memory cell array block 111, and the sub-sense amplifier 1212 is not coupled to the sub-sense amplifier 1211. The connected bit lines are coupled to the memory cell array block 111. Wherein, the number of bit lines to which the sub-sense amplifiers 1211 and 1212 are respectively coupled may be the same. Incidentally, the above-mentioned bit lines may be composed of multiple bit line pairs, and each bit line pair may be used to transmit complementary differential signals.

The data buffer circuit 131 is coupled to the sub-sense amplifier 1211 through the data lines MDQ11 , MDQ13 , MDQ15 and MDQ17 , and is coupled to the sub-sense amplifier 1212 through the data lines MDQ12 , MDQ14 , MDQ16 and MDQ18 . Each data line MDQ11˜MDQ18 may include a data line pair composed of two data lines, wherein each data line pair transmits a complementary data signal.

In this embodiment, the sub-sense amplifier 1211 can be used to process the data of the odd-numbered bits of the memory cell array block 111, and the sub-sense amplifier 1212 can be used to process the data of the even-numbered bits of the memory cell array block 111. data. In the layout of the integrated circuit, the data lines MDQ12, MDQ14, MDQ16, and MDQ18 may span over the memory cell array block 111 and the sub-sense amplifier 1211, and are not connected to the memory cell array block 111 and the sub-sense amplifier 1211. In case of a short circuit of the circuit elements, it is connected to the data buffer circuit 131.

Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of an implementation of a data buffer circuit according to an embodiment of the present invention. The data buffer circuit 300 includes a write buffer 310 and a read buffer 320 . The write buffer 310 is coupled to the data line pair formed by the data lines MDQ and bMDQ and the data transmission line RWD. The write buffer 310 receives a write control signal WCTRL. The write buffer 310 transmits the data on the data transmission line RWD to the data lines MDQ and bMDQ according to the write control signal WCTRL. Wherein, the data on the data lines MDQ and bMDQ are complementary.

The read buffer 320 is coupled to the data line pair formed by the data lines MDQ and bMDQ, and receives the read control signal RCTRL. The read buffer 320 transmits the data of the data lines MDQ and bMDQ to the data transmission line RWD according to the read control signal RCTRL.

Regarding the details of the operation of the data buffer circuit 300, when the memory cell array block corresponding to the data buffer circuit 300 is activated for access, the word line (word line) of the memory cell array block is opened, and when the data is read mode, by enabling the row selection signal (column selecting signal), the data in the memory cell array block is transmitted and amplified by the sense amplifier corresponding to the data buffer circuit 300, and then the data line MDQ And the voltage level on bMDQ is pulled apart to generate a potential difference. The read buffer 320 generates read data according to the change state of the voltage levels on the data lines MDQ and bMDQ according to the read control signal RCTRL, and transmits the read data to the data transmission line RWD.

In the data writing mode, by enabling the row selection signal, the write buffer 310 transmits the data on the data transmission line RWD to the data lines MDQ and bMDQ in the form of differential signals according to the write control signal WCTRL, And the data on the data transmission line RWD is written into the block of the memory cell array activated for access through the corresponding sense amplifier.

To sum up, the present invention uses a plurality of sense amplifiers respectively corresponding to a plurality of memory cell array blocks, and cooperates with a plurality of data buffer circuits respectively corresponding to a plurality of sense amplifiers, so that a plurality of memory cell array blocks are simultaneously activated to The memory cell array blocks to be accessed can simultaneously perform access operations without interfering with each other, effectively improving the read/write bandwidth of the memory device, and further improving the performance of the associated system.

Claims (7)

1. a kind of dynamic random access memory means, including：

Multiple memory cell array blocks；

Multiple sensing amplifiers, are adjacent to, and be respectively coupled to the plurality of storage with the plurality of memory cell array block respectively The a plurality of bit line of cell array block；And

Multiple data buffer circuits, the plurality of data buffer circuit couples the plurality of sensing and amplifies by a plurality of data lines respectively Device, the plurality of data buffer circuit is each other along the bearing of trend arranged adjacent of a plurality of data lines；

Wherein, part a plurality of data lines across Part I the plurality of data buffer circuit surface with Part II The plurality of data buffer circuit is mutually coupled.

2. dynamic random access memory means as claimed in claim 1, wherein the plurality of memory cell array block is simultaneously It is actuated to carry out access action.

3. dynamic random access memory means as claimed in claim 1, wherein when each memory cell array block is in During one data read mode, respectively the corresponding respectively data buffer circuit of the memory cell array block is according to corresponding respectively sensing The sensing result of amplifier produces one to read data.

4. dynamic random access memory means as claimed in claim 1, wherein when each memory cell array block is in During one data write mode, respectively the corresponding respectively data buffer circuit of the memory cell array block receives one and writes data, and Data write activity is carried out to the respectively memory cell array block by corresponding respectively sensing amplifier.

5. dynamic random access memory means as claimed in claim 1, the wherein a plurality of data lines include multiple data wires Right, respectively the data wire is to transmitting complementary data-signal.

6. dynamic random access memory means as claimed in claim 5, wherein respectively the data buffer circuit includes：

One write buffer, couples the respectively data wire pair and a data line, and receive a write control signal, the write-in Data on the data line are sent to the respectively data wire pair by buffer according to the write control signal；And

One sense buffer, couples the respectively data wire pair and the data line, and receive a reading control signal, the reading The respectively data wire is sent to the data line by buffer according to the reading control signal to upper data.

7. dynamic random access memory means as claimed in claim 1, wherein respectively the sensing amplifier includes：

One first sub- sensing amplifier；And

One second sub- sensing amplifier,

Wherein, first and second sub- sensing amplifier configuration is in two sides of the corresponding memory cell array block, and is somebody's turn to do First sub- sensing amplifier couples a plurality of bit line of the part of the corresponding memory cell array block, the second son sensing Amplifier couples a plurality of bit line that the corresponding memory cell array block is not coupled with the first sub- sensing amplifier.