CN104219527A - Coding method and coding system for embedded device-oriented 4K ultra-high-definition video - Google Patents
Coding method and coding system for embedded device-oriented 4K ultra-high-definition video Download PDFInfo
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Abstract
The embodiment of the invention provides a coding method and a coding system for an embedded device-oriented 4K ultra-high-definition video. The method comprises the following steps that: an embedded device segments the 4K ultra-high-definition video into a plurality of paths of 2K high-definition videos; the embedded device codes each path of the 2K high-definition videos; the embedded device carries out code stream-level synthesis on each of the coded 2K high-definition videos. The coding method and the coding system provided by the embodiment of the invention are used for lowering cost and CPU power consumption, and have the characteristics of real-time performance, stability and the like.
Description
Technical field
The present invention relates to video technique field, particularly relate to the coded system of a kind of coding method of 4K ultra high-definition video of Embedded equipment and a kind of 4K ultra high-definition video of Embedded equipment.
Background technology
Along with user is more and more higher for the requirement of video definition, the inexorable trend of resolution to be the popularization of the ultra high-definition video of 4K be future video technical development.But in order to promote 4K ultra high-definition video, just need the encoded question solving 4K ultra high-definition video.Method at present for 4K ultra high-definition video of encoding mainly contains two kinds, one method uses high performance x86 computer, the cpu performance utilizing it powerful carries out the coding of 4K ultra high-definition video, but there is real-time and less stable, and the problem that power consumption is very high.Another kind method uses special 4K ultra high-definition video coding chip, but due to the chip that can process 4K ultra high-definition Video coding at present few, therefore required cost is high.
Because the coding of current 4K ultra high-definition video completes primarily of high-performance CPU or high-performance special chip, the coding techniques with traditional in technical pattern is as broad as long, and hardware performance that just heap is high, increases data bandwidth, too increase required cost simultaneously.A performance bottleneck difficult problem at present for 4K ultra high-definition Video coding does not still well solve, therefore the popularization of 4K ultra high-definition video is always limited.Therefore, the technical problem needing those skilled in the art urgently to solve at present is exactly: the coding strategy proposing a kind of 4K ultra high-definition video of Embedded equipment, for reducing cost and CPU power consumption, and has the feature such as real-time, stability.
Summary of the invention
Embodiment of the present invention technical problem to be solved is to provide a kind of coding method of 4K ultra high-definition video of Embedded equipment, for reducing cost and CPU power consumption, and has the feature such as real-time, stability.
Accordingly, the embodiment of the present invention additionally provides a kind of coded system of 4K ultra high-definition video of Embedded equipment, in order to ensure the implementation and application of said method.
In order to solve the problem, the embodiment of the invention discloses a kind of coding method of 4K ultra high-definition video of Embedded equipment, comprising:
Described 4K ultra high-definition Video segmentation is multichannel 2K HD video by described embedded device;
Described embedded device is encoded to described each road 2K HD video respectively;
Described embedded device carries out the synthesis of code stream level to described encoded each road 2K HD video.
Preferably, the step that described 4K ultra high-definition Video segmentation is multichannel 2K HD video comprises by described embedded device:
Described embedded device calculates the described resolution of 4K ultra high-definition video and the quotient of default value;
The 2K HD video of described embedded device to be multipath resolution by described 4K ultra high-definition Video segmentation be described quotient.
Preferably, described embedded device comprises the step that described each road 2K HD video is encoded respectively:
Described embedded device adopts pre-arranged code agreement, encodes respectively to described 2K HD video;
Described embedded device adds timestamp respectively for each road 2K HD video;
Each road 2K HD video corresponding for described timestamp is merged into video code flow by described embedded device.
Preferably, described encoded each road 2K HD video includes the macro block data of some 2K respectively, and the cataloged procedure of described pre-arranged code agreement comprises entropy code; Described embedded device comprises the step that described encoded each road 2K HD video carries out the synthesis of code stream level:
Described embedded device decodes the macro block data of each road 2K from the 2K HD video of described each road;
The macro block data of described each road 2K arranges by described embedded device according to the order of sequence, again forms the macro block data of 1 road 4K;
Described embedded device carries out entropy code to the macro block data of described 4K;
The macro block data of 4K after described timestamp and entropy code is merged into video code flow by described embedded device.
Preferably, merge the step of described encoded each road 2K HD video at described embedded device before, also comprise:
Each road 2K HD video described in described embedded device buffer memory;
Described each road 2K HD video that described embedded device output time stamp is consistent.
Preferably, described 4K ultra high-definition video comprises at least one of Quad Full HD 4K, Full Aperture 4K, Academy 4K; Described default value is 4.
The embodiment of the invention also discloses a kind of coded system of 4K ultra high-definition video of Embedded equipment, comprising:
Be positioned at the segmentation module of embedded device, for being multichannel 2K HD video by described 4K ultra high-definition Video segmentation;
Be positioned at the coding module of embedded device, for encoding to described each road 2K HD video respectively;
Be positioned at the merging module of embedded device, for merging described encoded each road 2K HD video.
Preferably, the segmentation module being positioned at embedded device described in comprises:
Be positioned at the calculating sub module of embedded device, calculate the described resolution of 4K ultra high-definition video and the quotient of default value for described embedded device;
Be positioned at the segmentation submodule of embedded device, for the 2K HD video of to be multipath resolution by described 4K ultra high-definition Video segmentation be described quotient.
Preferably, the coding module being positioned at embedded device described in comprises:
Being positioned at the encoding submodule of embedded device, for adopting pre-arranged code agreement, respectively described 2K HD video being encoded;
Be positioned at the interpolation submodule of embedded device, for adding timestamp respectively for each road 2K HD video;
Be positioned at embedded device first merges submodule, for each road 2K HD video corresponding for described timestamp is merged into video code flow.
Preferably, described encoded each road 2K HD video includes the macro block data of some 2K respectively, and the cataloged procedure of described pre-arranged code agreement comprises entropy code; The described merging module being positioned at embedded device comprises:
Be positioned at the decoding sub-module of embedded device, for decoding the macro block data of each road 2K from the 2K HD video of described each road;
Being positioned at the arrangement submodule of embedded device, for being arranged according to the order of sequence by the macro block data of described each road 2K, again forming the macro block data of 1 road 4K;
Be positioned at the entropy code submodule of embedded device, for carrying out entropy code to the macro block data of described 4K;
Be positioned at embedded device second merges submodule, for the macro block data of 4K after described timestamp and entropy code is merged into video code flow.
Compared with prior art, the embodiment of the present invention comprises following advantage:
In the embodiment of the present invention, 4K ultra high-definition video is divided into 4 road 2K HD videos, compression coding is carried out again in synchronous driving to embedded device, utilize the macro block data of encoded 2K HD video to carry out the synthesis of code stream rank after coding, again synthesize the ultra high-definition video of resolution 4K and carry out flow transmission.The embodiment of the present invention does not need to complete 4K ultra high-definition video by high-performance CPU or high-performance special chip, and the dsp chip of the segmentation and 4 general performances that only need a fpga chip to carry out video is encoded, 4K ultra high-definition Video coding can be completed, reduce cost and CPU power consumption, there is stability, and can secondary development be carried out.Further, owing to carrying out in the process of Code And Decode to macro block data, the entropy code of macro block data has just been carried out, and do not relate to the process of other Code And Decode of video, therefore, do not need to take too many CUP performance, even the CPU in embedded device also can simply tackle.In embodiments of the present invention, the synchronous process of video can also be carried out, concrete steps are first buffer memory part 2K HD video, and then export each road 2K HD video of institute's buffer memory, only need synchronous process wherein and bit-stream synthesis only need take a small amount of cpu performance in actual applications.Not video processing procedure necessary in the embodiment of the present invention owing to synchronously processing, if save this step, can real-time be improved.
Accompanying drawing explanation
Fig. 1 is the flow chart of steps of the coding method embodiment 1 of the 4K ultra high-definition video of a kind of Embedded equipment of the present invention;
Fig. 2 is the schematic diagram of the chronological order of a kind of macro block data of the present invention;
Fig. 3 is the schematic diagram of the arrangement of a kind of macro block data of the present invention;
Fig. 4 is the flow chart of steps of the coding method embodiment 2 of the 4K ultra high-definition video of a kind of Embedded equipment of the present invention;
Fig. 5 is the process schematic that the 4K ultra high-definition video of a kind of Embedded equipment of the present invention carries out coded treatment;
Fig. 6 is the structured flowchart of the coded system embodiment of the 4K ultra high-definition video of a kind of Embedded equipment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Current main flow embedded device, the 2K HD video of the resolution of the 1920x1080 that mostly can only encode.In audio frequency and video field, be the 4K ultra high-definition video of 3840 × 2160 for resolution, be 4 times of the 2K HD video of the resolution of 1920x1080 just, belong to ultra high-definition resolution.Under this resolution, spectators can see each details in picture clearly, each feature.If adopt the resolution of surprising 3840 × 2160, therefore no matter in which position watch, spectators clearly can see each details of picture, and film is bright in luster, the clear Ruili of word, coordinate super true audio again, this Feeling be a kind of enjoyment being difficult to explain in words.
But if when using the CPU of high performance x86 computer to carry out process video compression for 4K ultra high-definition video, its power consumption is higher, and real-time is poor, and the CPU cost that can process 4K ultra high-definition video is also relatively high.In addition, for DSP (the digital signal processor of 4K ultra high-definition Video coding, digital processing chip) also less at present, mainstream chip manufacturer gets involved not yet on a large scale, the chip poor universality that little manufacturer provides, be not easy to secondary development, and due to demand and output very low, its price is also high.Inventor herein is based on above-mentioned situation just, creatively one of core idea proposing the embodiment of the present invention is, in embedded device, utilize fpga chip that 4K ultra high-definition video is divided into 4 road 2K HD videos, synchronous driving give 4 independently dsp chip carry out compression coding, utilize H.264 macro block data to carry out the synthesis of code stream rank after coding, again synthesize 4K ultra high-definition video and carry out flow transmission.Like this, the dsp chip that only needs 4 performances are general can complete the coding of 4K ultra high-definition video, greatly reduces cost and CPU power consumption, has real-time, stability, and can carry out secondary development.In addition, if desired carry out the Synchronization Control of each road video, also only need take a small amount of cpu performance.
With reference to Fig. 1, show the flow chart of steps of the coding method embodiment 1 of the 4K ultra high-definition video of a kind of Embedded equipment of the present invention, specifically can comprise the steps:
Step 101, described 4K ultra high-definition Video segmentation is multichannel 2K HD video by described embedded device;
In specific implementation, 4K ultra high-definition video can refer to that resolution is the ultra high-definition video of 4096 × 2160 in theory, in addition, and Quad Full HD 4K (resolution is 3840 × 2160), Full Aperture 4K (resolution is 4096x 3112), Academy 4K (resolution is 3656 × 2664) can be subdivided into, because Quad Full HD 4K is closer to display Aspect Ratio 16: 9, therefore main this standard of employing in television set manufacture and related software research and development.
In a kind of example of embody rule of the present invention, be the Quad Full HD 4K of 3840 × 2160 for resolution, the 2K HD video that resolution is 1920x1080 can be divided into; For the Full Aperture 4K that resolution is 4096x 3112, the 2K HD video that resolution is 2048x1556 can be divided into; For the Academy 4K that resolution is 3656 × 2664, then can be divided into the 2K HD video that resolution is 1828x1332.
In one preferred embodiment of the invention, described step 101 can comprise following sub-step:
Sub-step S11, described embedded device calculates the described resolution of 4K ultra high-definition video and the quotient of default value;
Sub-step S12, the 2K HD video of described embedded device to be multipath resolution by described 4K ultra high-definition Video segmentation be described quotient.
In a kind of example of embody rule of the present invention, in embedded device, be provided with FPGA (Field Programmable Gate Array, field programmable gate array).FPGA is a kind of programmable chip, can parallel processing mass data, and it is used for the work such as convergent-divergent, synthesis, fractionation, conversion of video in field of video processing, has that cost is low, real-time high.
For the Quad Full HD 4K that resolution is 3840 × 2160, can utilize FPGA that 4K ultra high-definition video is divided into 4 parts according to field word in embodiments of the present invention, every part is the 2K HD video of resolution 1920 × 1080, more respectively synchronous driving to 4 in embedded device independently dsp chip carry out compression coding.
It should be noted that, can also be the video of other resolution by 4K ultra high-definition Video segmentation in embodiments of the present invention, be such as divided into the video of SD video or other resolution, the embodiment of the present invention not be limited this.In addition, the embodiment of the present invention is for 8K ultra high-definition video, namely the video of 4K ultra high-definition video resolution 4 times is suitable for too, and 8K ultra high-definition video can be split as multiple 4K ultra high-definition video or 2K HD video, the embodiment of the present invention is not limited this equally.
Step 102, described embedded device is encoded to described each road 2K HD video respectively;
In one preferred embodiment of the invention, described step 102 can comprise following sub-step:
Sub-step S21, described embedded device adopts pre-arranged code agreement, encodes respectively to described 2K HD video;
Sub-step S22, described embedded device adds timestamp respectively for each road 2K HD video;
Sub-step S23, each road 2K HD video corresponding for described timestamp is merged into video code flow by described embedded device.
In a kind of example of embody rule of the present invention, in embedded device, be provided with multiple mutual independently dsp chip.Dsp chip is the general purpose processing chips that a kind of output is higher, is used for video coding and decoding technology.
The 2K HD video split is used H.264 agreement by dsp chip respectively, or other compressed encoding agreements such as MPEG4 agreement carry out compressed encoding, when adding collection, embedded device provides clock information (timestamp) for each road 2K HD video of segmentation, Data Synthesis ES (Elementary Stream, primary flow/elementary stream) after compressed encoding.
Step 103, described embedded device carries out the synthesis of code stream level to described encoded each road 2K HD video.
In one preferred embodiment of the invention, described encoded each road 2K HD video can include some macro block datas, and described step 103 can comprise following sub-step:
Sub-step S31, described embedded device decodes the macro block data of each road 2K from the 2K HD video of described each road;
Sub-step S32, the macro block data of described each road 2K arranges by described embedded device according to the order of sequence, again forms the macro block data of 1 road 4K;
Sub-step S33, described embedded device carries out entropy code to the macro block data of described 4K;
Sub-step S34, the macro block data of 4K after described timestamp and entropy code is merged into video code flow by described embedded device.
In Video coding; usually some macro block datas (Macroblock) are divided in the video image of encoded 2K HD video; macro block data can be understood as in a video image and is divided into a lot of fritter, and the data after the compression of each block are exactly macro block data.A macro block data can be made up of a luminance pixel block and two additional chroma pixel blocks.The block of pixels of usual luminance pixel block to be resolution be 16 × 16 sizes, and the size of two chroma pixel blocks is determined according to the sample format of its video image, such as: for the video image adopting yuv video coding protocol, the block of pixels of chroma pixel block to be resolution be 8 × 8 sizes.In each video image, some macro block datas are arranged form in blocks, and video encoding protocol is in units of macro block data, and macro block data carries out entropy code one by one, are organized into continuous print video code flow (4K ultra high-definition video).
In embodiments of the present invention, by the synchronous driving of 2K HD video give 4 independently dsp chip encode, utilize the macro block data in encoded each road 2K HD video to carry out the synthesis of code stream rank after coding, again synthesize the ultra high-definition video line flow transmission of 4K resolution.Wherein, the synthesis of video code flow be based on Video coding after code rate data, by resolving the structure in bit stream data, again the work of Video Composition is realized after layout, for H.264 protocol code, after coding, the macro block data of 2K HD video is with coordinate information, by changing coordinate information, multiple 2K HD video can being synthesized same video code flow, a complete 4K ultra high-definition video will be obtained when decoding this video code flow.
In specific implementation, H.264 protocol code and decoding process mainly comprise 5 parts: interframe and infra-frame prediction (Estimation), conversion (Transform) and inverse transformation, quantification (Quantization) and inverse quantization, loop filtering (LoopFilter), entropy code (EntropyCoding).
In embodiments of the present invention, in H.264 agreement or other agreements, compressed video data is in fact produced afterwards by entropy code (CABAC) by some macro block datas, after the 2K HD video decompress(ion) after coding, obtain all macro block datas, Video Composition is carried out, in specific implementation according to FMO pattern (Flexible Mcroblock Ordering, flexible working space), according to the difference of FMO pattern, the method for Video Composition is also different.For common raster scan pattern, the chronological order of concrete macro block data can with reference to the schematic diagram of the chronological order of the of the present invention a kind of macro block data shown in Fig. 2.In order to the packed data (i.e. 2K HD video) of 4 same sizes is synthesized, so need to carry out CABAC decoding respectively, after obtaining all macro block datas, (be such as the 2K HD video of 1920 × 1080 for resolution according to " width ", by its width pixel 1920/16=120, then width is 120 macro block datas) again split, arrange, concrete alignment processes can with reference to the schematic diagram of the arrangement of the of the present invention a kind of macro block data shown in Fig. 3.When after the arrangement completing one-frame video data, re-start CABAC entropy code, add the identical timestamp formerly added, generate new video code flow (i.e. 4K ultra high-definition video).
It should be noted that, the process Shi Ge road 2k high definition video decoding of code stream level synthesis carried out in embodiments of the present invention goes out macro block data, the macro block data on each road is rearranged together, forms a large video image, then the macro block data that this has merged is encoded into H.264 data.In embodiments of the present invention except the first time coding of 2K HD video is the coding utilizing H.264 agreement or other coding protocols to carry out, the said encoding and decoding of other links are all the entropy code of decoded macroblock rank.Be appreciated that because this encoding-decoding process does not relate to other Code And Decode process of video content, just need to carry out entropy code to macro block data, therefore the performance of too many CPU can not be taken, even the CPU of embedded device also can simply tackle.
Also it should be noted that, according to the difference of the arrangement mode of macro block data sequence in video, other modes also can be adopted to carry out the sequence of macro block data, and to generate new video code flow, the embodiment of the present invention is not limited this.
With reference to Fig. 4, show the flow chart of steps of the coding method embodiment 2 of the 4K ultra high-definition video of a kind of Embedded equipment of the present invention, specifically can comprise the steps:
Step 201, described 4K ultra high-definition Video segmentation is multichannel 2K HD video by described embedded device;
Step 202, described embedded device is encoded to described each road 2K HD video respectively;
Step 203, each road 2K HD video described in described embedded device buffer memory;
Step 204, described each road 2K HD video that described embedded device output time stamp is consistent;
In specific implementation, due to problems such as transmission delays, may occur the nonsynchronous problem of each road 2K HD video, in this case, for improving the synchronous precision play, the embodiment of the present invention considers the delay of transmission, synchronously can process 2K HD video.In a kind of preferred exemplary of the present invention, can first buffer memory part 2K HD video, and then each road 2K HD video that the timestamp exporting institute's buffer memory is consistent.2K HD video is synchronously processed, synchronism during control 4 road 2K HD video synthesis that can be stricter.
Step 205, described embedded device carries out the synthesis of code stream level to described encoded each road 2K HD video.
In embodiments of the present invention, owing to needing buffer memory part 2K HD video in synchronous processing procedure, so for the high application of requirement of real-time, also can save the process of carrying out synchronous process, the processing speed of embedded chip is relatively stable, and the scramble time of each frame video is only relevant with complexity of video content, therefore, so long as not the high dynamic video of process, economizing the processing procedure that desynchronizes also obviously can not affect final effect, thus the embodiment of the present invention to this without the need to being limited.
The method utilizing multiple general dsp chip synchronization to encode of the present invention, 4K ultra high-definition video is split as 4 road 2K HD videos, by 2K HD video simultaneous techniques and bit-stream synthesis technology, the 4K ultra high-definition video that final generation encodes, on the basis having ensured real-time, stability, greatly reduce cost.
It should be noted that, for embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the embodiment of the present invention is not by the restriction of described sequence of movement, because according to the embodiment of the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in specification all belongs to preferred embodiment, and involved action might not be that the embodiment of the present invention is necessary.
With reference to Fig. 5, show the structured flowchart of the coded system embodiment of the 4K ultra high-definition video of a kind of Embedded equipment of the present invention, specifically can comprise as lower module:
Be positioned at the segmentation module 301 of embedded device, for being multichannel 2K HD video by described 4K ultra high-definition Video segmentation;
Described 4K ultra high-definition video can comprise at least one of Quad Full HD 4K, Full Aperture 4K, Academy 4K.
In one preferred embodiment of the invention, the segmentation module 201 being positioned at embedded device described in can comprise following submodule:
Be positioned at the calculating sub module of embedded device, calculate the described resolution of 4K ultra high-definition video and the quotient of default value for described embedded device; Described default value can be 4;
Be positioned at the segmentation submodule of embedded device, for the 2K HD video of to be multipath resolution by described 4K ultra high-definition Video segmentation be described quotient.
Be positioned at the coding module 302 of embedded device, for encoding to described each road 2K HD video respectively;
In one preferred embodiment of the invention, the coding module 302 of described embedded device can comprise following submodule:
Being positioned at the encoding submodule of embedded device, for adopting pre-arranged code agreement, respectively described 2K HD video being encoded;
Be positioned at the interpolation submodule of embedded device, for adding timestamp respectively for each road 2K HD video;
Be positioned at embedded device first merges submodule, for each road 2K HD video corresponding for described timestamp is merged into video code flow.
In one preferred embodiment of the invention, described system can also comprise as lower module:
Be positioned at the cache module of embedded device, for each road 2K HD video described in buffer memory;
Be positioned at the output module of embedded device, for described each road 2K HD video that output time stamp is consistent.
Be positioned at the merging module 303 of embedded device, for carrying out the synthesis of code stream level to described encoded each road 2K HD video.
In one preferred embodiment of the invention, described encoded each road 2K HD video includes some macro block datas, described in be positioned at embedded device merging module 303 can comprise following submodule:
Be positioned at the decoding sub-module of embedded device, for decoding the macro block data of each road 2K from the 2K HD video of described each road;
Being positioned at the arrangement submodule of embedded device, for being arranged according to the order of sequence by the macro block data of described each road 2K, again forming the macro block data of 1 road 4K;
Be positioned at the encoding submodule of embedded device, for carrying out entropy code to the macro block data of described 4K;
Be positioned at embedded device second merges submodule, for the macro block data of 4K after described timestamp and entropy code is merged into video code flow.
In order to make those skilled in the art understand the embodiment of the present invention further, concrete example is below adopted to be described the process that the 4K ultra high-definition video towards embedded device carries out coded treatment.
4K ultra high-definition video with reference to the of the present invention a kind of Embedded equipment shown in Fig. 6 carries out the process schematic of coded treatment, input module (being positioned at the segmentation module of embedded device), coding module (being positioned at the coding module of embedded device), synchronization module (being positioned at the synchronization module of embedded device), synthesis module (being positioned at the synthesis module of embedded device) can be comprised in this embedded device, wherein input module is made up of fpga chip, coding module is made up of dsp chip, and process is as follows particularly:
1, input module gathers 4K ultra high-definition video;
2,4K ultra high-definition Video segmentation is 4 2K HD videos by input module, and exports 4 coding modules respectively to;
3,4 coding modules process the 2K HD video split on 4 tunnels simultaneously, carry out compression coding, can stab in cataloged procedure to the 2K HD video joining day;
4, synchronization module is according to the timestamp information of each road 2K HD video, synchronously processes, and be transferred to synthesis module to 2K HD video;
5, synthesis module resolves the h264 macro block data in coding 2K HD video, changes coordinate information, 4 road 2K HD video bit-stream synthesis are a 4K ultra high-definition video and are exported.
In the embodiment of the present invention, 4K ultra high-definition video is divided into 4 road 2K HD videos, compression coding is carried out again in synchronous driving to embedded device, utilize the macro block information of encoded 2K HD video to carry out the synthesis of code stream rank after coding, again synthesize the ultra high-definition video of resolution 4K and carry out flow transmission.The embodiment of the present invention does not need to complete 4K ultra high-definition video by high-performance CPU or high-performance special chip, and the dsp chip of the segmentation and 4 general performances that only need a fpga chip to carry out video is encoded, 4K ultra high-definition Video coding can be completed, reduce cost and CPU power consumption, there is stability, and can secondary development be carried out.Further, owing to carrying out in the process of Code And Decode to macro block data, the entropy code of macro block data has just been carried out, and do not relate to the process of other Code And Decode of video, therefore, do not need to take too many CUP performance, even the CPU in embedded device also can simply tackle.
In embodiments of the present invention, the synchronous process of video can also be carried out, concrete steps are first buffer memory part 2K HD video, and then export institute's cache-time and stab consistent each road 2K HD video, only need synchronous process wherein and bit-stream synthesis only need take a small amount of cpu performance in actual applications.Not video processing procedure necessary in the embodiment of the present invention owing to synchronously processing, if save this step, can real-time be improved.
For system embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Those skilled in the art should understand, the embodiment of the embodiment of the present invention can be provided as method, device or computer program.Therefore, the embodiment of the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the embodiment of the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disc store, CD-ROM, optical memory etc.) of computer usable program code.
The embodiment of the present invention describes with reference to according to the flow chart of the method for the embodiment of the present invention, terminal equipment (system) and computer program and/or block diagram.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can being provided to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing terminal equipment to produce a machine, making the instruction performed by the processor of computer or other programmable data processing terminal equipment produce device for realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing terminal equipment, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be loaded on computer or other programmable data processing terminal equipment, make to perform sequence of operations step to produce computer implemented process on computer or other programmable terminal equipment, thus the instruction performed on computer or other programmable terminal equipment is provided for the step realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
Although described the preferred embodiment of the embodiment of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of embodiment of the present invention scope.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or terminal equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or terminal equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the terminal equipment comprising described key element and also there is other identical element.
Above to the code device of the coding method of the 4K ultra high-definition video of a kind of Embedded equipment provided by the present invention and a kind of 4K ultra high-definition video of Embedded equipment, be described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a coding method for the 4K ultra high-definition video of Embedded equipment, is characterized in that, comprising:
Described 4K ultra high-definition Video segmentation is multichannel 2K HD video by described embedded device;
Described embedded device is encoded to described each road 2K HD video respectively;
Described embedded device carries out the synthesis of code stream level to described encoded each road 2K HD video.
2. method according to claim 1, is characterized in that, the step that described 4K ultra high-definition Video segmentation is multichannel 2K HD video by described embedded device comprises:
Described embedded device calculates the described resolution of 4K ultra high-definition video and the quotient of default value;
The 2K HD video of described embedded device to be multipath resolution by described 4K ultra high-definition Video segmentation be described quotient.
3. method according to claim 1, is characterized in that, described embedded device comprises the step that described each road 2K HD video is encoded respectively:
Described embedded device adopts pre-arranged code agreement, encodes respectively to described 2K HD video;
Described embedded device adds timestamp respectively for each road 2K HD video;
Each road 2K HD video corresponding for described timestamp is merged into video code flow by described embedded device.
4. method according to claim 3, is characterized in that, described encoded each road 2K HD video includes the macro block data of some 2K respectively, and the cataloged procedure of described pre-arranged code agreement comprises entropy code; Described embedded device comprises the step that described encoded each road 2K HD video carries out the synthesis of code stream level:
Described embedded device decodes the macro block data of each road 2K from the 2K HD video of described each road;
The macro block data of described each road 2K arranges by described embedded device according to the order of sequence, again forms the macro block data of 1 road 4K;
Described embedded device carries out entropy code to the macro block data of described 4K;
The macro block data of 4K after described timestamp and entropy code is merged into video code flow by described embedded device.
5. method according to claim 3, is characterized in that, before merging the step of described encoded each road 2K HD video, also comprises at described embedded device:
Each road 2K HD video described in described embedded device buffer memory;
Described each road 2K HD video that described embedded device output time stamp is consistent.
6. method according to claim 1, is characterized in that, described 4K ultra high-definition video comprises at least one of Quad Full HD 4K, Full Aperture 4K, Academy 4K; Described default value is 4.
7. a coded system for the 4K ultra high-definition video of Embedded equipment, is characterized in that, comprising:
Be positioned at the segmentation module of embedded device, for being multichannel 2K HD video by described 4K ultra high-definition Video segmentation;
Be positioned at the coding module of embedded device, for encoding to described each road 2K HD video respectively;
Be positioned at the merging module of embedded device, for merging described encoded each road 2K HD video.
8. system according to claim 7, is characterized in that, described in be positioned at embedded device segmentation module comprise:
Be positioned at the calculating sub module of embedded device, calculate the described resolution of 4K ultra high-definition video and the quotient of default value for described embedded device;
Be positioned at the segmentation submodule of embedded device, for the 2K HD video of to be multipath resolution by described 4K ultra high-definition Video segmentation be described quotient.
9. system according to claim 7, is characterized in that, described in be positioned at embedded device coding module comprise:
Being positioned at the encoding submodule of embedded device, for adopting pre-arranged code agreement, respectively described 2K HD video being encoded;
Be positioned at the interpolation submodule of embedded device, for adding timestamp respectively for each road 2K HD video;
Be positioned at embedded device first merges submodule, for each road 2K HD video corresponding for described timestamp is merged into video code flow.
10. system according to claim 9, is characterized in that, described encoded each road 2K HD video includes the macro block data of some 2K respectively, and the cataloged procedure of described pre-arranged code agreement comprises entropy code; The described merging module being positioned at embedded device comprises:
Be positioned at the decoding sub-module of embedded device, for decoding the macro block data of each road 2K from the 2K HD video of described each road;
Being positioned at the arrangement submodule of embedded device, for being arranged according to the order of sequence by the macro block data of described each road 2K, again forming the macro block data of 1 road 4K;
Be positioned at the entropy code submodule of embedded device, for carrying out entropy code to the macro block data of described 4K;
Be positioned at embedded device second merges submodule, for the macro block data of 4K after described timestamp and entropy code is merged into video code flow.
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