CN104183571A - Through-silicon via and manufacturing process thereof - Google Patents
Through-silicon via and manufacturing process thereof Download PDFInfo
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- CN104183571A CN104183571A CN201310201230.XA CN201310201230A CN104183571A CN 104183571 A CN104183571 A CN 104183571A CN 201310201230 A CN201310201230 A CN 201310201230A CN 104183571 A CN104183571 A CN 104183571A
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Abstract
The invention discloses a through-silicon via and a manufacturing process thereof. The through-silicon via comprises a substrate and a conductive plug; a hole is formed in the substrate and is located in one surface. The conductive plug arranged in the hole has an upper half portion protruded out of the surface; the upper half portion includes a top portion and a bottom portion, wherein the top portion is thinner than the bottom portion. In addition, the invention also provides a manufacturing process for forming the through-silicon via. The method includes the following steps: providing a substrate having one surface; forming a hole in the surface of the substrate; forming a first conductive material covering the hole and the surface; forming a patterned photoresist to cover the surface and expose the hole; forming a second conductive material on the exposed first conductive material; removing the patterned photoresist; and removing the first conductive material on the surface to form a conductive plug in the hole.
Description
Technical field
The present invention relates to a kind of straight-through silicon wafer perforation and manufacture craft thereof, and particularly relate to a kind of straight-through silicon wafer perforation and the manufacture craft thereof of a conductive filling material in a hole that first formed before forming a photoresist.
Background technology
Straight-through silicon wafer puncturing technique is mainly to solve the problem of chip chamber interconnection, belongs to a kind of new three-dimensional space three-dimensional encapsulation technology.Hot straight-through silicon wafer puncturing technique by tridimensional stacking, via silicon perforating wound, produce and more meet light, thin, short, little market demand product, the required packaging manufacturing process technology of wafer-class encapsulation such as MEMS (micro electro mechanical system) (MEMS), photoelectricity and electronic component are provided.
Specifically, straight-through silicon wafer puncturing technique is holed in the mode of etching or laser on wafer, then electric conducting material is inserted to the passage (the joint circuit that connects inside and outside portion) that guide hole (Via) forms conduction as copper, polysilicon, tungsten etc.Finally by wafer or tube core (die) thinning more in addition stacking, in conjunction with (bonding), and become tridimensional piling IC (3D IC).Thus, just can replace routing and link (wire bonding) mode.Change in etched mode and hole (Via) and form conduction electrode, not only can save routing space, also can dwindle the usable floor area of circuit board and the volume of packaging part.Because adopt the structure dress interior bonds distance of straight-through silicon wafer puncturing technique, be wafer after thinning or the thickness of tube core, compared to the traditional stack encapsulation of taking routing to link, the inside access path of three-dimensional space piling IC is shorter, relatively can make the transmission resistance of chip chamber less, speed is faster, noise is less, usefulness is better.Especially at central processing unit (CPU) and memory cache body, and in the transfer of data in memory card application, more can highlight the usefulness advantage that bring in the short distance interior bonds path of straight-through silicon wafer puncturing technique.In addition, the size after the encapsulation of three-dimensional space piling IC is equal to die-size.Emphasizing multi-functional, undersized portable electronic product field, the miniaturization characteristic of the three-dimensional space piling IC primary factor that market imports especially.
Yet along with the size micro of semiconductor element, the straight-through silicon wafer perforation in these a little semiconductor elements can be because having high-aspect-ratio, and be difficult to form in semiconductor fabrication process now.
Summary of the invention
The object of the invention is to propose a kind of straight-through silicon wafer perforation and manufacture craft thereof, it is before forming a photoresist, first fill an electric conducting material in a hole, to form a part for this straight-through silicon wafer perforation, thereby can reduce the degree of depth that follow-up photoresist is inserted this hole.
For reaching above-mentioned purpose, the invention provides a kind of straight-through silicon wafer perforation, comprise a substrate and a conductive plunger.Substrate has a hole, is arranged in one side.Conductive plunger is arranged in hole, and conductive plunger has a first half and protrude from this face, and wherein the first half has a top and a bottom, and top is thin compared with bottom.
The invention provides a kind of straight-through silicon wafer perforation manufacture craft, comprise following step.First, provide a substrate, there is one side.Then,, from this face of substrate, form a hole.Continue, form one first electric conducting material coverage hole and this face.Continue it, form a patterning photoresist coverage rate and also expose hole.Then, form one second electric conducting material on the first electric conducting material exposing.Then, remove patterning photoresist.Remove first electric conducting material be arranged in face on to form a conductive plunger in hole thereafter.
Based on above-mentioned, the present invention proposes a kind of straight-through silicon wafer perforation and manufacture craft thereof, and it,, before forming a patterning photoresist, first fills one first electric conducting material in a hole of a substrate.Therefore, can reduce the degree of depth that photoresist is inserted hole, so that photoresist is easy to remove.Moreover, after forming patterning photoresist, insert on first electric conducting material of one second electric conducting material in hole, then remove patterning photoresist, then remove again the first electric conducting material of being positioned at outside hole to form a conductive plunger.Because the first electric conducting material being positioned at outside hole removes with for example etching method, thereby conductive plunger protrudes from a first half of substrate, can have a top thin compared with a bottom.
Accompanying drawing explanation
Fig. 1 is the generalized section that illustrates the straight-through silicon wafer perforation manufacture craft of one embodiment of the invention;
Fig. 2-Fig. 4 is the generalized section that illustrates the straight-through silicon wafer perforation manufacture craft of the present invention one first embodiment;
Fig. 5-Figure 10 is the generalized section that illustrates the straight-through silicon wafer perforation manufacture craft of the present invention one second embodiment;
Figure 11 is the generalized section that illustrates the straight-through silicon wafer perforation manufacture craft of one embodiment of the invention;
Figure 12 is the generalized section that illustrates the straight-through silicon wafer perforation manufacture craft of one embodiment of the invention.
Main element symbol description
100,200: straight-through silicon wafer perforation
110,310,410: substrate
120,120 ', 220,220 ': barrier layer
130,130 ', 230,230 ': crystal seed layer
140: leading electric material
150,250: conductive pad
242: the first electric conducting materials
242a: hole part
242b: surperficial part
246: the second electric conducting materials
320,420: interlayer dielectric layer
340,440: the internal connection-wire structure of multilayer
C1, C2: conductive plunger
K1, K2: patterning photoresist
M:MOS transistor
S1: face
S2: front
S3: the back side
T1: the first half
T11: top
T12: bottom
T2: Lower Half
V, V1, V2: hole
Embodiment
Fig. 1 is the generalized section that illustrates the straight-through silicon wafer perforation manufacture craft of one embodiment of the invention.As shown in Figure 1, provide a substrate 110, there is a hole V.In the present embodiment, hole V-arrangement is formed in the one side S1 of substrate 110, and wherein face S1 can be the another side that an active surface is relative, or the one side identical with active surface, but the present invention is not as limit.Substrate 110 be for example a silicon base, one containing silicon base, a San Wu family cover silicon base (for example GaN-on-silicon), a Graphene covers the semiconductor bases such as silicon base (graphene-on-silicon) or one silicon-coated insulated (silicon-on-insulator, SOI) substrate.Hole V can for example form with etching, but the present invention is not as limit.Hole V has a high-aspect-ratio, in order to form a straight-through silicon wafer perforation structure.Generally speaking, the depth-to-width ratio of hole V is between 3.5～10, and its critical dimension (critical dimension, CD) is less than 18 microns (micrometer, μ m), but the present invention is not as limit.
Below propose two embodiment, the step of hookup 1, to form straight-through silicon wafer perforation.
Fig. 2-Fig. 4 is the generalized section that illustrates the straight-through silicon wafer perforation manufacture craft of the present invention one first embodiment.As shown in Figure 2, first optionally form a laying (not illustrating) and conformably cover substrate 110.Laying (not illustrating) is for example an oxide layer, and in order to substrate 110 is electrically insulated, but the present invention is not limited with this material.Then, form a barrier layer 120 on laying.Barrier layer 120 can comprise the structure of the single or multiple lift that titanium nitride layer or tantalum nitride layer etc. form, but the present invention is not as limit.
Afterwards, selectivity forms a crystal seed layer 130 on barrier layer 120.Crystal seed layer 130 can physical vapour deposition (PVD) (physical vapor deposition, PVD) manufacture craft form, the use that provides follow-up leading electric material formed thereon to adhere to, but the present invention is not as limit.Form a patterning photoresist K1 coverage rate S1 but expose hole V.Specifically, can first form the comprehensive coverage rate S1 of a photoresist (not illustrating) and at least fill a part of hole V.Then, patterning photoresist is with coverage rate S1 but expose hole V.
As shown in Figure 3, insert a leading electric material 140 in the hole V exposing and be formed on the crystal seed layer 130 of part.Leading electric material 140 can for example be comprised of copper (copper, Cu), and can for example by electro-plating method, be formed, but the present invention is not as limit.Then, form a conductive pad 150 on leading electric material 140.Conductive pad 150 can be for example nickel, tin or gold, and it for example forms by the method for pressurizeing, but the present invention is not as limit.
Afterwards, remove patterning photoresist K1, and remove in the lump crystal seed layer 130 and the barrier layer 120 that is positioned at the part exposing under patterning photoresist K1, thereby form barrier layer 120 ' and crystal seed layer 130 ', as shown in Figure 4.Patterning photoresist K1, crystal seed layer 130 and barrier layer 120 can for example remove with same manufacture craft, or such as manufacture crafts such as etching process, sequentially remove it with a plurality of.Therefore, can form a plurality of conductive plunger C1 in hole V, conductive plunger C1 can comprise barrier layer 120 ', crystal seed layer 130 ' and leading electric material 140.
Hold, 100 of straight-through silicon wafer perforation are formed in the hole V of substrate 110, and wherein straight-through silicon wafer perforation 100 comprises conductive plunger C1 and conductive pad 150.Yet, owing to having between 3.5～10 depth-to-width ratio and the critical dimension that is less than 18 microns in order to form the hole V of straight-through silicon wafer perforation 100, thereby cause facing serious problem when forming patterning photoresist K1.Because when forming photoresist comprehensively, photoresist also can be inserted in hole V, and when wish forms patterning photoresist K1 by photoresist patterning, the photoresist that is arranged in hole V is because the capillarity that the high-aspect-ratio of hole V produces faces the problem that is difficult to remove.
Therefore, below propose one second embodiment, in order to form the straight-through silicon wafer perforation of an improvement, and address the above problem.Fig. 5-Figure 10 is the generalized section that illustrates the straight-through silicon wafer perforation manufacture craft of the present invention one second embodiment.
After carrying out the step of Fig. 1, refer to Fig. 5, first optionally form a laying (not illustrating) and conformably cover substrate 110.Laying is for example an oxide layer, and in order to substrate 110 is electrically insulated, but the present invention is not limited with this material.Sequentially form a barrier layer 220 and crystal seed layer 230 coverage hole V and a face S1.Barrier layer 220 can comprise the structure of the single or multiple lift that titanium nitride layer or tantalum nitride layer etc. form; Crystal seed layer 230 can physical vapour deposition (PVD) (physical vapor deposition, PVD) manufacture craft form, and with the use that provides follow-up electric conducting material formed thereon to adhere to, but the present invention is not as limit.
As shown in Figure 6, form one first electric conducting material 242 coverage hole V and face S1, the first electric conducting material 242 like this comprises that a hole part 242a is arranged in hole V and a surperficial part 242b is positioned on face S1.The first electric conducting material 242 can be for example copper, and it is for example to electroplate formation, but the present invention is not as limit.Preferably, the depth-to-width ratio that the first electric conducting material 242 is formed to remaining hole V is less than 3.Better person, the depth-to-width ratio that the first electric conducting material 242 is formed to remaining hole V is 2.5.Thus, when the depth-to-width ratio of remaining hole is less than 3, can be easy to remove the follow-up photoresist of inserting hole V.
As shown in Figure 7, form a patterning photoresist K2 coverage rate S1 but expose hole V.Specifically, can first form the comprehensive coverage rate S1 of a photoresist (not illustrating) and insert at least part of hole V.Then, patterning photoresist is with coverage rate S1 but expose hole V.Thereafter, selectivity is carried out an oxygen and is processed manufacture craft, with after forming patterning photoresist K2, further removes the photoresist residuing in hole V.Owing to first the hole part 242a of the first electric conducting material 242 being inserted to the depth-to-width ratio of hole V to hole V, be less than 3, thereby when patterning photoresist, can remove the photoresist that is arranged in hole V completely.
As shown in Figure 8, form the hole part 242a that one second electric conducting material 246 exposes in the first electric conducting material 242.The second electric conducting material 246 can be for example copper, and it can be for example forms to electroplate, but the present invention is not as limit.Then, form a conductive pad 250 on the second electric conducting material 246.Conductive pad 250 can be for example nickel, tin or gold, and it for example forms by the method for pressurizeing, but the present invention is not as limit.
Remove patterning photoresist K2, and expose the surperficial part 242b of the first electric conducting material 242, as shown in Figure 9.Then, carry out an etching process to remove the surperficial part 242b of the first electric conducting material 242, as shown in figure 10.In the present embodiment, take conductive pad 250 carries out etching process to remove surperficial part 242b as a mask.Now, barrier layer 220 and crystal seed layer 230 are positioned at the part on face S1 or the part that is positioned under surperficial part 242b removes in the lump, thereby form a barrier layer 220 ' and a crystal seed layer 230 '.The barrier layer 220 of surface part 242b, part and crystal seed layer 230 can same manufacture craft remove or a plurality of manufacture craft sequentially removes it.Thus, form conductive plunger C2 and be arranged in hole V, wherein conductive plunger C2 can comprise barrier layer 220 ', crystal seed layer 230 ', the first electric conducting material 242 and the second electric conducting material 246.Conductive plunger C2 can for example be comprised of copper, but the present invention is not as limit.Thus, 200 of straight-through silicon wafer perforation are formed in the hole V of substrate 110, and straight-through silicon wafer perforation 200 can comprise a plurality of conductive plunger C2 and conductive pad 250.
Each conductive plunger C2 has a first half T1 and a Lower Half T2, first half T1 raised face S1 wherein, and Lower Half T2 is positioned at the below of first half T1.At this, emphasize, when the surperficial part 242b of the first electric conducting material 242 be take conductive pad 250 when mask removes, 11 of top T higher than the first half T1 of the surperficial part 242b of the first electric conducting material 242 can be etched, but with a bottom T12 of the contour first half T1 of the surperficial part 242b of the first electric conducting material 242 can be not etched because being covered by surperficial part 242b.Therefore top T 11 can be thin compared with bottom T12.When take conductive pad 250 when mask carries out etching, 11 of top T can be thin compared with conductive pad 250.Preferably, conductive pad 250 has same diameter with bottom T12, therefore (particularly when the distance of each conductive plunger C2 approaches) can avoid conductive plunger C2 to contact with each other and short circuit, more easily to control to lead directly to the bore a hole layout of 200 formed semiconductor elements of silicon wafer.What is more, bottom T12 and Lower Half T2 have same diameter, to form an accurate straight-through silicon wafer with good electric conductivity, bore a hole 200.
Straight-through silicon wafer perforation 200 has respectively six conductive plunger C2 and is arranged in six hole V.Yet the number of conductive plunger C2 is non-is limited to this, it can for example be less than or greater than six.In other words, straight-through silicon wafer perforation 200 can for example only have a conductive plunger C2, and straight-through silicon wafer perforation structure 200 of the present invention and manufacture craft thereof can be applicable in various straight-through silicon wafers perforation manufacture crafts, such as a rear boring (via last) manufacture craft etc.Below will exemplify out the applicable various straight-through silicon wafer perforation manufacture crafts of two kinds of straight-through silicon wafer perforation structures 200 of the present invention and manufacture craft thereof, but range of application of the present invention is non-, be limited to this.
As shown in figure 11, the rear boring manufacturing process steps after metal interconnecting, is first formed at a MOS transistor M in (as shown in left figure) in substrate 310, and forms the internal connection-wire structure 340 of an interlayer dielectric layer 320 and a multilayer; Then, then form a hole V1 in internal connection-wire structure 340, interlayer dielectric layer 320 and the substrate 310 of multilayer by a positive S2 of substrate 310, and form a straight-through silicon wafer perforation 200(as shown at right).
As shown in figure 12, the rear boring manufacturing process steps after metal-oxide-semiconductor (MOS) and before metal interconnecting, that is first complete the making (as shown in left figure) that MOS transistor M etc. wants to be formed at the semiconductor structure of substrate 410; Then form a required interlayer dielectric layer 420, the internal connection-wire structure 440 of a multilayer, then thinning substrate 410, and by a back side S3 of substrate 410, form a hole V2 through substrate 410 and interlayer dielectric layer 420, and form a straight-through silicon wafer perforation 200 and make to be connected (as shown at right) with the Metal Phases such as internal connection-wire structure 440 of multilayer.
In sum, the present invention proposes a kind of straight-through silicon wafer perforation and manufacture craft thereof, and it is covering and patterning and before forming a patterning photoresist, first fill one first electric conducting material in a hole of a substrate.Therefore, can reduce the degree of depth that photoresist is inserted hole, so that photoresist is easy to remove when patterning.Preferably, after forming the first electric conducting material, the depth-to-width ratio of remaining hole is less than 3.
Moreover, after forming patterning photoresist, insert on first electric conducting material of one second electric conducting material in hole, form a conduction and be padded on the second electric conducting material, then remove patterning photoresist and remove again the first electric conducting material of being positioned at outside hole to form conductive plunger.Because the first electric conducting material being positioned at outside hole removes with for example etching method, thereby conductive plunger protrudes from a first half of substrate, and it is thin compared with a bottom that it has a top.Preferably, take conductive pad as mask etching first electric conducting material, thereby top is also thin compared with conductive pad.Better person, conductive pad and bottom have same diameter, therefore (particularly when contiguous conductive plunger mutual distance approaches) can avoid these a little conductive plungers to contact with each other and short circuit.What is more, bottom has same diameter with a Lower Half that is arranged in each conductive plunger of hole, so can form the straight-through silicon wafer perforation of a precision with good electric conductivity.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (20)
1. a straight-through silicon wafer perforation, comprises:
Substrate, has a hole, is arranged in one side;
Conductive plunger, is arranged in this hole, and this conductive plunger has a first half, protrudes from this face, and wherein this first half has a top and a bottom, and this bottom is thin at this top.
2. straight-through silicon wafer perforation as claimed in claim 1, wherein this conductive plunger comprises copper.
3. straight-through silicon wafer perforation as claimed in claim 1, wherein this straight-through silicon wafer perforation also comprises a conductive pad, is positioned on this conductive plunger.
4. straight-through silicon wafer perforation as claimed in claim 3, wherein this conductive pad comprises nickel, tin or gold.
5. straight-through silicon wafer perforation as claimed in claim 3, wherein this conductive pad is thin at this top.
6. straight-through silicon wafer perforation as claimed in claim 3, wherein this conductive pad and this bottom have same diameter.
7. straight-through silicon wafer perforation as claimed in claim 1, wherein a Lower Half of this conductive plunger in this bottom and this hole has same diameter.
8. straight-through silicon wafer perforation as claimed in claim 1, wherein the depth-to-width ratio of this hole is between 3.5～10.
9. straight-through silicon wafer perforation as claimed in claim 1, wherein the critical dimension of this hole (critical dimension, CD) is less than 18 microns (micrometer, μ m).
10. a straight-through silicon wafer perforation manufacture craft, comprises:
One substrate is provided, and it has one side;
From this face of this substrate, form a hole;
Form one first electric conducting material and cover this hole and this face;
Forming a patterning photoresist covers this face and exposes this hole;
Form one second electric conducting material on this first electric conducting material exposing;
Remove this patterning photoresist; And
Remove this first electric conducting material of being arranged on this face to form a conductive plunger in this hole.
11. straight-through silicon wafers perforation manufacture crafts as claimed in claim 10, wherein this conductive plunger has a first half and protrudes from this face, and this first half has a top and a bottom, and this bottom is carefully at this top.
12. straight-through silicon wafer perforation manufacture crafts as claimed in claim 10, wherein the depth-to-width ratio of this hole is between 3.5～10.
13. straight-through silicon wafer perforation manufacture crafts as claimed in claim 10, wherein the critical dimension of this hole (critical dimension, CD) is less than 18 microns (micrometer, μ m).
14. straight-through silicon wafer perforation manufacture crafts as claimed in claim 10, before forming this first electric conducting material, also comprise:
Sequentially form a barrier layer and a crystal seed layer and cover this hole and this face.
15. straight-through silicon wafer perforation manufacture crafts as claimed in claim 10, wherein this first electric conducting material and the second electric conducting material form to electroplate.
16. straight-through silicon wafer perforation manufacture crafts as claimed in claim 12, the depth-to-width ratio that wherein this first electric conducting material is formed to this remaining hole is less than 3.
17. straight-through silicon wafers perforation manufacture crafts as claimed in claim 16, to be wherein formed to the depth-to-width ratio of this remaining hole be 2.5 to this first electric conducting material.
18. straight-through silicon wafer perforation manufacture crafts as claimed in claim 10, before removing this first electric conducting material, also comprise:
Forming a conduction is padded on this second electric conducting material.
19. straight-through silicon wafer perforation manufacture crafts as claimed in claim 18, wherein remove this first conduction material and using this conductive pad as a mask.
20. straight-through silicon wafer perforation manufacture crafts as claimed in claim 10, after forming this patterning photoresist, also comprise:
Carry out an oxygen and process manufacture craft.
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| CN201310201230.XA CN104183571B (en) | 2013-05-27 | 2013-05-27 | Straight-through silicon wafer perforation and its manufacture craft |
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| CN104183571B CN104183571B (en) | 2018-01-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110010575A (en) * | 2018-12-25 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of TSV structure and preparation method thereof of embolism interconnection type |
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| US6333274B2 (en) * | 1998-03-31 | 2001-12-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including a seamless shallow trench isolation step |
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