CN104182578B - Battery power consumption optimization method and system based on reconfigurable arrays - Google Patents
Battery power consumption optimization method and system based on reconfigurable arrays Download PDFInfo
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Abstract
The present invention provides a kind of battery power consumption optimization method and system based on reconfigurable arrays, and wherein method comprises the following steps：Battery behavior is combined with the cyclic mapping of reconfigureable computing array, and carries out circulation fusion in mapping process and splits to obtain multiple cut；Reconfigureable computing array is reconstructed and obtains reconstitution time ΔCFG,PWith average current ICFG,P；Loading time Δ is obtained in the enterprising row data loading of reconfigureable computing array and storage to multiple cut after segmentationLD,P, average current ILD,P, storage time IST,P, average current IST,P；Electric current and required time obtain average current I according to needed for the quantity and corresponding many bit process units of the synchronous many bit process units performedEXE,PWith execution time ΔEXE,P；According to ΔCFG,P、ICFG,P、ΔLD,P、ILD,P、IST,P、IST,P、IEXE,PAnd ΔEXE,PElectric quantity consumption model is obtained, is optimized with the power consumption to battery.Method according to embodiments of the present invention, by the way that battery behavior is corresponding with carried cyclic mapping method, regenerate electric quantity consumption model and battery power consumption is optimized, so as to be effectively improved the service life of battery.
Description
Technical field
The present invention relates to communication-electronics field, more particularly to a kind of battery power consumption optimization based on reconfigurable arrays
Method and system.
Background technology
Coarseness reconfigurable processing structure (being abbreviated as CGRA) is the huge high-performance mobile platform of a prospect, wherein can
Reconstruction calculations array (abbreviation PEA) is CGRA important component.PEA is by bit process unit (abbreviation PE) group more than one group
Into each PE can the different operator of independent operating.When application program, which is mapped to CGRA, to be got on to perform, main is computation-intensive
Type computing, which is mapped on PEA, to be accelerated.It is substantial amounts of to calculate the huge energy expenditure brought, therefore in order to preferably drop
Low-power consumption is, it is necessary to generate effective Array Mapping optimized algorithm.
Present mobile electronic device is mainly battery powered, such as mobile phone, tablet personal computer, and now the energy consumption of array is straight
The electric quantity consumption for being reflected as battery is connect, improving battery life, extension battery life turns into the main purpose of optimization power consumption.Cause
This, considers that battery behavior has great importance in optimized algorithm.
For most of application programs, circulation is main computation-intensive computing.Many Array Mapping methods of forefathers
Concentrate on cyclic mapping.For cyclic mapping, two kinds of mapped modes of domain mapping and space reflection when being broadly divided into, selection is different
Mapped mode can bring different energy expenditures.For each pattern, cyclic mapping is divided into several subproblems：That is operator
Scheduling, place and route.
Existing cyclic mapping can substantially be divided into 4 kinds.
The first be using loop start interval (II) as Algorithm mapping measurement, by solving above-mentioned cyclic mapping
Problem come find minimum II.It is for second, as optimization aim, and to establish a cyclic mapping using total execution time (TET)
Model.The third be using the work area of programmable logic array (abbreviation FPGA) as influence performance a key factor.
4th kind is to divide to optimize power consumption with task scheduling by task.
However, the first and the second way are turned a blind eye to for the power consumption of array computation, therefore larger energy can be caused
Amount consumption.And the third and the 4th kind be although it is contemplated that the power problemses brought during array operation, and to being mapped on PEA
Task carries out optimised power consumption, but ignores influence of the characteristic circulated on Array Mapping to power consumption, it is impossible in cyclic mapping
Obtain preferable effect of optimization.
The content of the invention
The purpose of the present invention is intended at least solve one of above-mentioned technological deficiency.
Therefore, one aspect of the present invention provides a kind of battery power consumption optimization method based on reconfigurable arrays.
Another aspect of the present invention proposes a kind of battery power consumption optimization system based on reconfigurable arrays.
In view of this, the embodiment of one aspect of the present invention proposes a kind of battery power consumption optimization side based on reconfigurable arrays
Method, comprises the following steps：Segmentation step is merged, the behavioral trait of battery is mutually tied with the cyclic mapping on reconfigureable computing array
Close, and to after mapping circulation carry out circulation fusion and split with obtain it is multiple cut, the reconfigureable computing array include it is multiple
Many bit process units；Reconstruction step, to many bit process units of at least a portion of the multiple many bit process units
The reconstitution time Δ for obtaining reconstruction stage is reconstructed in functionCFG,PWith the average current I of reconstruction stageCFG,P；Data are loaded into storage
Step, is loaded into and stores in the enterprising row data of many bit process units of described at least a portion to the multiple cut after segmentation
To the loading time Δ in the stage of loadingLD,P, be loaded into the stage average current ILD,P, memory phase storage time IST,P, storage rank
The average current I of sectionST,P；Calculation procedure, according to the quantity of the synchronous many bit process units performed and corresponding described
Electric current and required operation time obtain the average current I of calculation stages needed for many bit process unitsEXE,PWith holding for calculation stages
Row time ΔEXE,P；Modeling optimization step, according to the reconstitution time Δ of the reconstruction stageCFG,P, the reconstruction stage is averaged
Electric current ICFG,P, the loading stage duration of ΔLD,P, the loading stage average current ILD,P, the memory phase
Duration IST,P, memory phase average current IST,P, calculation stages average current IEXE,PWith continuing for calculation stages
Time ΔEXE,PElectric quantity consumption model is obtained, is optimized with the power consumption to the battery.
Method according to embodiments of the present invention, by by the cyclic mapping knot of battery behavioral trait and reconfigureable computing array
Close, and carry out in mapping process circulation fusion and split with obtain it is multiple cut, regeneration electric quantity consumption model is to the work(of battery
Consumption is optimized, so as to effectively combine battery with the cyclic mapping of reconfigurable processor, improves the use of battery
In the life-span, optimize the combination property of battery.
In one embodiment of the invention, the power consumption to the battery is optimized as by adjusting the electricity
The parameter of consumption models is optimized with the power consumption to the battery.
In one embodiment of the invention, the electric quantity consumption model is represented by equation below, and the formula is：
Wherein, TCL consumes for total electricity, and I is the multiple sum cut, and P is array processing when each cutting mapping
Sum, F is Rakhmatov battery model functions, and f is clock frequency, tpFor the initial time of pth time array processing.
In one embodiment of the invention, the multiple size cut is carried out about in the fusion segmentation step
Beam, the constraint is represented by equation below：
Wherein, SiRepresent to cut for i-th produced, dj(size (PEA)) represents Reconfigurable Computation battle array in ascending order
J-th of factor of row size.
In one embodiment of the invention, it is the multiple by what is obtained under constraints in the fusion segmentation step
The loop body cut tiles on the reconfigureable computing array.
The embodiment of another aspect of the present invention proposes a kind of battery power consumption optimization system based on reconfigurable arrays, bag
Include：Fusion segmentation module, for the behavioral trait of battery to be combined with the cyclic mapping on reconfigureable computing array, and mapping
Circulation after penetrating carry out circulation fusion and split with obtain it is multiple cut, the reconfigureable computing array includes multiple many bit process
Unit；Reconstructed module, the function to many bit process units of at least a portion of the multiple many bit process units is weighed
Structure obtains the reconstitution time Δ of reconstruction stageCFG,PWith the average current I of reconstruction stageCFG,P；Data are loaded into memory module, to dividing
The multiple cut after cutting obtains being loaded into rank in the enterprising row data loading of many bit process units of described at least a portion and storage
The loading time Δ of sectionLD,P, be loaded into the stage average current ILD,P, memory phase storage time IST,P, memory phase is averaged
Electric current IST,P；Computing module, at the quantity and corresponding many bits of the synchronous many bit process units performed
Electric current and required operation time obtain the average current I of calculation stages needed for reason unitEXE,PWith the execution time of calculation stages
ΔEXE,P；Modeling optimization module, for the reconstitution time Δ according to the reconstruction stageCPG,P, the reconstruct average current
ICPG,P, the loading stage duration of ΔLD,P, the loading stage average current ILD,P, the memory phase holds
Continuous time IST,P, memory phase average current IST,P, calculation stages average current IEXE,PWith the execution time of calculation stages
ΔEXE,PElectric quantity consumption model is obtained, is optimized with the power consumption to the battery.
System according to embodiments of the present invention, by the mapping method that battery behavioral trait is merged to segmentation with proposing circulation
Correspondence, regeneration electric quantity consumption model is optimized to the power consumption of battery, so that effectively by battery and reconfigurable processor
Cyclic mapping combines, and improves the service life of battery, optimizes the combination property of battery.
In one embodiment of the invention, the modeling optimization module is by adjusting the parameter of the electric quantity consumption model
Power consumption to the battery is optimized.
In one embodiment of the invention, the electric quantity consumption model is represented by equation below, and the formula is：
Wherein, TCL consumes for total electricity, and I is the multiple sum cut, and P is array processing when each cutting mapping
Sum, F is Rakhmatov battery model functions, and f is clock frequency, tpFor the initial time of pth time array processing.
In one embodiment of the invention, the fusion segmentation module is additionally operable to carry out about the multiple size cut
Beam, the constraint represented by equation below,
Wherein, SiRepresent to cut for i-th produced, dj(size (PEA)) represents Reconfigurable Computation battle array in ascending order
J-th of factor of row size.
In one embodiment of the invention, the fusion segmentation module the multiple is cut what is obtained under constraints
Loop body tiled on the reconfigureable computing array.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
Of the invention above-mentioned and/or additional aspect and advantage will become from the following description of the accompanying drawings of embodiments
Substantially and be readily appreciated that, wherein,
Fig. 1 is the flow chart of the battery power consumption optimization method proposed by the present invention based on reconfigurable arrays；
Fig. 2 is the executive mode schematic diagram of the reconfigureable computing array of one embodiment of the invention；
Fig. 3 is the schematic diagram converted according to polyhedron in one embodiment of the invention；
Fig. 4 is the iteration space and fusion schematic diagram after being converted according to the polyhedron of one embodiment of the invention；
Fig. 5 is the direct mapping graph of original loop according to one embodiment of the invention；
Fig. 6 is the Loop partitioning schematic diagram according to one embodiment of the invention；
Fig. 7 is to cut S according to one embodiment of the invention2Mapping graph；
Fig. 8 is to cut S according to one embodiment of the invention1Mapping graph；And
Fig. 9 is the structural frames for optimizing system according to the battery power consumption based on reconfigurable arrays of one embodiment of the invention
Figure.
Embodiment
Embodiments of the invention are described below in detail, the example of embodiment is shown in the drawings, wherein identical from beginning to end
Or similar label represents same or similar element or the element with same or like function.Retouched below with reference to accompanying drawing
The embodiment stated is exemplary, is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " on ", " under ",
The orientation or position relationship of the instruction such as "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer " are
Based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than indicate or dark
Specific orientation must be had, with specific azimuth configuration and operation by showing the device or element of meaning, therefore it is not intended that right
The limitation of the present invention.In addition, term " first ", " second " are only used for describing purpose, and it is not intended that indicating or implying and be relative
Importance.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected to by intermediary, Ke Yishi
The connection of two element internals.For the ordinary skill in the art, with concrete condition above-mentioned term can be understood at this
Concrete meaning in invention.
Fig. 1 is the flow chart of the battery power consumption optimization method proposed by the present invention based on reconfigurable arrays.As shown in figure 1,
Battery power consumption optimization method based on reconfigurable arrays according to embodiments of the present invention comprises the following steps：The behavior of battery is special
Property be combined with the cyclic mapping on reconfigureable computing array, and circulation fusion is carried out to the circulation after mapping and split to obtain
Multiple to cut, reconfigureable computing array includes multiple many bit process units (step 101).To multiple many bit process units extremely
The reconstitution time Δ for obtaining reconstruction stage is reconstructed in the function of few a part of many bit process unitsCFG,PWith putting down for reconstruction stage
Equal electric current ICFG,P(step 103).Multiple cut after segmentation is loaded into the enterprising row data of many bit process units of at least a portion
The loading time Δ in loading stage is obtained with storageLD,P, be loaded into the stage average current ILD,P, memory phase storage time
IST,P, memory phase average current IST,P(step 105).According to the quantity of the synchronous many bit process units performed and correspondingly
Many bit process units needed for electric current and required operation time obtain the average current I of calculation stagesEXE,PWith calculation stages
Execution time ΔEXE,P(step 107).According to the reconstitution time Δ of reconstruction stageCPG,P, reconstruction stage average current ICPG,P, carry
Enter the duration of Δ in stageLD,P, be loaded into the stage average current ILD,P, memory phase duration IST,P, memory phase
Average current IST,P, calculation stages average current IEXE,PWith the execution time Δ of calculation stagesEXE,PElectric quantity consumption model is obtained,
Optimized (step 109) with the power consumption to battery.
Method according to embodiments of the present invention, battery behavioral trait is combined with the cyclic mapping of reconfigureable computing array,
And circulation fusion and segmentation are carried out in mapping process, regeneration electric quantity consumption model is optimized to the power consumption of battery, so that
Effectively battery is combined with the cyclic mapping of reconfigurable processor, the service life of battery is improved, optimizes battery
Combination property.
In one embodiment of the invention, battery is used as the main energy sources of mobile platform, the electrochemistry of its own
Effect need to be taken into account.The present invention uses Rakhmatov battery models, and the model considers the nonlinear effect of battery, that is, compared
Example capacity effect and electricity recovery Effects, and only 2% error rate.The specific of the battery model is represented by：Wherein, to represent that tasks carrying is consumed total by σ
Electricity, k represents the number of discharge regime, and β represents the nonlinear effect of battery, and Δ, I and t represent discharge cycle number respectively, electric discharge
Average current and discharge regime initial time (for the battery of determination), m are Laplace transform coefficient, and T performs the cycle to be total
Number.During cyclic mapping, each time a stage of array processing be considered as the implementation procedure of a discharge regime, this
(Δ, I t) also correspond to the periodicity in the stage, average current and initial time to sample.It therefore, it can reflect by the circulation of proposition
Shooting method obtains these parameters, and Analytical Expression is carried out to the electric quantity consumption of array implementation procedure.According to the fortune of reconfigurable arrays
Row mechanism, the Array Mapping process entirely circulated is made up of a series of array processings, therefore we are needed to each array
Each stage of operation carries out Analytical Expression, specific as follows.
It is an object of the invention to reduce the consumption of gross energy by setting up the model of battery power consumption, it is therefore desirable to according to
The energy that the behavioral trait of battery is consumed to program is modeled.Then the present invention is carried out to the executive mode of reconfigurable arrays
Analysis, then correctly expresses using the electric quantity consumption of battery the energy consumption produced by each stage, it is possible thereby to right on this basis
The method of cyclic mapping is rationally instructed, and it is optimal effect in terms of power consumption.
The execution of reconfigureable computing array is made up of array processing several times.In fact, for certain array processing, array
Implementation procedure is generally divided into four-stage：Reconstruction stage, data are loaded into stage, array computation stage and phase data memory.
Fig. 2 is the executive mode schematic diagram of the reconfigureable computing array of one embodiment of the invention.As shown in Fig. 2 abscissa is the time,
Ordinate is Δ in electric current, Fig. 2CFG,p, ΔLD,p, ΔEXE,pAnd ΔST,pThe reconstruction stage of pth time array processing, number are represented respectively
According to the stage of loading, array computation stage and phase data memory.The array process performing of the four-stage is as follows：(1) reconstruct
Stage：Array reads configuration information come mutual between each PE and PE in configuring array inside configuration memory first
Connection form, that is, form the data path with certain function after configuring on array.(2) data are loaded into the stage：Array from
Calculative data are read in local memory and the input register of data distribution to the PE for needing to be loaded into the data.
(3) the array computation stage：Array is calculated according to configured good data path.(4) phase data memory：Array is by data
The data result that path is calculated is write back to inside local memory.It is to complete once battle array by performing an aforementioned four stage
Row operation, and for some array processings, PE functions and Join Shape in its last array processing all with this
As secondary operation, then this array processing avoids the need for carrying out the reconstruct of array, and is directly entered data loading, array computation
With these three stages (the pth time array processing in such as Fig. 2) of data output.The special operating mechanism of reconfigurable processor and place
Reason device and GPU are very different.
For certain array processing, the average current in each stage is changed due to the difference of array behavior.In Fig. 2
In, the average current in each stage is represented sequentially as ICFG,p, ILD,p, IEXE,pAnd IST,p.Wherein, reconstruction stage, data are loaded into
Stage and phase data memory are storage operation, and electric current is larger.Different cyclic mapping modes affects PEA execution side
Formula, also influences the size of its corresponding average current.For macroscopic perspective, cyclic mapping mode affects PEA electric current point
Cloth.
The present invention is further described below.
It is corresponding to reduce by space reflection pattern to reduce many reconstitution times in one embodiment of the present of invention
Energy expenditure.The battery behavior characteristics procedure for needing to be mapped is rewritten as DFD (abbreviation DFG), then should
DFG is mapped on reconfigurable arrays.Polyhedral model can be used at this makes it meet simultaneously to change the direction of the dependence of some in DFG
Capable legitimacy, to reach the effect for improving degree of parallelism.When entering line translation, it is contemplated that composite factor mainly two layers is circulated into
Row processing, for multilayer nest circulation, can choose two layers of circulation for being best suitable for handling and be handled, now by the two of conversion
Layer hyperplane (two one-dimensional affine transformations) is set to Θ and ∏.It is common for the original iteration domain of two layers of circulation
For rectangle iteration domain.Fig. 3 is the schematic diagram converted according to polyhedron in one embodiment of the invention.As shown in figure 3, by circulation
Conversion, rectangle iteration domain is changed into parallelogram iteration domain.
In the example of the present invention, the placement location and raising PE utilization rates relied on by changing, enabling change
Become CURRENT DISTRIBUTION during PEA operations, reduce energy expenditure.Specifically, for most of circulations, there is example between loop body
Various dependences as shown in Figure 4.For less loop body, in traditional mapping method between loop body
Many rely on is placed on local memory rather than array, so as to bring larger power consumption.In contrast to this, it is of the present invention because
X × x original loop bodies are merged and form an equivalent cycle body by this, and x is dependence between loop body to be dealt with
Maximum length (number for the circulation crossed over).
Because the equivalent cycle body is general bigger than PEA size, it would be desirable to which the equivalent cycle body is split.In entirety
Improved on the basis of kernel division methods (IKP), i.e., we increase constraint in terms of each size cut.IKP will be to be split
Loop body be divided into several and cut (cut), the constraint is represented by equation below：
Wherein, SiRepresent to cut for i-th produced, represent djJ-th of factor of the PEA sizes of (size (PEA)) in ascending order.Pass through
The constraint can ensure SiSize is identical as far as possible with some factor of PEA sizes so that mapping SiShi Tigao PE utilization rates
(UR), PE utilization rates (UR) are defined as hereWherein, WpeaAnd LpeaRespectively PEA
Width and length.The raising of PE utilization rates can generally make program execution time shorten and reduce the number of times of array processing so that
The storage operation number of times of array is tailed off, and energy expenditure is reduced with this, and in the case of identical temporal constraint, performs the time
Shorten and make it possible to obtain more free times, so that more electricity can be recovered using the recovery Effects of battery, increase battery
Endurance.
After Loop partitioning has been carried out, cutting for each generation is regarded as an independent subcycle body, and respectively to every
Individual cut carries out Array Mapping successively.Due to increased dimension constraint, cutting and (regarding subcycle as) for each generating can be put on PEA
Several, these subcycles are tiled on PEA, and draw final tiling number with reference to expansion coefficient, define PE's
Resource matrix (PRT).Using the circulation number accommodated on PEA as the size of the PRT, η × ξ is set to.Due to being followed in advance
The polyhedron conversion of ring so that the PRT having can be full of by loop iteration, be called R-PRT；Some PRT can not then be circulated
Iteration is full of, and is called I-PRT, as shown in Figure 3.
Place and route is carried out to the mapping cut generated with reference to the kernel mappings method (SPKM) pushed afterwards is first divided.
The main contents of SPKM methods are：First by the division to be dealt with circulated into determinant, so-called is solved in the process
With (matching-cut) problem is cut, (set on some sides for referring to no common node is cut in a matching, and removes these sides
So that figure is completely separable)；After division, routing processing unit (routing PE) is carried out for the row for being unsatisfactory for matching the problem of cutting
Insertion, comply with the requirement of wiring；The scattered of line is finally carried out, that is, is pushed.In order to improve concurrency, SPKM is also introduced into
One expansion coefficient is characterized while the loop body quantity performed., can be effectively in space reflection mould after SPKM methods
Good placement-and-routing's scheme is obtained under formula.
In reconstruction stage (step 103), for the CGRA of a certain determination, its reconstruct electric current determined by hardware and
It is a constant, is set to ICFG.For the array processing for needing reconstruction stage, reconstitution time is also a constant, is set to
ΔCFG.By introducing Boolean variable xpTo represent the array processing (x for needing to reconstructp=array processing (the x 1) reconstructed with needsp
=0).Simultaneously, it is contemplated that some CGRA can be hidden in hardware realization to reconstruction stage, therefore it is next to introduce Boolean variable ε
Distinguish the CGRA (ε=0) for hiding reconstruction stage.The duration in the stage and average current are represented by：ΔCFG, p=ε
xp·ΔCFG, ICFG, p=ICFG, wherein, ε is the Boolean variable for indicating whether to hide reconstruct.
It is loaded into data in stage and phase data memory (step 105), dependence length is regarded as to the function of the traffic, it is right
In hyperplane Θ and ∏, rely on length and be set to σe(Θ) and σe(∏).According to I-PRT and R-PRT difference, data are loaded into
Stage and the time of phase data memory are expressed as：
Wherein, BW is the bandwidth of the CGRA memories, γLDAnd γSTIt is Boolean type variable, represents I-PRT and R-PRT
Difference, η be PRT width, ξ be PRT length.
The loading electric current and storage electric current for transmitting a data are respectively a constant, and overall average electric current and the traffic have
Close, we use CVLDAnd CVSTTo simplify the traffic for representing loading stage and memory phase respectively, therefore the loading stage and deposit
The average current in storage stage is respectively：
In the array computation stage (step 107), the time that performs is the length of maximum critical path on PEA, is expressed as
maxeLep.Average current then (is set to n with the PE numbers performed in a certain control step simultaneouslypallel,p) and these PE operator
Scheduling is relevant.The number of assumption operator is num (op), IPE(opk) and tPE(opk) it is respectively that a PE performs k-th of operator institute
The electric current needed and time, then the average current of calculation stages is：
In electric quantity consumption model (step 109) is built, for simplified expression, by the expression formula of formula battery modelIt is reduced toThis
When, total electricity is consumed to (TCL) as the performance measure index of cyclic mapping, according to the analytical expression in above-mentioned each stage, followed
Electric quantity consumption model is represented by ring mapping process：
Wherein, TCL consumes for total electricity, and I is multiple sums cut, and P is the sum of array processing when each cutting mapping,
F is Rakhmatov battery model functions, and f is clock frequency, tpFor the initial time of pth time array processing.
The present invention is optimized by adjusting the parameter of electric quantity consumption model with the power consumption to battery.By TCL to proposing
Round-robin method be estimated, choose the coefficient correlation of optimal round-robin method, reach the purpose of extension service time of battery.
Method according to embodiments of the present invention, by by the cyclic mapping knot of battery behavioral trait and reconfigureable computing array
Close, and carry out in mapping process circulation fusion and split with obtain it is multiple cut, regeneration electric quantity consumption model is to the work(of battery
Consumption is optimized, so as to effectively combine battery with the cyclic mapping of reconfigurable processor, improves the use of battery
In the life-span, optimize the combination property of battery.
Fig. 9 is the structural frames for optimizing system according to the battery power consumption based on reconfigurable arrays of one embodiment of the invention
Figure.As shown in figure 9, the optimization of the battery power consumption based on reconfigurable arrays system according to embodiments of the present invention includes：Fusion segmentation
Module 100, reconstructed module 300, data are loaded into memory module 500, computing module 700 and modeling optimization module 900.
Specifically, fusion segmentation module 100, the circulation on the behavioral trait and reconfigureable computing array by battery is reflected
Penetrate and be combined, and to after mapping circulation carry out circulation fusion and split with obtain it is multiple cut, reconfigureable computing array include it is many
Individual many bit process units.Reconstructed module 300 is to many bit process units of at least a portion of multiple many bit process units
The reconstitution time Δ for obtaining reconstruction stage is reconstructed in functionCFG,PWith the average current I of reconstruction stageCFG,P.Data are loaded into storage
Multiple cut after 500 pairs of segmentations of module is loaded into the enterprising row data loading of many bit process units of at least a portion and storage
The loading time Δ in stageLD,P, be loaded into the stage average current ILD,P, memory phase storage time IST,P, memory phase it is flat
Equal electric current IST,P.The quantity and corresponding many bit process lists for many bit process units that computing module 700 is performed according to synchronization
Electric current and required operation time obtain the average current I of calculation stages needed for firstEXE,PWith the execution time Δ of calculation stagesEXE,P。
Modeling optimization module 900 is used for the reconstitution time Δ according to reconstruction stageCFG,P, reconstruct average current ICFG,P, be loaded into stage
Duration of ΔLD,P, be loaded into the stage average current ILD,P, memory phase duration IST,P, memory phase average current
IST,P, calculation stages average current IEXE,PWith the execution time Δ of calculation stagesEXE,PElectric quantity consumption model is obtained, with to battery
Power consumption optimize.
In one embodiment of the invention, electric quantity consumption model is represented by equation below, and formula is：
Wherein, TCL consumes for total electricity, and I is multiple sums cut, and P is the sum of array processing when each cutting mapping,
F is Rakhmatov battery model functions, and f is clock frequency, tpFor the initial time of pth time array processing.
In one embodiment of the invention, modeling optimization module 900 is by adjusting the parameter of electric quantity consumption model to electricity
The power consumption in pond is optimized.
In one embodiment of the invention, fusion segmentation module 100 is additionally operable to enter row constraint to multiple sizes cut, about
Beam represented by equation below,Wherein, SiRepresent to cut for i-th produced, dj
(size (PEA)) represents j-th of factor of reconfigureable computing array in ascending order.
System according to embodiments of the present invention, by the mapping method that battery behavioral trait is merged to segmentation with proposing circulation
Correspondence, regeneration electric quantity consumption model is optimized to the power consumption of battery, so that effectively by battery and reconfigurable processor
Cyclic mapping combines, and improves the service life of battery, optimizes the combination property of battery.
It should be noted that the function of multiple modules of the system of the present invention or the process step of structure and the above method and
Process is corresponding not to be repeated.
The present invention is further described below by embodiments of the invention.
Assuming that the Join Shape that the hardware configuration in Fig. 4 is row-based, the CGRA for being 4 × 4, and target circulation body are gathered around
There are 4 operators, therefrom select most interior two layers of circulation to be handled, the dependence between loop body is as shown in Figure 4.
First, contrasted using cyclic mapping method, for example, polyhedron is only used only and converts, obtained direct mapping knot
Really (as shown in Figure 5).Mapping method PE utilization rates in Fig. 5 are not high, and the dependence between the loop body shown in Fig. 4 can not be straight
Connect and be mapped on PEA and (need by memory).
The present invention first carries out the exploration of an algorithm.The hyperplane Θ and ∏ of two layers of circulation conversion coefficient difference will be handled
(c1, c2) and (d1, d2) are set to, then selects one group of initial value to carry out cyclical-transformation to it.After cyclical-transformation, between loop body
Dependence form is it has been determined that the dependence between every loop body is belonging respectively to dependence and the major class of dependence two of two interlayers of innermost layer.
Now, circulation is merged, then the loop body after fusion split using the IKP algorithms after improvement, and use PE
Utilization rate (UR) is characterized to segmentation effect.Afterwards, Operator Scheduling and placement-and-routing, shape are determined with circulation tiling and SPKM
TCL can be calculated into a feasible mapping scheme, and using electric quantity consumption model.By specifically souning out, find it is proposed that
One feasible program of method can be adjusted by (c1, c2, d1, d2, UR) these parameters, and these parameters influence last TCL size.
We need to build planning problem to solve and consider the constraint of restricted T CL optimization problems.First, it is contemplated that relying on legitimacy
Constraint, that is, rely on distance deltae(Θ) and σe(∏) should be greater than 0, wherein
Secondly, it is considered to perform the constraint of time, actual performs free time T of the time plus insertionidle(consider battery recovery effect
Should) it should be less than constraint Tset.In addition, total electricity consumption should be less than battery capacity α.Finally, compacting for guarantee transformation space
Property, it is considered to the unimodular constraint of (c1, c2, d1, d2).These constraint composition planning problem it is as follows, constraint by carry order
Arrangement.
The present invention optimizes solution using genetic algorithm to the formula.Genetic algorithm is studied and sent out by many forefathers
Exhibition, is proved to be a kind of method for effectively obtaining globally optimal solution.Using TCL inverse (1/TCL) as fitness function, become
Amount combination (c1, c2, d1, d2, UR) is used as chromosome., can be by one in (c1, c2, d1, d2) due to the presence that unimodular is constrained
Individual parameter other parameters, which are replaced, reduces variable number.Because for determining (c1, c2, d1, d2), improved IKP optimizes
The UR gone out is uniquely determined, therefore final chromosome variable number is reduced to three.By the genetic algorithm, obtain one group it is optimal
Solution, finally can determine the cyclical-transformation mode of an optimization.
Fig. 4, Fig. 6, Fig. 7 and Fig. 8 are the process schematic for the cyclic mapping mode for being followed successively by the optimization to the loop body.Through
Cross genetic algorithm and be determined one group of optimal (c1, c2, d1, d2, UR), now cyclical-transformation and Posterior circle fusion, segmentation
Mode also have determined that.The loop body of this in Fig. 4 through determination parameter cyclical-transformation converted after iteration domain, and according to
Dependence form has been fused into an equivalent cycle.In fig. 8, the IKP methods that the equivalent cycle is modified are divided into two to cut.So
Afterwards, we are cut using SPKM methods to each, and last mapping result is as shown in Fig. 8 and Fig. 7.Intuitively, our method
PE utilization rates are made to reach the 100% of Fig. 8 and Fig. 7 from the 50% of Fig. 5.Shown by the simulation result to different situations, in battery
Nonlinear effect β=0.574 under conditions of, our method in terms of electric quantity consumption to it is known the first, second of and
The third method averagely has 46.28%, 26.21% and 27.34% performance boost respectively.
Although embodiments of the invention have been shown and described above, it is to be understood that above-described embodiment is example
Property, it is impossible to limitation of the present invention is interpreted as, one of ordinary skill in the art is not departing from the principle and objective of the present invention
In the case of above-described embodiment can be changed within the scope of the invention, change, replace and modification.
Claims (8)
1. a kind of battery power consumption optimization method based on reconfigurable arrays, it is characterised in that comprise the following steps：
Segmentation step is merged, the behavioral trait of battery is combined with the cyclic mapping on reconfigureable computing array, and to mapping
Rear circulation carry out circulation fusion and split with obtain it is multiple cut, the reconfigureable computing array includes multiple many bit process lists
Member；
Reconstruction step, the function to many bit process units of at least a portion of the multiple many bit process units is reconstructed
Obtain the reconstitution time Δ of reconstruction stageCFG,PWith the average current I of reconstruction stageCFG,P；
Data are loaded into storing step, and the multiple cut after segmentation is carried out on many bit process units of described at least a portion
Data are loaded into and stored the loading time Δ for obtaining the loading stageLD,P, be loaded into the stage average current ILD,P, memory phase deposits
Storage time ΔST,P, memory phase average current IST,P；
Calculation procedure, according to the quantity and corresponding many bit process units of the synchronous many bit process units performed
Required electric current and required operation time obtain the average current I of calculation stagesEXE,PWith the execution time Δ of calculation stagesEXE,P；
Modeling optimization step, according to the reconstitution time Δ of the reconstruction stageCFG,P, the reconstruction stage average current ICFG,P、
The loading time Δ in the loading stageLD,P, the loading stage average current ILD,P, the memory phase storage time
ΔST,P, memory phase average current IST,P, calculation stages average current IEXE,PWith the execution time Δ of calculation stagesEXE,P
Electric quantity consumption model is obtained, is optimized with the power consumption to the battery；
The electric quantity consumption model represents that the formula is by equation below：
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Wherein, TCL consumes for total electricity, and I is the multiple sum cut, and P is the sum of array processing when each cutting mapping,
F is Rakhmatov battery model functions, and f is clock frequency, tpFor the initial time of pth time array processing.
2. the battery power consumption optimization method as claimed in claim 1 based on reconfigurable arrays, it is characterised in that described to described
The power consumption of battery optimizes to optimize with the power consumption to the battery by the parameter for adjusting the electric quantity consumption model.
3. the battery power consumption optimization method as claimed in claim 1 based on reconfigurable arrays, it is characterised in that in the fusion
Row constraint is entered to the multiple size cut in segmentation step, the constraint is represented by equation below,
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Wherein, SiRepresent to cut for i-th produced, dj(size (PEA)) represents the reconfigureable computing array chi in ascending order
J-th very little of factor, PEA is reconfigureable computing array.
4. the battery power consumption optimization method as claimed in claim 3 based on reconfigurable arrays, it is characterised in that in the fusion
Segmentation step tiles the multiple loop body cut obtained under constraints on the reconfigureable computing array.
5. a kind of battery power consumption optimization system based on reconfigurable arrays, it is characterised in that including：
Fusion segmentation module, for the behavioral trait of battery to be combined with the cyclic mapping on reconfigureable computing array, and it is right
Circulation after mapping carry out circulation fusion and split with obtain it is multiple cut, the reconfigureable computing array is included at multiple many bits
Manage unit；
Reconstructed module, the function to many bit process units of at least a portion of the multiple many bit process units is reconstructed
Obtain the reconstitution time Δ of reconstruction stageCFG,PWith the average current I of reconstruction stageCFG,P；
Data are loaded into memory module, and the multiple cut after segmentation is carried out on many bit process units of described at least a portion
Data are loaded into and stored the loading time Δ for obtaining the loading stageLD,P, be loaded into the stage average current ILD,P, memory phase deposits
Storage time ΔST,P, memory phase average current IST,P；
Computing module, according to the quantity and corresponding many bit process units of the synchronous many bit process units performed
Required electric current and required operation time obtain the average current I of calculation stagesEXE,PWith the execution time Δ of calculation stagesEXE,P；
Modeling optimization module, for the reconstitution time Δ according to the reconstruction stageCFG,P, the reconstruct average current ICFG,P、
The loading time Δ in the loading stageLD,P, the loading stage average current ILD,P, the memory phase storage time
ΔST,P, memory phase average current IST,P, calculation stages average current IEXE,PWith the execution time Δ of calculation stagesEXE,P
Electric quantity consumption model is obtained, is optimized with the power consumption to the battery；
The electric quantity consumption model represents that the formula is by equation below：
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</mfenced>
Wherein, TCL consumes for total electricity, and I is the multiple sum cut, and P is the sum of array processing when each cutting mapping,
F is Rakhmatov battery model functions, and f is clock frequency, tpFor the initial time of pth time array processing.
6. the battery power consumption based on reconfigurable arrays optimizes system as claimed in claim 5, it is characterised in that the modeling is excellent
Change module to optimize the power consumption of the battery by adjusting the parameter of the electric quantity consumption model.
7. the battery power consumption based on reconfigurable arrays optimizes system as claimed in claim 5, it is characterised in that the fusion point
Cut module to be additionally operable to enter row constraint to the multiple size cut, the constraint is represented by equation below,
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Wherein, SiRepresent to cut for i-th produced, dj(size (PEA)) represents the reconfigureable computing array chi in ascending order
J-th very little of factor, PEA is reconfigureable computing array.
8. the battery power consumption based on reconfigurable arrays optimizes system as claimed in claim 7, it is characterised in that the fusion point
Cut module the multiple loop body cut obtained under constraints tiles on the reconfigureable computing array.
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| CN201410412289.8A CN104182578B (en) | 2014-08-20 | 2014-08-20 | Battery power consumption optimization method and system based on reconfigurable arrays |
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| CN201410412289.8A CN104182578B (en) | 2014-08-20 | 2014-08-20 | Battery power consumption optimization method and system based on reconfigurable arrays |
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| CN102129495A (en) * | 2011-03-07 | 2011-07-20 | 北京大学深圳研究生院 | Method for reducing power consumption of reconfigurable operator array structure |
| CN102509036A (en) * | 2011-09-28 | 2012-06-20 | 东南大学 | Reconfigurable cipher processor and anti-power consumption attach method |
| CN103096445A (en) * | 2013-02-05 | 2013-05-08 | 清华大学 | Method and system of wireless sensor network task scheduling based on actual battery model |
| CN103218347A (en) * | 2013-04-28 | 2013-07-24 | 清华大学 | Multiparameter fusion performance modeling method for reconfigurable array |
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| CN102129495A (en) * | 2011-03-07 | 2011-07-20 | 北京大学深圳研究生院 | Method for reducing power consumption of reconfigurable operator array structure |
| CN102509036A (en) * | 2011-09-28 | 2012-06-20 | 东南大学 | Reconfigurable cipher processor and anti-power consumption attach method |
| CN103096445A (en) * | 2013-02-05 | 2013-05-08 | 清华大学 | Method and system of wireless sensor network task scheduling based on actual battery model |
| CN103218347A (en) * | 2013-04-28 | 2013-07-24 | 清华大学 | Multiparameter fusion performance modeling method for reconfigurable array |
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