CN104168705A - LED driver without electrolytic capacitor - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to an LED driver without an electrolytic capacitor. The LED driver without the electrolytic capacitor comprises a rectification bridge, a reference voltage generation module, a drive module, an LED, a power tube, an operational amplifier, an analog multiplier, a current amplifier, a zero-cross detection device (ZCD), an MOS tube, a resistor and the like. A circuit in the driver works in an inductance and current critical conduction mode, power factor correction is automatically achieved, the peak value of input power is lowered through a harmonic component, a capacitance element with a small capacity value can be used, and accordingly use of the high-capacity electrolytic capacitor is avoided. Meanwhile, by means of a method for transiently responding to an enhanced network, load transient response speed is very high, interference resistance is enhanced, the load adjustment rate is high, and meanwhile output voltage can be stabilized without the high-capacity electrolytic capacitor.

Description

LED driver without electrolytic capacitor

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to an LED driver without electrolytic capacitors.

Background

The service life of the current LED driving power supply mainly depends on a large-capacity electrolytic capacitor in a circuit. The service life of the electrolytic capacitor is only thousands of hours generally, the service life of the LED can reach tens of thousands of hours, and the service life of the electrolytic LED is seriously mismatched, so the service life of the LED driving power supply is influenced. On the other hand, the electrolytic capacitor is bulky, which results in a bulky LED driving device without using miniaturization. For some applications, the volume is too large to facilitate installation.

Disclosure of Invention

The invention aims to solve the problems of electrolytic capacitors in the existing LED driver and provides an LED driver without the electrolytic capacitors.

The technical scheme of the invention is as follows: as shown in fig. 2, an LED driver without electrolytic capacitor includes a rectifier bridge, a reference voltage generating module, a driving module, an LED module, a switching transistor Q1, a PMOS transistor PM1, an NMOS transistor MN1, a first operational amplifier, a second operational amplifier, a third operational amplifier, a first error operational amplifier, a second error operational amplifier, a first multiplier, a second multiplier, a third multiplier, an RS flip-flop, a current amplifier, a zero-cross detection module ZCD, a resistor R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, a capacitor C1, C2, C3, C4, C5, a diode D5, and an inductor L; wherein,

the input end of the rectifier bridge is connected with an external alternating current power supply, and the output end of the rectifier bridge is connected with the anode of a diode D5 through an inductor L; the connection point of the inductor L and the output end of the rectifier bridge is grounded after passing through R1 and R2 in sequence; the connection point of R1 and R2 is connected with the positive input end of the first operational amplifier; the inverting input end of the first operational amplifier is grounded after passing through R3 and R4 in sequence, the output end of the first operational amplifier is connected with the inverting input end of the first operational amplifier, and the output end of the first operational amplifier is also connected with the first input end of the first multiplier, the second input end of the first multiplier and the first input end of the second multiplier; the output end of the first multiplier is connected with the second input end of the second multiplier; the output end of the second multiplier is connected with the inverting input end of the second operational amplifier after passing through R5; the connection point of R3 and R4 is connected with the positive input end of the second operational amplifier after passing through R7; the connection point of the R7 and the positive input end of the second operational amplifier is grounded after passing through the R8; the inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier through the R6, and the output end of the second operational amplifier is connected with the first input end of the third multiplier; the second input end of the third multiplier is connected with the output end of the first error operational amplifier; the reverse input end of the first error operational amplifier is connected with the output end of the reference voltage generating module, the positive input end of the first error operational amplifier is connected with the cathode of the diode D5 after passing through R11, the connection point of the positive input end of the first error operational amplifier and R11 is connected with the ground after passing through R12, and the output end of the first error operational amplifier is connected with the positive input end of the first error operational amplifier after passing through C1; the second input end of the third multiplier is connected with the positive input end of the first error amplifier after passing through C2 and R9 in sequence; the output end of the third multiplier is connected with the reverse input end of the third operational amplifier; the positive input end of the third operational amplifier is connected with the source electrode of the switching tube Q1, and the output end of the third operational amplifier is connected with the R input end of the RS trigger; the S output end of the RS trigger is connected with the zero-crossing detection module ZCD, and the Q output end of the RS trigger is connected with the input end of the driving module; the output end of the driving module is connected with the grid electrode of the switching tube Q1; the drain electrode of the switching tube Q1 is connected with the connection point of the inductor L and the anode of the diode D5, and the connection point of the source electrode of the switching tube Q1 and the positive input end of the third operational amplifier is grounded after passing through R10; the cathode of the diode D5 is connected with the source electrode of the PMOS tube PM 1; the connection point of the cathode of the diode D5 and the source electrode of the PMOS tube PM1 is grounded after passing through C3; the grid electrode of the PMOS tube PM1 is connected with the output end of the second error operational amplifier and the drain electrode of the NMOS tube MN1, and the drain electrode of the PMOS tube PM1 is connected with the LED module; the reverse input end of the second error operational amplifier is connected with the output end of the reference voltage module, and the forward input end of the second error operational amplifier is connected with the drain electrode of the PMOS tube PM1 through R14; the connection point of the R14 and the positive input end of the second error operational amplifier is grounded after passing through the R15; the source electrode of the NMOS tube MN1 is grounded, and the grid electrode of the NMOS tube MN1 is connected with the output end of the current amplifier; the current amplifier is connected with the R13 in parallel, and the input end of the current amplifier is connected with the drain electrode of the PMOS transistor PM1 after passing through the C4; c5 is connected in parallel with the LED module.

The invention has the advantages that the invention does not use electrolytic capacitors with large capacity, can improve the reliability and the service life of the power supply, can carry out automatic power factor adjustment, and has the advantages of high load transient response speed, strong anti-jamming capability and high load adjustment rate.

Drawings

FIG. 1 is a diagram of input and output waveforms at a power factor of 1;

FIG. 2 is a circuit configuration diagram of embodiment 1;

FIG. 3 is a waveform of parameters in example 1;

fig. 4 is a structural view of embodiment 2.

Detailed Description

The invention is described in detail below with reference to the figures and examples

Fig. 1 shows waveforms of input voltage, input current, input power, and output power when PF is 1, and it can be known from the diagrams that the input power is pulsating and the output power is constant. A large capacitance is required to balance the input power and the output power.

Example 1

As shown in fig. 2, the present embodiment includes a rectifier bridge, a reference voltage generating module, a driving module, an LED, a power tube, an operational amplifier, an analog multiplier, a current amplifier, an inductor, a zero-crossing detecting module ZCD, an MOS tube, a resistor, and the like.

Specifically, the ac input Vin is connected to the inductor L through the rectifier bridge, and is connected to GND through the resistors R1 and R2. The other end of the inductor L is connected to the drain terminal of the switching tube Q1 and the non-inverting terminal of the diode D5, and the source of the switching tube Q1 is connected to GND through the resistor R10; the negative terminal of the diode D5 is connected to the capacitor C3, and the other terminal of the capacitor C3 is connected to GND. One end of the resistor R1 connected with the resistor R2 is connected to the non-inverting end of the operational amplifier 1, the negative end and the output end of the operational amplifier 1 are connected to the resistor R3, and then connected to GND through the resistor R4. The output end of the operational amplifier 1 is input to two ports of the multiplier 1 to realize squaring, the output end of the multiplier 1 and the operational amplifier 1 are respectively input to the input end of the multiplier 2, and the output end of the multiplier 2 is connected to the negative end of the operational amplifier 2 through R5; the connecting section of the resistors R3 and R4 is connected to the in-phase end of the operational amplifier 2 through R7, and the in-phase end of the operational amplifier 2 is connected to GND through R8. The negative end of the operational amplifier 2 is connected with the output end through a resistor R6; the output end of the operational amplifier 2 is input to the input end of the multiplier 3, and the other input end of the multiplier 3 is connected to the output end of the error amplifier 1; the output end of the multiplier 3 is connected to the negative end of the operational amplifier 3, the source electrode of the switching tube Q1 is connected to the in-phase end of the operational amplifier 3, the output of the operational amplifier 3 is connected to the R end of the RS trigger, and the S end of the RS trigger is connected to the inductor current zero-crossing detection circuit ZCD. The output end of the RS trigger is connected to a driving module, and the driving module drives the grid electrode of the switching tube Q1; the negative end of the diode is connected to GND through a resistor R11 and a resistor R12. The junction of the resistor R11 and the resistor R12 is connected to the in-phase end of the error amplifier 1, and the inverting end of the error amplifier 1 is connected to the reference voltage VREF; the non-inverting terminal of the error amplifier is connected to the output terminal of the error amplifier through a capacitor C1, and a resistor R9 is connected in series with the capacitor C2 and then connected in parallel across the capacitor C1. The negative end of the diode is connected to the source electrode of the PMOS tube PM1, the drain electrode of the PMOS tube PM1 is connected to the capacitor C4, the capacitor C4 is input to the input end of the current amplifier CA, the resistor R13 is in bridge connection with the input end and the output end of the current amplifier CA, the output end of the current amplifier CA is connected to the grid electrode of the NMOS tube NM1, and the source electrode of the NM1 is connected to GND. The drain of the NM1 is connected to the gate of the PMOS transistor PM1, the drain of the PMOS transistor PM1 is connected to GND through a resistor R14 and a resistor R15, the junction of the resistor R14 and the resistor R15 is connected to the non-inverting input terminal of the error amplifier 2, and the negative input terminal of the error amplifier 2 is connected to the reference voltage VREF. The drain terminal of PM1 is connected to capacitor C5, and the other terminal of C5 is connected to GND. The drain terminal of the PM1 is connected with the positive terminal of the LED1, the negative terminal of the LED1 is connected with the in-phase terminal of the LED2, the LED1 and the LED2 … LEDN are sequentially connected, and the reverse terminal of the LEDN is connected to GND. The reference voltage module provides a reference voltage VREF for the circuit.

The working principle of the embodiment is as follows:

the resistors R1, R2, R3, R4, R5, R6, R7, R8, R9 and R10, the operational amplifier 1, the operational amplifier 2, the operational amplifier 3, the multiplier 1, the multiplier 2, the multiplier 3, the RS trigger, the error amplifier 1, the capacitors C1, C2 and C3, the diodes D1, D2, D3, D4 and D5, the inductor L and other circuits form a power factor corrector, and the capacity of an output energy storage capacitor can be reduced by properly reducing the input power factor. And by a harmonic injection method, the input power factor is reduced, and the capacity of the output energy storage capacitor is further reduced. When the content of the injected third harmonic is 48.4 percent of the fundamental wave and the input power factor is 0.9, the requirements of different countries on the power factor are met, and the capacity of the output capacitor is reduced to 65.6 percent of the original capacity.

In the attached drawings

v_a＝V_in*k_a*|sinωt|

v_b＝V_in*k_b*|sinωt|

$k_a=\frac{R2}{R1+R2}*\frac{R4}{R3+R4}$

$k_b=\frac{R2}{R1+R2}$

Wherein V_inIs the amplitude of the input voltage, k_a,、k_bIs a scaling factor. v. of_aIs the output voltage, v, of the operational amplifier 1_bVoltage v is divided into points by resistors R3 and R4_aThus, the compound was obtained.

v_aV is obtained after two times of multiplication_a ³The resistors R5, R6, R7, R8 and the operational amplifier 2 form a subtractor, wherein R5-R6-R7-R8 is removed, and the output of the subtractor is finally obtained

v_r＝V_ink_b*|sinωt|-V_in ³k_a ³*|sinωt|³

Output v of the subtractor_rContaining the third harmonic wave, v_rAnd multiplying the output signal of the output voltage error amplifier, taking the product as the reference of a switch-off signal of the switching tube, and turning on the switch when the inductive current is detected to be reduced to zero so as to realize that the inductor works in an inductive current critical conduction working mode. Guarantee k_b:(V_in ²*k_a ³) 2.45:1.94, then v_rThe amplitude of the medium third harmonic is 48.4% of the amplitude of the fundamental wave. The main waveforms of the harmonic injection circuit are shown in the attached figure two:

the capacitor C4, the current amplifier CA, the NMOS transistor MN1 and the resistors 13 form a transient response enhancement network. The capacitor C4 mainly has the function of converting the variable quantity of the output voltage into current, converting the current into voltage through the formed trans-impedance amplifier and then converting the voltage into the current through NM1, so that the current is input to the grid of the power adjusting tube after passing through the amplifier to charge the grid capacitor, the transient response is quick, the output voltage is smooth without a large electrolytic capacitor, and the output voltage can be stabilized only by a ceramic capacitor or a thin-film capacitor with a small capacitance value.

As shown in fig. 3, the waveform of the circuit parameter in the embodiment 1 shows that the voltage in Vc already contains the third harmonic component.

As shown in fig. 4, which is a schematic structural diagram of embodiment 2, in embodiment 1, the output is a constant voltage. In some cases, constant current driving is required for the LED. This embodiment 2 is given. In this example, the LED driver may drive the LED with a constant current pair having

I_LED＝VREF/R13

The invention provides two embodiments, the first is constant voltage output, the second is constant current output, and the capacitors in the two embodiments are ceramic capacitors or film capacitors, so that large-capacity electrolytic capacitors are not needed.

In summary, the present invention provides an LED driver without electrolytic capacitor, which includes a rectifier bridge, a reference voltage generating module, a driving module, an LED, a power tube, an operational amplifier, an analog multiplier, a current amplifier, a zero-crossing detecting module ZCD, an MOS transistor, and a resistor. The circuit works in an inductive current critical conduction mode, automatically realizes power factor correction, utilizes harmonic components to reduce the peak value of input power, can use a capacitor element with a smaller capacitance value to avoid using a large-capacity electrolytic capacitor, and simultaneously utilizes a method of a transient response enhancement network to ensure that the load transient response speed is very high, the anti-interference capability is enhanced, the load regulation rate is very high, and the use of a large-capacity electrolytic capacitor to stabilize output voltage can also be avoided. The failure of the electrolytic capacitor with large capacity is an important cause of the failure rate of the power supply, so the invention has the greatest benefit of improving the reliability and the service life of the power supply.

Claims (1)

1. An LED driver without electrolytic capacitor is characterized by comprising a rectifier bridge, a reference voltage generation module, a driving module, an LED module, a switching tube Q1, a PMOS tube PM1, an NMOS tube MN1, a first operational amplifier, a second operational amplifier, a third operational amplifier, a first error operational amplifier, a second error operational amplifier, a first multiplier, a second multiplier, a third multiplier, an RS trigger, a current amplifier, a zero-crossing detection module ZCD, a resistor R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, a capacitor C1, C2, C3, C4, C5, a diode D5 and an inductor L; wherein,

the input end of the rectifier bridge is connected with an external alternating current power supply, and the output end of the rectifier bridge is connected with the anode of a diode D5 through an inductor L; the connection point of the inductor L and the output end of the rectifier bridge is grounded after passing through R1 and R2 in sequence; the connection point of R1 and R2 is connected with the positive input end of the first operational amplifier; the inverting input end of the first operational amplifier is grounded after passing through R3 and R4 in sequence, the output end of the first operational amplifier is connected with the inverting input end of the first operational amplifier, and the output end of the first operational amplifier is also connected with the first input end of the first multiplier, the second input end of the first multiplier and the first input end of the second multiplier; the output end of the first multiplier is connected with the second input end of the second multiplier; the output end of the second multiplier is connected with the inverting input end of the second operational amplifier after passing through R5; the connection point of R3 and R4 is connected with the positive input end of the second operational amplifier after passing through R7; the connection point of the R7 and the positive input end of the second operational amplifier is grounded after passing through the R8; the inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier through the R6, and the output end of the second operational amplifier is connected with the first input end of the third multiplier; the second input end of the third multiplier is connected with the output end of the first error operational amplifier; the reverse input end of the first error operational amplifier is connected with the output end of the reference voltage generating module, the positive input end of the first error operational amplifier is connected with the cathode of the diode D5 after passing through R11, the connection point of the positive input end of the first error operational amplifier and R11 is connected with the ground after passing through R12, and the output end of the first error operational amplifier is connected with the positive input end of the first error operational amplifier after passing through C1; the second input end of the third multiplier is connected with the positive input end of the first error amplifier after passing through C2 and R9 in sequence; the output end of the third multiplier is connected with the reverse input end of the third operational amplifier; the positive input end of the third operational amplifier is connected with the source electrode of the switching tube Q1, and the output end of the third operational amplifier is connected with the R input end of the RS trigger; the S output end of the RS trigger is connected with the zero-crossing detection module ZCD, and the Q output end of the RS trigger is connected with the input end of the driving module; the output end of the driving module is connected with the grid electrode of the switching tube Q1; the drain electrode of the switching tube Q1 is connected with the connection point of the inductor L and the anode of the diode D5, and the connection point of the source electrode of the switching tube Q1 and the positive input end of the third operational amplifier is grounded after passing through R10; the cathode of the diode D5 is connected with the source electrode of the PMOS tube PM 1; the connection point of the cathode of the diode D5 and the source electrode of the PMOS tube PM1 is grounded after passing through C3; the grid electrode of the PMOS tube PM1 is connected with the output end of the second error operational amplifier and the drain electrode of the NMOS tube MN1, and the drain electrode of the PMOS tube PM1 is connected with the LED module; the reverse input end of the second error operational amplifier is connected with the output end of the reference voltage module, and the forward input end of the second error operational amplifier is connected with the drain electrode of the PMOS tube PM1 through R14; the connection point of the R14 and the positive input end of the second error operational amplifier is grounded after passing through the R15; the source electrode of the NMOS tube MN1 is grounded, and the grid electrode of the NMOS tube MN1 is connected with the output end of the current amplifier; the current amplifier is connected with the R13 in parallel, and the input end of the current amplifier is connected with the drain electrode of the PMOS transistor PM1 after passing through the C4; c5 is connected in parallel with the LED module.