CN104166631B - The replacement method of Cache rows in LLC - Google Patents
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- CN104166631B CN104166631B CN201410462286.5A CN201410462286A CN104166631B CN 104166631 B CN104166631 B CN 104166631B CN 201410462286 A CN201410462286 A CN 201410462286A CN 104166631 B CN104166631 B CN 104166631B
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Abstract
The invention provides a kind of replacement method of Cache rows in LLC, if target Cache addresses are lacked in LLC, the new replacement priority for calling in Cache rows is calculated according to action type, according to the replacement orderly principle of priority, the original Cache rows for replacing highest priority are replaced, and the correspondence position that will newly call in Cache rows deposit target Cache；If target Cache is hit address in LLC, according to Cache coherency states and action type, the replacement priority of current accessed Cache rows is updated, according to the replacement orderly principle of priority, the promotion and demotion to current accessed Cache travelings row major level.Can effectively reduce comprising in Cache replace introduce include victim caused by performance loss.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of afterbody cache memory (LLC, Last
Level Cache) in Cache rows replacement method.
Background technology
In order to fill up the performance difference of processor and storage system, modern processors are usually using multi-layer C ache structures.Its
In, a kind of important design is comprising the design of Cache (Inclusive Cache) hierarchical structure.In Inclusive
In Cache hierarchical structures, the upper strata Cache of close processor core Cache rows are equal in the lower floor Cache away from processor core
With copy, and the Cache rows in lower floor Cache then not necessarily have copy in the Cache of upper strata, and this structure can simplify
Cache coherence protocol.But, with it is non-include and mutual exclusion Cache structures compared with, may meet with performance loss comprising Cache.One
Aspect, because the repetition of data is stored, effective Cache spaces are reduced；On the other hand, when a Cache row is replaced from LLC
When going out, in order to keep include attribute, must by its from the Cache of upper strata it is invalid, in current upper strata Cache in order to keep comprising category
Property and the Cache rows that are deactivated are commonly known as " including victim " (inclusive victims).Due to existing comprising victim
Conventional Cache rows may be belonged in the Cache of upper strata, therefore, too early ineffective treatment can cause extra access to lack, so as to reduce
Cache performances.
Traditional LLC replaces algorithm, for example the replacement of least recently used (LRU, Least Recently Used) in the recent period
In strategy, the Cache rows that the last time is accessed always are placed in Cache nearest most use (MRU, Most Resently
Used) OK, Cache LRU rows are then placed on apart from the Cache rows being currently farthest accessed.When carrying out LLC replacements, lead to
Often determined to replace candidate blocks according to nearest visiting frequency of the Cache rows in LLC, i.e., will always be replaced positioned at the LRU rows of correspondence group
Change, and the Cache rows newly added are placed at MRU, without considering its service condition in the Cache of upper strata.Therefore, replacement is worked as
When candidate blocks have good locality of reference in the Cache of upper strata, " including victim " in such replacement algorithm will lead
Cache performances are caused drastically to decline.
In addition, in on-chip multi-processor (CMP, Chip multiprocessors) system, each processor core has
Privately owned L1 data/commands Cache, multiple processor cores share a LLC.In system operation, multiple processor cores
The copy of a certain data block is may be simultaneously present in privately owned Cache, therefore, when to it is one of carry out write operation when, it is necessary to
Ensure the correctness of data by Cache coherence protocol.When carrying out LLC replacements, in order to ensure comprising attribute, it is necessary to will treat
Whole copies of the replacement data block in the Cache of upper strata are invalid.It is above-mentioned when the data block is often accessed in upper strata Cache
Invalid operation will greatly reduce Cache access performances.
In view of this, it is necessary to which a kind of improved LLC alternatives solve problem of the prior art.
The content of the invention
In order to solve the above-mentioned technical problem, can be effective the invention provides a kind of replacement method of Cache rows in LLC
Reduction includes performance loss caused by " including victim " that introducing is replaced in Cache.
In order to reach the object of the invention, the invention provides a kind of replacement method of Cache rows in LLC, including：If mesh
Mark Cache addresses are lacked in LLC, and the new replacement priority for calling in Cache rows is calculated according to action type, preferential according to replacing
The orderly principle of level, the Cache rows of highest priority are swapped out, and will newly call in Cache rows deposit target Cache corresponding position
Put；If target Cache is hit address in LLC, according to Cache coherency states and action type, current accessed is updated
The replacement priority of Cache rows, according to the replacement orderly principle of priority, the lifting to current accessed Cache travelings row major level
Level.
Further, the calculation of replacement priority P is：P=a1×c×op+k×a2+a3× (1-c) × op, its
In, a1Write operation weight is represented, whether c represents copy in the Cache of upper strata write-back, if write-back, c=0, otherwise, c=
1；Op represents to cause the action type of replacement, write operation correspondence op=1, otherwise op=0；K represents read-only copy amount, its value
Processor check figure no more than shared LLC；A2 represents read operation weight；A3 represents write back operations weight, wherein, P values are smaller, replace
Change priority higher, be preferentially replaced when replacing.
Further, action type includes read operation and write operation；If causing Cache rows in LLC to be replaced by read operation,
The new P=2*a2 called in Cache rows；If causing Cache rows in LLC to be replaced by write operation, the P newly called in Cache rows
=a1, wherein, a1 is more than 2*a2；If write-back occurs for upper strata Cache Cache rows, P=a3, wherein, a3 is less than 2*a2；
If there is a read-only copy in LLC in upper strata Cache Cache rows, P=a2, wherein, a3 is more than a2.
Further, replacing the orderly principle of priority is：Two Cache rows in same Cache, respectively by this two
The position of individual Cache rows is designated as i and j, and wherein i and j have magnitude relationship；If i is more than j, replaces priority P i and be more than Pj.
Further, according to the orderly principle of priority is replaced, the Cache rows of highest priority are swapped out, and will newly call in
Cache rows deposit target Cache correspondence position, including：If the new initial replacement priority for calling in Cache rows to be more than or
Equal to the Cache rows of a non-LRU position in target Cache groups, then by from the Cache rows of the non-LRU position to LRU bit
The Cache rows put move the distance of a Cache row to LRU directions successively, and originally the Cache rows positioned at LRU position are replaced,
And the Cache rows that will newly call in the Cache rows deposit non-LRU position.
Further, Cache coherency states are MESI, and the Cache rows in LLC have following shared state：M
State：Cache rows are existed only in LLC, without copy in the Cache of upper strata；SS states：Cache rows are present in LLC and upper strata Cache simultaneously
In, all data trnascriptions are readable state；MT states：Cache rows are simultaneously positioned at LLC and upper strata permitted in mutually exclusive operation
In Cache, and data in LLC may be modified in the Cache of upper strata；Cache rows in M states, which occur to replace, to be needed
Write-back LLC data；Cache rows in SS states are when replacing except needing, by addition to the data invalid in LLC, also to need lower floor
Read-only data copy in Cache is invalid；, need to be first by the data changed on upper strata when Cache rows in MT states are replaced
Write-back is then invalid by the data trnascription on the upper strata.
Further, it is described according to Cache coherency states and action type, update the replacement of current accessed Cache rows
Priority, according to the replacement orderly principle of priority, the promotion and demotion to current accessed Cache travelings row major level, including：According to
The change of the shared number of copies of Cache coherency states and the read/write operation situation of action type, update current accessed Cache
Capable replacement priority；If due to the change and the read/write operation of action type of the shared number of copies of Cache coherency states
Situation, replaces priority and changes, according to the orderly principle of priority is replaced, current accessed Cache rows are degraded or risen
Level.
Compared with prior art, the present invention includes：If target Cache addresses are lacked in LLC, according to action type meter
Newly priority must be replaced by calling in Cache rows for calculation, and according to the orderly principle of priority is replaced, the Cache rows of highest priority are swapped out,
And the correspondence position that will newly call in Cache rows deposit target Cache；If target Cache is hit address in LLC, basis
Cache coherency states and action type, update the replacement priority of current accessed Cache rows, and according to replacing, priority is orderly
Principle, the promotion and demotion to current accessed Cache travelings row major level.The coherency state of Cache row of the present invention in LLC
Information, Cache rows are weighted in the distribution of whole Cache levels and shared state, obtain the replacement of Cache rows
Priority.On the one hand, for the access lacked in LLC, the new initial replacement for calling in Cache rows is calculated according to action type preferential
Level, according to the orderly principle of priority is replaced, the Cache rows of highest priority are swapped out, and call in Cache rows deposit target by new
Cache correspondence position；On the other hand, for the access hit in LLC, according to Cache coherency states and action type
Update current accessed Cache rows and replace priority, according to the orderly principle of priority is replaced, carry out the liter of current accessed Cache rows
Degrade, so as to reduce the ineffective treatment of focus " including victim ", effectively improve Cache access performance.
Brief description of the drawings
Fig. 1 is the structural representation of multinuclear shared Cache processor of the present invention.
Fig. 2 is the schematic flow sheet of the replacement method of Cache rows in LLC of the present invention.
Fig. 3 is an instantiation schematic diagram of Cache rows replacement in LLC of the present invention.
Fig. 4 is another instantiation schematic diagram of Cache rows replacement in LLC of the present invention.
Fig. 5 is another instantiation schematic diagram of Cache rows replacement in LLC of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings.By description detailed enough, these implementations are shown
Example so that those skilled in the art can put into practice the present invention.Without departing from the spirit and scope in the present invention, can be right
Implement to make logic, realization and other changes.
Fig. 1 is the structural representation of multinuclear shared Cache processor of the present invention.As shown in figure 1, Cache processors have
Two-level cache, is upper strata Cache close to the L1 of processor core, and the LLC away from processor core is lower floor Cache.L1 is with LLC
The Cache rows of inclusion relation, i.e. L1 have copy in LLC, and LLC Cache rows then not necessarily have copy in L1,
The operation of Cache rows can not destroy the inclusion relation.In addition, L1 is that processor core is privately owned, instruction I and data D is discrete, and LLC is
All processor cores are shared.
Fig. 2 is the schematic flow sheet of the replacement method of Cache rows in LLC of the present invention, as shown in Fig. 2 can specifically include：
Step 21, target Cache groups are determined according to the reference address of current data.
Step 22, judge whether target Cache addresses hit in LLC, if hit, into step 28；If missing,
Into step 23.
In this step, whether comparison object Cache addresses match with the field of Cache tag tables in LLC, if
Match somebody with somebody, then hit；If it does not match, missing.
Step 23, judge to whether there is null in LLC, if it does, into step 24；If it does not, into step
25。
In this step, if there are one or more untapped Cache rows, LLC in LLC target Cache groups
In there is null.
Step 24, it will newly call in Cache rows to be put near in a null of MRU position, wherein MRU position is designated as into 0
Position.
Step 25, the Cache rows of LRU position of the selection in target Cache groups are as replacement candidate row, and if this is replaced
Change candidate row data to be modified, by the replacement candidate row write back data, wherein LRU position is designated as into W-1 positions, W is to be connected
Degree.
Step 26, according to action type, the new replacement priority for calling in Cache rows is calculated, the calculation is：
P=a1×c×op+k×a2+a3× (1-c) × op, (1)
Wherein, a1Write operation weight is represented, whether c represents copy in the Cache of upper strata write-back, if write-back, c=
0, otherwise, c=1；Op represents to cause the action type of replacement, write operation correspondence op=1, otherwise op=0；K represents read-only copy
Quantity, its value is no more than shared LLC processor check figure；A2 represents read operation weight；A3 represents write back operations weight；
Wherein, P values are smaller, and replacement priority is higher, is preferentially replaced when replacing.
In this step, action type includes read operation and write operation.
The maintenance of the replacement priority of Cache rows includes two stages in LLC：It is initial to replace priority and promotion and demotion.
According to the definition of formula (1), replace in priority：If causing LLC rows to be replaced by read operation, Cache rows are initial
When calling in, P=2*a2；If replaced caused by write operation, the initial replacement priority of Cache rows is P=a1.Assuming that P
Value is smaller, and it is higher to replace priority, then in order to reduce the invalid and write back operations of L1 data trnascriptions, it is necessary to increase write operation power
Weight, it is ensured that a1 is more than 2*a2.When write-back occurs for the Cache rows in L1, P=a3, now only data trnascription is deposited in system
It is in LLC, replacement will not cause " including victim ", therefore, replace priority increase, a3 is less than 2*a2.Meanwhile, when
When Cache rows have a read-only copy only in LLC, it should have highest to replace priority, now P=a2.It can be seen that
A1, a2, a3 magnitude relationship can be met：a1＞ 2a2＞ a3＞ a2。
In program operation process, the increase and decrease of the quantity of the shared copy of the Cache rows in LLC and write back operations cause
The promotion and demotion of priority.Priority reduction is replaced in read-only shared copy increase, P values increase；Upper strata, which is replaced, causes Cache rows to return
Being written in LLC will cause P values to decline, and replace priority and improve.
Significantly, since different applications has different Cache access characteristics, therefore, can assign different
Cache shares the different weight of state.For example, it is assumed that priority calculated value is smaller, replacement priority is higher, if time of system
Write expense big, then should assign write operation bigger weight, so as to reduce the replacement priority of the LLC rows with write operation copy.
Step 27, according to priority is replaced, according to the orderly principle of priority is replaced, the Cache rows of highest priority are changed
Go out, and the correspondence position that will newly call in Cache rows deposit target Cache.
In this step, replacing the orderly principle of priority is：Two Cache rows in same Cache, respectively should
The position of two Cache rows is designated as i and j, and wherein i and j have magnitude relationship；If i>J, then replace priority P i>Pj.
If the new initial replacement priority for calling in Cache rows is more than or equal to a non-LRU position in target Cache
Cache rows, then move one to LRU directions successively by the Cache rows from the Cache rows of the non-LRU position to LRU position
The distance of Cache rows, originally the Cache in LRU position is paged out, and is stored in the non-LRU position by Cache rows are newly called in
Cache rows.
Instantiation can be referring to shown in Fig. 3, and A, B, C, D and E represent to map to same Cache Cache rows, and wherein E is
New to call in Cache rows, numeral represents to replace priority P value.Replace before occurring, the Cache rows A with maximum P values is in MRU
Put, with minimum replacement priority, the Cache rows D with minimum P values is in LRU position, replace preferential with highest
Level.New Cache rows of calling in initially replace the initial of Cache rows B that priority is a non-LRU position in 20, target Cache
It is 20 to replace priority, then by the row D from Cache rows B to Cache successively to Cache row D directions move Cache row away from
From i.e. A->A+1,A+1->A+2,…,W-2->W-1, and the Cache rows newly called in are stored in the Cache rows being located at A.
Step 28, according to Cache coherency states and action type, the replacement priority of current accessed Cache rows is updated,
According to the orderly principle of priority is replaced, the promotion and demotion of priority are replaced to current accessed Cache rows.
In this step, with a kind of typical Cache coherence protocol, MESI (M：modified；E：exclusive；S：
shared；I：Invalid) illustrated exemplified by agreement.It is emphasized that the inventive method is not rely on specific Cache
Consistency protocol, any Cache coherence protocol for being suitable for inclusion in Cache hierarchical structures is applied to the inventive method.
In MESI protocol, the Cache rows in LLC have three kinds of possible shared states：1) M states：Cache rows are only
It is stored in LLC, without copy in the Cache of upper strata；2) SS states：Cache rows are present in LLC and upper strata Cache simultaneously, all data
Copy is readable state；3) MT states：Cache rows are in the upper strata Cache that mutually exclusive operation is permitted positioned at LLC and one simultaneously,
And the data in LLC may be modified in the Cache of upper strata.The Cache rows of three kinds of states are when replacing, it is necessary to perform
Operation it is different, postpone different.Wherein, the Cache rows in M states, which occur to replace, needs write-back LLC data；In SS states
It is except needing in addition to the data invalid in LLC, will also to need that the read-only data copy in the Cache of upper strata is invalid when Cache rows are replaced；
When Cache rows in MT states are replaced, the write back data that first need to be changed the possibility on upper strata is then invalid by its.
The replacement priority of Cache rows in LLC is closely related with its Cache coherency state, may be referred to such as the institute of table 1
The contrast relationship for the two shown：
Table 1
As it can be seen from table 1 the change and the read/write operation of action type of the shared number of copies of Cache coherency states
Situation, replaces priority P and changes.
Instantiation can be referring to shown in Fig. 4, and A, B, C, D represent to map to same Cache Cache rows, hatching designation
B, D are respectively current accessed Cache rows, and numeral represents to replace priority P value.Replace before occurring, the Cache with maximum P values
Row A is in MRU position, with minimum replacement priority, and the Cache rows D with minimum P values is in LRU position, with highest
Priority.
Assuming that write-back or replacement due to upper strata Cache, current accessed Cache rows B replacement priority P value become from 20
5, then according to the orderly principle of priority is replaced, current accessed Cache rows are degraded, will currently there are the Cache rows of minimum P values
B is in LRU position.
Assuming that due to shared number of copies increase, current accessed Cache rows D replacement priority P value becomes 20 from 10, then pressed
According to replace the orderly principle of priority, current accessed Cache rows are upgraded, by Cache rows D be moved to Cache rows A with
Between Cache rows B.
The coherency state information of Cache row of the present invention in LLC, divides in whole Cache levels Cache rows
Cloth and shared state are weighted, and obtain the replacement priority of Cache rows.On the one hand, the visit for being lacked in LLC
Ask, the new initial replacement priority for calling in Cache rows is calculated according to action type, will be excellent according to the orderly principle of priority is replaced
First level highest Cache rows swap out, and the correspondence position that will newly call in Cache rows deposit target Cache；On the other hand, for
The access hit in LLC, updates current accessed Cache rows according to Cache coherency states and action type and replaces priority,
According to the orderly principle of priority is replaced, the promotion and demotion of current accessed Cache rows are carried out, so as to reduce focus " including victim "
Ineffective treatment, lifted Cache access performances.
It should be understood that, although this specification is been described by according to embodiment, but not each embodiment only includes one
Individual independent technical scheme, this narrating mode of specification is only that for clarity, those skilled in the art will should say
Bright book is as an entirety, and the technical scheme in each embodiment may also be suitably combined to form those skilled in the art can
With the other embodiment of understanding.
Those listed above is a series of to be described in detail only for feasibility embodiment of the invention specifically
Bright, they are not intended to limit protection scope of the present invention, all equivalent implementations made without departing from skill spirit of the present invention
Or change should be included in the scope of the protection.
Claims (6)
1. the replacement method of Cache rows in a kind of afterbody cache memory LLC, it is characterised in that including：
If target Cache addresses are lacked in LLC, the new replacement priority for calling in Cache rows is calculated according to action type, pressed
According to the orderly principle of priority is replaced, the Cache rows of highest priority are swapped out, and Cache rows deposit target Cache is called in by new
Correspondence position；
If target Cache is hit address in LLC, according to Cache coherency states and action type, current accessed is updated
The replacement priority of Cache rows, according to the replacement orderly principle of priority, the lifting to current accessed Cache travelings row major level
Level；
It is described replace priority P calculation be：
P=a1×c×op+k×a2+a3× (1-c) × op,
Wherein, a1Write operation weight is represented, whether c represents copy in the Cache of upper strata write-back, if write-back, c=0 is no
Then, c=1；Op represents to cause the action type of replacement, write operation correspondence op=1, otherwise op=0；K represents read-only copy amount,
Its value is no more than shared LLC processor check figure；a2Represent read operation weight；a3Represent write back operations weight；
The P values are smaller, and replacement priority is higher, is preferentially replaced when replacing.
2. the replacement method of Cache rows, its feature in afterbody cache memory LLC according to claim 1
It is, the action type includes read operation and write operation；
If causing Cache rows in LLC to be replaced by read operation, the P=2*a newly called in Cache rows2；
If causing Cache rows in LLC to be replaced by write operation, the P=a newly called in Cache rows1, wherein, a1More than 2*a2；
If write-back occurs for upper strata Cache Cache rows, P=a3, wherein, a3Less than 2*a2；
If there is a read-only copy in LLC in upper strata Cache Cache rows, P=a2, wherein, a3More than a2。
3. the replacement method of Cache rows, its feature in afterbody cache memory LLC according to claim 1
It is, the replacement orderly principle of priority is：
Two Cache rows in same Cache, are designated as i and j, wherein i and j tools by the position of two Cache rows respectively
There is magnitude relationship；
If i is more than j, replaces priority P i and be more than Pj.
4. the replacement method of Cache rows in the afterbody cache memory LLC according to claim 1 or 3, it is special
Levy and be, it is described according to the orderly principle of priority is replaced, the Cache rows of highest priority are swapped out, and newly will call in Cache rows
Target Cache correspondence position is stored in, including：
If the new initial replacement priority for calling in Cache rows is more than or equal to a non-LRU position in target Cache
Cache rows, then move one to LRU directions successively by the Cache rows from the Cache rows of the non-LRU position to LRU position
The distance of Cache rows, originally the Cache rows positioned at LRU position are replaced, and new Cache rows of calling in are stored in into the non-LRU bit
The Cache rows put.
5. the replacement method of Cache rows, its feature in afterbody cache memory LLC according to claim 1
It is, the Cache coherency states are MESI, the Cache rows in LLC have following shared state：M states：Cache rows
Exist only in LLC, without copy in the Cache of upper strata；SS states：Cache rows are present in LLC and upper strata Cache simultaneously, all data
Copy is readable state；MT states：Cache rows are in the upper strata Cache that mutually exclusive operation is permitted positioned at LLC and one simultaneously, and
And the data in LLC may be modified in the Cache of upper strata；
Cache rows in M states, which occur to replace, needs write-back LLC data；Except needing when Cache rows in SS states are replaced
It is invalid by the read-only data copy in the Cache of upper strata outside data invalid in LLC, will also to need；Cache rows in MT states are replaced
When, need to be first by the write back data changed on upper strata, then by the data invalid changed on the upper strata.
6. according to claim 1 or 5 in afterbody cache memory LLC Cache rows replacement method, it is special
Levy and be, it is described that the replacement priority of current accessed Cache rows is updated according to Cache coherency states and action type, according to
The orderly principle of priority is replaced, the promotion and demotion to current accessed Cache travelings row major level, including：
According to the change of the shared number of copies of Cache coherency states and the read/write operation situation of action type, current visit is updated
Ask the replacement priority of Cache rows；
If change and the read/write operation situation of action type due to the shared number of copies of Cache coherency states, replace excellent
First level changes, and according to the orderly principle of priority is replaced, current accessed Cache rows is degraded or upgraded.
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| CN106126434B (en) * | 2016-06-22 | 2019-04-30 | 中国科学院计算技术研究所 | The replacement method and its device of the cache lines of the buffer area of central processing unit |
| CN108108312A (en) * | 2016-11-25 | 2018-06-01 | 华为技术有限公司 | A kind of cache method for cleaning and processor |
| CN106649150B (en) * | 2016-12-26 | 2020-04-24 | 锐捷网络股份有限公司 | Cache management method and device |
| US11061622B2 (en) * | 2017-11-13 | 2021-07-13 | Weka.IO Ltd. | Tiering data strategy for a distributed storage system |
| CN107861819B (en) * | 2017-12-07 | 2021-07-16 | 郑州云海信息技术有限公司 | Cache group load balancing method and device and computer readable storage medium |
| CN110147331B (en) * | 2019-05-16 | 2021-04-02 | 重庆大学 | Cache data processing method and system and readable storage medium |
| CN112612727B (en) * | 2020-12-08 | 2023-07-07 | 成都海光微电子技术有限公司 | Cache line replacement method and device and electronic equipment |
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