CN104157601A - Method for forming shallow trench isolation structure - Google Patents
Method for forming shallow trench isolation structure Download PDFInfo
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- CN104157601A CN104157601A CN201410410384.4A CN201410410384A CN104157601A CN 104157601 A CN104157601 A CN 104157601A CN 201410410384 A CN201410410384 A CN 201410410384A CN 104157601 A CN104157601 A CN 104157601A
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- Prior art keywords
- isolation structure
- fleet plough
- hard mask
- mask layer
- plough groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Abstract
The invention provides a method for forming a shallow trench isolation structure. The method comprises a step of providing a semiconductor substrate and forming a hard mask layer on the substrate, a step of etching the hard mask layer and the substrate to form an isolation trench, a step of carrying out back etching on the hard mask layer and forming an inner lining layer at the surface of the isolation trench, a step of depositing an isolation medium layer to fill the isolation trench and carrying out planarization process, a step of etching the isolation medium layer along an opening to form a groove structure, a step of carrying out ion injection in the groove structure in a oblique manner, wherein the ion injection amount at the middle of the groove structure is larger than the ion injection amount at the edge of the groove structure, and a step of using etching process to remove the hard mask layer to form the shallow trench isolation structure. According to the method, the appearance of a groove at the joint of the shallow trench isolation structure and the semiconductor substrate can be avoided, the appearance of the formed shallow trench isolation structure is improved, and thus the electrical properties of a semiconductor device with the formed shallow trench isolation structure are improved.
Description
Technical field
The present invention relates to a kind of integrated circuit technology manufacturing technology, relate in particular to a kind of method that forms fleet plough groove isolation structure.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, 0.18 micron of following element (for example, between the active area of CMOS integrated circuit) mostly adopts fleet plough groove isolation structure (STI) to carry out lateral isolation and makes.Integrated circuit comprises many transistors that are formed in Semiconductor substrate, and in general, transistor is to be spaced apart from each other by insulation or isolation structure.The technique that is commonly used to form isolation structure is that shallow trench isolation is from (shallow trench isolation is called for short STI) technique.
Of STI, make the device of isolating, general all very high to the requirement of the electric leakage of STI, and the pattern of STI top depression is a key factor that affects STI edge current leakage.When STI top depression deepens, can impact many techniques in later stage.For example, when carrying out etching polysilicon, because STI top depression is darker, very difficult that etching polysilicon in depression is clean, thus cause STI edge current leakage; In silicide growth technique, if STI top depression is darker, silicide can down be grown along edge, active area, produces electric leakage.
Fleet plough groove isolation structure is as a kind of device separation, and its existing concrete technology comprises:
S01: substrate 101 (please refer to Fig. 1) is provided;
S02: form silicon nitride layer 103 (please refer to Fig. 2) on described substrate 101;
S03: form the opening 105 that runs through described silicon nitride layer 103, described opening 105 has the shape corresponding with the isolation structure that defines active area (please refer to Fig. 3);
S04: the silicon nitride layer 103 that comprises opening 105 of take is mask, etched substrate 101 is to form isolated groove 107 (please refer to Fig. 4);
S05: in isolated groove 107 and opening 105 and the silicon nitride layer 103 surface deposition silica 109 of opening both sides, described silica 109 is filled full isolated groove 107 and opening 105 and covered the silicon nitride layer 103 (please refer to Fig. 5) of opening 105 both sides;
S06: remove unnecessary silica 109 (please refer to Fig. 6) on silicon nitride layer 103 by CMP technique;
S07: remove silicon nitride layer 103 by wet-etching technology, form fleet plough groove isolation structure 111 (please refer to Fig. 7); In Fig. 8, can find out, fleet plough groove isolation structure 111 forms depression 112 because wet-etching technology in Fig. 7 causes edge.
Above-mentioned known thus, by above-mentioned technique, form fleet plough groove isolation structure 111 time, while especially adopting wet-etching technology, easily at the edge of formed fleet plough groove isolation structure 111, form darker depression, cause the isolation performance of fleet plough groove isolation structure 111 not good, the semiconductor device that comprises fleet plough groove isolation structure 111 easily leaks electricity, and has had a strong impact on the stability of the semiconductor device that comprises fleet plough groove isolation structure 111.
Therefore, how to reduce the depression at fleet plough groove isolation structure 111 edges, improve the isolation performance of the fleet plough groove isolation structure that forms, become those skilled in the art's problem demanding prompt solution.
Summary of the invention
The object of this invention is to provide a kind of method that forms fleet plough groove isolation structure, can avoid formed fleet plough groove isolation structure Qi edge to occur groove, improved the electric property of the semiconductor device that forms.
For addressing the above problem, the invention provides a kind of method that forms fleet plough groove isolation structure, comprising:
Step S01: semi-conductive substrate is provided, and forms hard mask layer on described substrate, form the opening that exposes described substrate in described hard mask layer;
Step S02: adopt etching technics to form isolated groove in described substrate; Wherein, the bottom of described isolated groove is arranged in described substrate;
Step S03: described hard mask layer is returned to quarter, and form inner covering on described isolated groove surface;
Step S04: deposition spacer medium layer to be to fill described isolated groove and to cover the surface of described hard mask layer, and described spacer medium layer is carried out to flatening process;
Step S05: along described opening, described spacer medium layer is carried out to etching, to form groove structure;
Step S06: carry out Implantation in the mode tilting in described groove structure, wherein, the Implantation amount in the middle of described groove structure is greater than the Implantation amount of its rim;
Step S07: adopt etching technics to remove described hard mask layer, to form fleet plough groove isolation structure.
Preferably, described hard mask layer is that single layer structure and thickness are greater than
the material of described hard mask layer is wherein a kind of of polysilicon, silicon nitride or boron nitride.
Preferably, in step S06, the vertical plane of substrate surface of take is benchmark, and described angle of inclination is greater than 0 ° and is less than 45 °.
Preferably, described Implantation element is wherein a kind of of argon element, boron element, P elements, arsenic element or Ge element.
Preferably, in step S06, in described groove structure, inject after ion, carry out annealing in process.
Preferably, described inner covering is to form by high-aspect-ratio technique, and wherein, the thickness of described inner covering is 3nm～5nm.
Preferably, the material of described spacer medium layer is silica.
Preferably, in described step S04, employing chemical vapor deposition method is filled up described isolated groove by described spacer medium layer and is covered the surface of described hard mask layer.
Preferably, in described step S04, by chemical mechanical milling tech, remove the spacer medium layer being positioned at outside described isolated groove.
Preferably, in step S02, described etching technics is plasma etching industrial.
From technique scheme, can find out, in the method for formation fleet plough groove isolation structure provided by the invention, by making the Implantation amount in the middle of groove structure be greater than the Implantation amount of its rim, thereby control the speed that fleet plough groove isolation structure and etching solution react.Concrete, Implantation amount is larger, injects the speed that ion region and etching solution react faster.Hence one can see that, the two ends of fleet plough groove isolation structure are compared with the centre of its structure, slower with the speed that etching solution reacts, the two ends of the fleet plough groove isolation structure solution that can or not be etched is at short notice corroded, and then avoid the two ends of fleet plough groove isolation structure that sunk structure occurs causing electric leakage.The present invention has avoided occurring groove at fleet plough groove isolation structure and Semiconductor substrate seam crossing, improves the pattern of the fleet plough groove isolation structure that forms, and then improves the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure.
Accompanying drawing explanation
Fig. 1 to Fig. 8 is the cross-sectional view of fleet plough groove isolation structure that prior art forms;
Fig. 9 is the schematic flow sheet that the present invention forms an execution mode of method of fleet plough groove isolation structure;
Figure 10 to Figure 16 by the present invention, form in embodiment of method of fleet plough groove isolation structure the cross-sectional view of formation fleet plough groove isolation structure.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention is described in detail in detail, for convenience of explanation, schematic diagram does not amplify according to general ratio is local, should not using this as limitation of the invention.
Above-mentioned and other technical characterictic and beneficial effect, be elaborated to the method for formation fleet plough groove isolation structure of the present invention in connection with embodiment and accompanying drawing 9 to Figure 16.Fig. 9 is the schematic flow sheet of a preferred embodiment of the present invention's method of forming fleet plough groove isolation structure; Figure 10～16 are for adopting the schematic diagram of the fleet plough groove isolation structure that shown in Fig. 9, formation method manufactures.
Refer to Fig. 9, in the present embodiment, the invention provides a kind of method that forms fleet plough groove isolation structure and specifically comprise the following steps:
Step S01: semi-conductive substrate 10 is provided, and forms hard mask layer 20 on described substrate 10, the interior formation of described hard mask layer 20 exposes the opening 21 (as shown in figure 10) of described substrate 10.
Wherein, the material of Semiconductor substrate 10 is monocrystalline silicon, can be that silicon, germanium silicon can also be other semi-conducting materials, does not repeat them here.
Concrete, described hard mask layer 20 is greater than for single layer structure and thickness
the material of described hard mask layer 20 is wherein a kind of of polysilicon, silicon nitride or boron nitride.
In addition, hard mask layer 20 is preferably silicon nitride layer, between substrate 10 and hard mask layer 20, can be provided with cushion oxide layer, and cushion oxide layer can be two amorphous carbon (SiO
2), cushion oxide layer provides resilient coating for subsequent silicon nitride layer, and specifically, cushion oxide layer is for avoiding directly on substrate 10 grown silicon nitride layer can produce the shortcoming of dislocation, and it can be existing chemical vapor deposition method that silicon nitride layer forms technique.
Step S02: adopt etching technics to form isolated groove 30 in described substrate 10; Wherein, the bottom of described isolated groove 30 is arranged in described substrate 10 (as shown in figure 11).
Concrete, along the opening 21 of hard mask layer 20, be etched in substrate 10, form isolated groove 30.The formation technique of opening 21 can be existing plasma etching industrial.The technique of etching semiconductor substrate 10 can that is to say for existing plasma etching industrial, along opening 21 use plasma etching industrial etching semiconductor substrates 10, forms isolated groove 30.
Step S03: described hard mask layer 20 is returned to quarter, and form inner covering 40 (as shown in figure 12) on described isolated groove 30 surfaces.
By hard mask layer 20 is returned to quarter, thereby the thickness at spacer medium layer 50 two ends is increased greatly, thereby can stop etching solution to infiltrate the seam crossing of fleet plough groove isolation structure and Semiconductor substrate 10, avoid fleet plough groove isolation structure and the etching solution of seam crossing to react, and then avoid occurring groove at fleet plough groove isolation structure and Semiconductor substrate 10 seam crossings; In addition, can also prevent that trench filling from making the too early sealing of groove, thereby reduce the difficulty of trench fill.
Wherein, described inner covering 40 can form by existing high-aspect-ratio technique, and wherein, the thickness of described inner covering 40 is preferably 3nm～5nm.
Step S04: deposition spacer medium layer 50 to be to fill described isolated groove 30 and to cover the surface of described hard mask layer 20, and described spacer medium layer 50 is carried out to flatening process (as shown in figure 13).
Concrete, the material of described spacer medium layer 50 is silica; Employing chemical vapor deposition method is filled up described isolated groove 30 by described spacer medium layer 50 and is covered the surface of described hard mask layer 20; By chemical mechanical milling tech, remove the spacer medium layer 50 being positioned at outside described isolated groove 30.After flatening process, the upper surface of spacer medium layer 50 described in described isolated groove 30 is concordant with described hard mask layer 20 surfaces.
Step S05: carry out etching along 21 pairs of described spacer medium layers 50 of described opening, to form groove structure 60 (as shown in figure 14).
Concrete, described spacer medium layer 50 is returned to quarter, for the later stage, at its surface injection ion 70, the lower surface of described groove structure 60 rests between the upper surface and lower surface of described hard mask layer 20.
Step S06: carry out ion 70 in the mode tilting and inject in described groove structure 60, wherein, the Implantation amount in the middle of described groove structure 60 is greater than the Implantation amount (as shown in figure 15) of its rim.
Wherein, described Implantation element is preferably wherein a kind of of argon element, boron element, P elements, arsenic element or Ge element, and the upper surface of Implantation is preferably lower than described spacer medium layer 50, and Implantation amount is no more than the scope of groove structure 60.It is benchmark that the vertical plane on substrate 10 surfaces is take at described angle of inclination, is preferably more than 0 ° and is less than 45 °.Concrete, while adopting the mode at angle of inclination to carry out Implantation, make to keep relative rotation between Semiconductor substrate and ion gun, i.e. Semiconductor substrate rotation, ion gun maintenance fix indefinite; Or ion gun rotation, Semiconductor substrate keeps maintaining static.For guaranteeing that groove structure 60 middle Implantation amounts are greater than the Implantation amount of its rim all the time, the Implantation amount of rim is less, and groove structure 60 mid portions keep carrying out Implantation, Implantation amount is larger, injects the speed that ion region and etching solution react faster.Therefore, the two ends of fleet plough groove isolation structure are compared with the centre of its structure, slower with the speed that etching solution reacts, and the two ends of the fleet plough groove isolation structure solution that can or not be etched is at short notice corroded.
Preferably, after the interior injection ion of described groove structure 60, can carry out annealing in process.Wherein, the annealing temperature in annealing treating process is preferably 700 ℃～900 ℃, and annealing time is 20 seconds～35 seconds.
Step S07: adopt etching technics to remove described hard mask layer 20, to form fleet plough groove isolation structure (as shown in figure 16).
In the method for formation fleet plough groove isolation structure provided by the invention, by making the middle Implantation amount of groove structure be greater than the Implantation amount of its rim, thereby control the speed that fleet plough groove isolation structure and etching solution react, concrete, Implantation amount is larger, injects the speed that ion region and etching solution react faster.Therefore, the two ends of fleet plough groove isolation structure are compared with the centre of its structure, slower with the speed that etching solution reacts, the two ends of the fleet plough groove isolation structure solution that can or not be etched is at short notice corroded, and then avoid the two ends of fleet plough groove isolation structure that sunk structure occurs causing electric leakage.The present invention has avoided occurring groove at fleet plough groove isolation structure and Semiconductor substrate seam crossing, improves the pattern of the fleet plough groove isolation structure that forms, and then improves the electric property of the semiconductor device that comprises formed fleet plough groove isolation structure.
Above is only the preferred embodiments of the present invention, and embodiment is not in order to limit scope of patent protection of the present invention, and the equivalent structure that therefore every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. a method that forms fleet plough groove isolation structure, is characterized in that, comprising:
Step S01: semi-conductive substrate is provided, and forms hard mask layer on described substrate, form the opening that exposes described substrate in described hard mask layer;
Step S02: adopt etching technics to form isolated groove in described substrate; Wherein, the bottom of described isolated groove is arranged in described substrate;
Step S03: described hard mask layer is returned to quarter, and form inner covering on described isolated groove surface;
Step S04: deposition spacer medium layer to be to fill described isolated groove and to cover the surface of described hard mask layer, and described spacer medium layer is carried out to flatening process;
Step S05: along described opening, described spacer medium layer is carried out to etching, to form groove structure;
Step S06: carry out Implantation in the mode tilting in described groove structure, wherein, the Implantation amount in the middle of described groove structure is greater than the Implantation amount of its rim;
Step S07: adopt etching technics to remove described hard mask layer, to form fleet plough groove isolation structure.
2. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, described hard mask layer is that single layer structure and thickness are greater than
the material of described hard mask layer is wherein a kind of of polysilicon, silicon nitride or boron nitride.
3. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, in step S06, the vertical plane of substrate surface of take is benchmark, and described angle of inclination is greater than 0 ° and is less than 45 °.
4. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, described Implantation element is wherein a kind of of argon element, boron element, P elements, arsenic element or Ge element.
5. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, in step S06, in described groove structure, injects after ion, carries out annealing in process.
6. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, described inner covering is to form by high-aspect-ratio technique, and wherein, the thickness of described inner covering is 3nm～5nm.
7. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the material of described spacer medium layer is silica.
8. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, in described step S04, employing chemical vapor deposition method is filled up described isolated groove by described spacer medium layer and covered the surface of described hard mask layer.
9. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, in described step S04, removes the spacer medium layer being positioned at outside described isolated groove by chemical mechanical milling tech.
10. the method for formation fleet plough groove isolation structure as claimed in claim 1, is characterized in that, in step S02, described etching technics is plasma etching industrial.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410410384.4A CN104157601B (en) | 2014-08-20 | 2014-08-20 | The method for forming fleet plough groove isolation structure |
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| CN201410410384.4A CN104157601B (en) | 2014-08-20 | 2014-08-20 | The method for forming fleet plough groove isolation structure |
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| CN104157601A true CN104157601A (en) | 2014-11-19 |
| CN104157601B CN104157601B (en) | 2017-03-15 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158720A (en) * | 2015-04-03 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN111211039A (en) * | 2019-01-18 | 2020-05-29 | 合肥晶合集成电路有限公司 | Trench isolation structure and forming method thereof |
| CN113113347A (en) * | 2020-01-10 | 2021-07-13 | 芯恩（青岛）集成电路有限公司 | Shallow trench isolation structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010046750A1 (en) * | 2000-05-24 | 2001-11-29 | Shuji Miyazaki | Method for manufacturing semiconductor device having a STI structure |
| CN1540740A (en) * | 2003-04-21 | 2004-10-27 | 旺宏电子股份有限公司 | Method for preparing shallow trench isolation |
| CN102122630A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Fabrication method of shallow trench isolation (STI) structure |
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2014
- 2014-08-20 CN CN201410410384.4A patent/CN104157601B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010046750A1 (en) * | 2000-05-24 | 2001-11-29 | Shuji Miyazaki | Method for manufacturing semiconductor device having a STI structure |
| CN1540740A (en) * | 2003-04-21 | 2004-10-27 | 旺宏电子股份有限公司 | Method for preparing shallow trench isolation |
| CN102122630A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Fabrication method of shallow trench isolation (STI) structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158720A (en) * | 2015-04-03 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN111211039A (en) * | 2019-01-18 | 2020-05-29 | 合肥晶合集成电路有限公司 | Trench isolation structure and forming method thereof |
| CN113113347A (en) * | 2020-01-10 | 2021-07-13 | 芯恩（青岛）集成电路有限公司 | Shallow trench isolation structure and preparation method thereof |
| CN113113347B (en) * | 2020-01-10 | 2023-01-13 | 芯恩（青岛）集成电路有限公司 | Shallow trench isolation structure and preparation method thereof |
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| CN104157601B (en) | 2017-03-15 |
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