CN104135292B - Mixed mode time interleaving digital analog converter for radio frequency applications - Google Patents

Abstract

Open one kind is related to the system, apparatus and method of mixed mode time interleaving digital analog converter (DAC).In certain embodiments, this DAC can be used for radio frequency (RF) application.In certain embodiments, the DAC for RF application may include the first circuit, is configured to receive digital signal and executes the first operation to generate the increased bandwidth of the DAC.The DAC may further include second circuit, be configured to execute the digital signal the second operation to generate the analog signal for representing the digital signal.The second circuit can be further configured to reduce or eliminate image in the increased bandwidth.

Description

Mixed mode time interleaving digital analog converter for radio frequency applications

Cross reference to related applications

This application claims entitled " the mixed mode time interleaving digital-to-analogues for radio frequency applications submitted on May 2nd, 2013 The U.S. Provisional application No.61/818 of converter ", 788 priority are open to be incorporated herein explicitly by reference is whole.

Technical field

The disclosure generally relates to a kind of digital analog converter (DAC) for radio frequency (RF) application.

Background technique

In many digital radio devices and system, data are generally handled in a digital format, and be converted into for passing Defeated analog format.This conversion is usually executed by digital analog converter (DAC).

Digital information is converted to the analog representation of the information with separated step by DAC.It, can during this conversion process Many effects can be shown；And at least some of this effect may be decreased the performance of equipment and system using DAC.

Summary of the invention

In some implementations, this disclosure relates to a kind of digital analog converter (DAC) comprising the first circuit is configured to It receives digital signal and executes the first operation to generate the increased bandwidth of the DAC.The DAC further comprises the second electricity Road is configured to execute the digital signal the second operation to generate the analog signal for indicating the digital signal.Described second Circuit is further configured to reduce or eliminate image (image) in the increased bandwidth.

In certain embodiments, first circuit may include up-sampling circuit, be configured to described in coefficient n up-sampling Digital signal, wherein quantity n is real number, such as 2.First circuit may further include finite impulse response (FIR) (FIR) filter Wave device is configured to receive the digital signal of the up-sampling, and generates the digital signal of filtered up-sampling.

In certain embodiments, first circuit may further include the mixing electricity communicated with the second circuit Road.The hybrid circuit is configurable to execute mixed mode operations.In certain embodiments, the second circuit may include Time interleaving DAC (TIDAC) circuit communicated with the hybrid circuit.The TIDAC circuit may include multiple samplings and guarantor Hold (S/H) circuit.Each S/H circuit is configurable to receive the digital signal of the up-sampling and generates the simulation after conversion Signal.The TIDAC circuit may include the clock with the multiple S/H circuit communication.The clock is configurable to institute It states multiple S/H circuits and staggered clock signal is provided.The TIDAC circuit may further include delay circuit, be configured to as institute It states at least one of staggered clock signal and delay is provided.

In some embodiments it is possible to execute the mixed mode operations in analog domain.The hybrid circuit can wrap Include the multiplier circuit communicated with each of the S/H circuit.Each multiplier circuit is configurable to corresponding from it S/H circuit receive the analog signal after the conversion and mix clock signal.Each multiplier circuit can further match It is set to based on the analog signal and mix clock signal generation product signal after the conversion.First circuit can be into One step includes the summing circuit communicated with each of the multiple multiplier circuit.The summing circuit be configurable to from Its corresponding multiplier circuit receives the product signal, and generates analog output signal for the DAC.

In some embodiments it is possible to execute the mixed mode operations in the digital domain.The hybrid circuit can wrap Include the multiplier circuit that the input with each of the multiple S/H circuit communicates.The multiplier circuit is configurable to Receive the digital signal and mix clock signal of the up-sampling.The multiplier circuit can be further configured to based on described The digital signal of up-sampling and the mix clock signal are the multiple S/H circuit evolving product signal.First circuit It may further include the switching circuit that the output with each of the multiple S/H circuit communicates.The switching circuit can To be configured to receive analog signal and clock signal after the conversion from each of the multiple S/H circuit.It is described to open Powered-down road can be further configured to generate analog output signal for the DAC circuit.The clock provided to the switching circuit Signal can be provided from the clock for the TIDAC for providing the staggered clock signal to the multiple S/H circuit.

In certain embodiments, the analog signal may include radio frequency (RF) signal.Described image may include spuious Emit wave crest.

In certain embodiments, the increased bandwidth can have effective frequency model more broader than sinc receptance function It encloses.The increased bandwidth can have the broader effective frequency range of the response than only being obtained by mixed mode operations.

According to many implementations, this disclosure relates to a kind of for converting digital signals into the side of radio frequency (RF) signal Method.The method includes receiving the digital signal and execute the first operation to generate the increased bandwidth of RF signal.The side Method further comprises executing the second operation to the digital signal to generate the RF signal.Second operation is further in institute It states in increased bandwidth and reduces or eliminates image.

In certain embodiments, first operation may include up-sampling the numerical data.First operation can To further comprise being filtered to the numerical data of the up-sampling.

In certain embodiments, the operation may further include hybrid manipulation.It can be in numeric field or analog domain Execute the hybrid manipulation.Second operation may include executing multiple time interleaving numbers to the numerical data of the up-sampling Mould converts (TIDAC) operation.Second operation may further include the output for merging the TIDAC operation, or selection institute State one in the output of TIDAC operation.

In many introductions, this disclosure relates to which a kind of baseband subsystems, generate the processor of digital signal including being configured to Be configured to being converted to the digital signal into the digital analog converter (DAC) of radio frequency (RF) signal.The DAC includes the first electricity Road is configured to receive the digital signal and executes the first operation to generate the increased bandwidth of the DAC.The DAC is into one Step includes second circuit, is configured to execute the digital signal the second operation to generate the RF letter for representing the digital signal Number.Second operation is further configured to reduce or eliminate image in the increased bandwidth.

According to certain implementations, this disclosure relates to a kind of wireless system, the base band including being configured to processing digital signal Subsystem.The baseband subsystems have digital analog converter (DAC), including are configured to receive the digital signal and execute first It operates to generate the first circuit of the increased bandwidth of the DAC.The DAC further comprises second circuit, is configured to institute It states digital signal and executes the second operation to generate radio frequency (RF) signal for representing the digital signal.The second circuit is further It is configured to reduce or eliminate image in the increased bandwidth.The wireless system further comprises and the baseband subsystems The RF subsystem of communication.The RF subsystem is configured to receive the RF signal and generates amplified RF signal.It is described wireless System further comprises the antenna with the RF subsystem communication.The antenna configuration is convenient for the amplified RF signal Transmission.

In some embodiments it is possible to realize the wireless system in infrastructure base station.It can be in such as mobile phone The wireless system is realized in portable radio machine.

For the purpose for summarizing the disclosure, this document describes certain aspects of the invention, advantage and novel features.It manages All these advantages may not necessarily be realized by solving any specific embodiment according to the present invention.It therefore, can be with as taught herein Realization or one advantage of optimization or the mode of one group of advantage the present invention is practiced or carried out, without such as introduction herein or suggestion Realize further advantage.

Detailed description of the invention

Fig. 1 describes the digital analog converter (DAC) with one or more features as described herein.

Fig. 2 shows in some embodiments it is possible to realize the DAC of Fig. 1 in radio systems.

Fig. 3 A shows conventional DAC configuration.

Fig. 3 B shows the example of up-sampling configuration.

Fig. 3 C shows the example of time interleaving DAC (TIDAC) configuration.

Fig. 4 A is shown with sample frequency F_SWith pitch frequency (tone frequency) F_toneConventional DAC example ring It answers.

Fig. 4 B shows the example DAC operational circumstances for being likely to occur relatively large spurious emissions wave crest.

Fig. 5 A shows with the zero of normal sample model comparision (RZ) and mixes the example of (MIX) sampling configuration.

Fig. 5 B shows the example of the power spectral density estimation for the sampling configuration of Fig. 5 A.

Fig. 6 A shows example Normal Mode Operation situation, wherein (7/8) F_SPitch frequency F_toneIt generates about 0.3GHz's The spurious emissions (image) of opposite high-amplitude, wherein F_SFor 2.4GHz.

Fig. 6 B shows example hybrid mode operational circumstances, wherein F_toneAnd F_SIt is identical as Fig. 6 A, generate raised tone frequency Rate F_toneAmplitude, but wherein spurious emissions (image) amplitude can remain sufficiently high for influence bandwidth of operation.

Fig. 7 A is shown with F identical with Fig. 6 A_toneAnd F_SThe input spectrum of the TIDAC system of operation.

Fig. 7 B shows the output spectrum of the TIDAC system of Fig. 7 A, wherein essentially eliminating image from 0.3GHz.

Fig. 8 shows example DAC configuration, and can be implemented as providing has improved tone power and reduce or substantially eliminate Image output spectrum.

The F that Fig. 9 A is shown with 2.4GHz_SWith the F of 0.3GHz_toneOutput spectrum caused by the DAC of Fig. 8 of operation shows Example, wherein basic do not have or reduce the first image.

The F that Fig. 9 B is shown with 2.4GHz_SWith the F of 2.1GHz_toneOutput spectrum caused by the DAC of Fig. 8 of operation it is another Example, wherein also not having or reducing the first image substantially.

Figure 10 shows another example DAC configuration, can be implemented as providing the desired characteristics for being similar to Fig. 8 and 9.

Figure 11 shows the process that can be implemented as executing DAC operation as described herein.

Figure 12 shows the more specific exemplary process that can be the process of Figure 11 in the context of the DAC system of Fig. 8.

Figure 13 shows the more specific exemplary mistake that can be the process of Figure 11 in the context of the DAC system of Figure 10 Journey.

Figure 14 describes the example of radio frequency (RF) system, with one realized in a wireless device as described herein or more A DAC.

Figure 15 describes the example of RF system, with one realized in the wireless system of such as base station as described herein Or multiple DAC.

Specific embodiment

Headings provided herein, if any, be intended merely to conveniently, and not necessarily will affect claimed The range or meaning of invention.

Disclosed herein is be related to the various systems of digital-to-analogue conversion of signal for radio frequency (RF) application, circuit, equipment and Method.Although being described in the context of RF application, it will be appreciated that the one or more features of the disclosure can be used for relating to And in the other application of digital-to-analogue conversion.

When the signal of number format is synthesized RF format, in fact it could happen that the bandwidth limitation of digital analog converter (DAC) Problem.In some cases, this bandwidth limitation may include due to Nyquist bandwidth F_S/ 2 band in response to DAC limits (band limited) frequency, wherein F_SRepresent sample frequency.This frequency band limitation can produce the dynamic model for reducing RF system The effect enclosed.This frequency band limitation can also cause and be used for F_SFrequency domain in the associated problem of signal replication, close F_SThe spurious emissions close to the signal sent are generated when/2 operation.

Fig. 1 schematic depiction has the DAC100 of one or more features as described herein.These features can be conducive to Solve the problems, such as it is above-mentioned with for RF application in DAC it is associated some or all.As depicted in fig. 1, DAC100 can match It is set to and receives digital signal and generate the RF signal for representing the digital signal.Showing for DAC100 will be described in further detail herein Example.

Fig. 2 describes the wireless system that wherein may be implemented to have the DAC100 of one or more features of the disclosure.At certain In a little embodiments, DAC100 can be realized in baseband subsystems 102, to convert digital signals into corresponding analog signal. This analog signal can be supplied to transmitter 110, be configured to generate be used for transmission (for example, by power amplifier (PA) 112) amplified RF signal.In some embodiments it is possible to realize transmitter 110 and PA112 in RF subsystem 104.

Fig. 2, which is further shown, can be supplied to antenna by front end system 106 for the amplified RF signal from PA112 108.In certain embodiments, front end system 106 is configurable to convenient for receiving (Rx) (not shown) and sending (Tx) operation.

In some embodiments it is possible in the base station for being related to converting digital signals into analog signal, wireless device or appoint The wireless system of Fig. 2 is realized in RF system of anticipating.Although in addition, the example in DAC100 as a part of baseband subsystems 102 It is described in context, it will be appreciated that the one or more features of the disclosure can also be realized in other types of RF framework.

Fig. 3 A, which is shown, to be wherein supplied to sampling for the digital signal 122 for being portrayed as " Data_in " and keeps (S/H) circuit 124 conventional DAC configuration 120.Can in a known way configuration and operation S/H circuit 124 to generate simulation output.

As generally understood, response characteristic possessed by above-mentioned routine DAC configuration usually is or is similar to sync letter It counts, wherein sinc (x)=sin (x)/x.It usually also will appreciate that when DAC is with frequency F_SSampling is to generate pitch frequency F_toneWhen, it can To generate frequency F_IMThe spurious emissions at place.F_IMIt can be expressed as F_IM=F_S-F_tone, and this spurious emissions are usually to be not intended to 's.These spurious emissions are also referred to as image herein.

The sample frequency F that Fig. 4 A is shown with 2.4GHz_SOperate and generate the pitch frequency F of 0.1GHz_tone(wave crest 160) The example response of conventional DAC (for example, example of Fig. 3 A).As shown, in the frequency (F of about 2.3GHz (2.4-0.1)_IM) at go out Existing spurious emissions (image) wave crest.In the specific example, F_toneAnd F_IMIt is clearly separated, and substantially due to the response of sinc function Reduce spurious emissions amplitude.Therefore, relatively small spurious emissions wave crest 162 can relatively easily be eliminated.

However, it is contemplated that another sample situation as shown in Figure 4 B, wherein F_S=2.4GHz, and F_tone1.5GHz (wave crest 166).As shown, in about 0.9GHz (2.4-1.5) F_IMThere is relatively large spurious emissions (image) wave crest 164 in place.

Based on above-mentioned example, pay attention to F_toneIncrease, tone power reduces, to reduce dynamic range.In addition, working as F_toneBecome close to F_SWhen/2, undesirably F_IMBecome close to F_tone.Frequency F_S/ 2 are sometimes referred to as Nyquist frequency.It is generally understood The effect of this frequency and relevant such as aliasing (aliasing).

It can be solved in many ways with reference to Fig. 4 A and the 4B above-mentioned effect described.For example, signal equalization can maintain or Improve DAC system dynamic range, with compensate DAC response roll-off (roll-off).Can also using such as resampling or on Sample the technology for the data come.In the context of up-sampling, it can use many operation modes.Zero mode and hybrid guided mode Formula is the example of this operation mode.

Fig. 3 B schematic depiction up-sampling configuration 130, wherein the up-sampling up-sampling of component 134 is portrayed as " Data_in " Digital signal 132.If up-sampled with coefficient n, can be from up-sampling component 134 there is sample frequency is imitated nF_S.The data of up-sampling are illustrated as being supplied to sampling and keep (S/H) circuit 136.It can configuration and operation institute in a known way S/H circuit 136 is stated to generate simulation output.

Fig. 5 A and 5B show above-mentioned zero (RZ) and mixing (MIX) mode operation compared with conventional (normal) DAC operation The example of (for example, the up-sampling for Fig. 3 B configures).In fig. 5, describe and represent normal, RZ and MIX mode sampling week Phase.Fig. 5 B shows the power spectral density estimation for model identical.

In figure 5B, MIX mode is illustrated as generating widest bandwidth expansion in three kinds of example arrangements, and indicated with arrows The crest location of MIX mode response.At the frequency for corresponding to this wave crest, even if equilibrium is utilized, sampled using zero hold Normal response (" O ") power be also in sinc response abrupt slope in.RZ sampling in the case where, power fall to about- 8dBFS can seriously reduce the noise spectrum and spectral mask performance of DAC, so that the response is not used to example Low noise spectral density (NSD) application such as associated with infrastructure base station.

For MIX mode tool there are three widest bandwidth expansion in example, bandwidth can also be limited to spurious emissions (image). This effect is shown with reference to Fig. 6 A and 6B.Fig. 6 A shows Normal Mode Operation situation, wherein ideal pitch frequency F_toneIt is (7/ 8)F_S, F_SFor 2.4GHz.Therefore, F_toneAbout 2.1GHz, and the spurious emissions (image) of opposite high-amplitude (are rung based on sinc Answer) it is illustrated as F in about 0.3GHz_IMPlace generates.

In fig. 6b, there is same tone and sample frequency (F_S=2.4GHz, F_tone=(7/8) F_S=2.1GHz) MIX Mode operation is illustrated as generating raised pitch frequency F_toneAmplitude (for example, increase about 13dB), and in the F of about 0.3GHz_IM Place reduces the amplitude of image.However, spurious emissions amplitude (image) can remain sufficiently high for influencing bandwidth of operation.

In some applications, for example spuious hair can be reduced for example, by the technology of time interleaving DAC (TIDAC) framework Penetrate the frequency spectrum duplicate (replica) of (image).In general, TIDAC configuration may include the parallel connection in multiple channels DAC (parallel) it combines, and the output in these channels can be summed to generate total system output.

Fig. 3 C shows tool, and there are two the example TIDAC in the channel DAC configurations 140.First passage is shown as including to receive data It inputs the first sampling of (Data_in) 142 and keeps (S/H) component 148.Similarly, second channel is shown as including also to receive The 2nd S/H component 150 of data input (Data_in) 142.First S/H component 148 be illustrated as by from clock 144 when Clock signal operation, and the 2nd S/H component 150 is illustrated as the delay by the clock signal from clock 144 (for example, half Period) version operation.In this example, the delay is illustrated as being introduced by component 146.

Fig. 3 C is further shown can merge the defeated of the first and second S/H component 148,150 in summing circuit 152 Out to generate simulation output.This TIDAC configuration can effectively eliminate the image of spurious emissions generation.For example, Fig. 7 A is shown With the F of 2.1GHz_tone(wave crest 170) (wherein F_S=2.4GHz) operation TIDAC system input spectrum.Fig. 7 B show including F at 2.1GHz_toneThe output spectrum of wave crest 172, and the first image is substantially eliminated near 0.3GHz or its.When from When the output spectrum effectively eliminates image, pay attention to roll-offing due to sinc, the output power of tone wave crest 172 is from input power Reduce about 12dB.

In some implementations, DAC system be configurable to include with for increase output tone power (for example, from And expand available bandwidth) the associated one or more features of technology, and be not intended to for reducing or substantially eliminate Image the associated one or more features of technology.For example, the MIX pattern configurations that can will be described with reference Fig. 3 B, 5,6 Associated one or more features and one or more features knot associated with the TIDAC configuration of reference Fig. 3 C, 7 descriptions It closes.Although being described in this exemplary context, one that the disclosure can be realized in other combinations can be understood Or multiple features.

Fig. 8, which is shown, may be embodied as providing for example with improved tone power and reduction or the image substantially eliminated The example DAC configuration 100 of the desired characteristics of output spectrum.DAC configuration 100 may include up-sampling circuit 204 (for example, to be Number 2 up-samples), passage path 202 receives the input of digital signal 200 to generate the data of up-sampling.It can be with passage path This data are supplied to filter 208 (for example, finite impulse response (FIR) (FIR) filter) to generate in outgoing route 210 by 206 Up-sampling and filtered data.

Up-sampling and filtered data are illustrated as passage path 210,212 and are supplied to the first S/H circuit 214.Similarly, Up-sampling and filtered data are considered as also passage path 210,216 and are supplied to the 2nd S/H circuit 218.It can be in TIDAC mould The first and second S/H circuits 214,218 are operated in formula.For example, the first S/H circuit 214 is illustrated as by passing through from clock 220 The clock signal in path 222 and 224 operates, and the 2nd S/H circuit 218 is illustrated as by the passage path from clock 220 222, delay (for example, half period) the version operation of 226 and 230 clock signal.In this example, the delay is illustrated as It is introduced by component 228.

In the example arrangement 100 of Fig. 8, hybrid manipulation can be executed in analog domain.For example, can be with from clock 250 mixed mode clock signal multiplied by the first and second S/H circuits 214,218 each of simulation output.More specifically Ground, the simulation output from the first S/H circuit 214 are illustrated as passage path 240 and are supplied to the first multiplier circuit 260, and Mixed mode clock signal from clock 250 is illustrated as passage path 252 and 254 and is supplied to the first multiplier circuit 260.The One multiplier circuit 260 is illustrated as exporting product signal to path 262.Similarly, the simulation from the 2nd S/H circuit 218 is defeated It is illustrated as passage path 242 out and is supplied to the second multiplier circuit 264, and the mixed mode clock signal from clock 250 It is illustrated as passage path 252 and 256 and is supplied to the second multiplier circuit 264.Second multiplier circuit 264 is illustrated as exporting product Signal is to path 266.

As further described in association with figure 8, the output signal of the first and second multiplier circuits 260,264 is illustrated as by summing circuit 270 merge.Summing circuit 270, which is illustrated as generating the output that may be used as DAC100, outputs signal to path 272.

The DAC for being configured in the above manner and operating can produce ideal function, including increase bandwidth and at least described Reduce or substantially eliminate image in increased bandwidth.For example, Fig. 9 A and 9B show the F with 2.4GHz_S, be respectively 0.3GHz (figure The wave crest 280 of 9A) and 2.1GHz (wave crest 282 of Fig. 9 B) F_toneOutput spectrum caused by the DAC100 of Fig. 8 of operation.It can It is basic there is no or reduce the first image to find out in each frequency spectrum.More specifically, not having substantially in the frequency spectrum of Fig. 9 A The F of 2.1GHz (2.4-0.3)_IMFirst image at place；F in the frequency spectrum of Fig. 9 B substantially without 0.3GHz (2.4-2.1)_IMPlace The first image.In addition, the 0.3GHz tone (wave crest 280) and 2.1GHz (wave crest of roughly the same (for example, greater than about -50dB) 282) output power of tone shows improved bandwidth.

Figure 10 shows another example DAC configuration 100, can be implemented as providing similar with the feature with reference to described in Fig. 8 and 9 Desired characteristics.In the example in Figure 10, hybrid manipulation can be carried out in numeric field.

DAC configuration 100 may include up-sampling circuit 204 (for example, with the up-sampling of coefficient 2), and passage path 202 receives The input of digital signal 200 is to generate the data of up-sampling.This data can be supplied to filter 208 with passage path 206 (for example, finite impulse response (FIR) (FIR) filter) is to generate up-sampling and the filtered data in outgoing route 210.

In the example arrangement 100 of Figure 10, hybrid manipulation can be executed in the digital domain.For example, can be with from clock 290 mixed mode clock signal is multiplied by numerical data (path 210).More specifically, after up-sampling and filtering in path 210 Data and path 292 in clock signal be illustrated as being supplied to multiplier circuit 294.Multiplier circuit 294 is illustrated as exporting Product signal is to path 296.

Hybrid digital data from multiplier circuit 294 are illustrated as passage path 296 and 298 and are supplied to the first S/H electricity Road 214.Similarly, hybrid digital data are illustrated as passage path 296 and 300 and are supplied to the 2nd S/H circuit 218.It can be The first and second S/H circuits 214,218 are operated in TIDAC mode.For example, the first S/H circuit 214 is illustrated as by from clock The clock signal of 220 passage path 222,224,302 operates, and the 2nd S/H circuit 218 is illustrated as by from clock 220 Passage path 222,226,230 clock signal delay (for example, half period) version operation.In this example, described Delay is illustrated as being introduced by component 228.

In the example depicted in fig. 10, the simulation output of the first and second S/H circuits 214,218 is illustrated as passing through road respectively Diameter 310 and 312 is supplied to switching circuit 314.The switching circuit 314 is illustrated as receiving also by path 222,224 and 304 From the staggered clock signal of clock 220.The switching circuit 314 can also be operated to switch and the first and second S/H circuits 214, the output between 218 associated two channels interleaveds (in path 316).

In certain embodiments, switching circuit 314 can be implemented as the switch of very high frequency.In certain embodiments, may be used To realize this switch to generate High Linear performance.

Figure 11 shows process 330, can be implemented as executing the DAC behaviour with one or more features as described herein Make.In frame 332, numerical data can receive.In frame 334, DAC operative combination can be executed to the numerical data to increase Add operation bandwidth simultaneously reduces or eliminates the image in the bandwidth.

In the context of the example DAC system of Fig. 8 and 10, process 340 and 360 is shown respectively in Figure 12 and 13, can be with It is embodied as the more specific example of the process 330 of Figure 11.In the frame 342 of the instantiation procedure 340 of Figure 12, digital number can receive According to.In frame 344, the numerical data can be up-sampled.In frame 346, the data of the up-sampling can be filtered. In frame 348, multiple time interleaving samplings can be executed and keep operation.It can be the time interleaving S/H in frame 350 Each simulation output of operation executes hybrid manipulation.In frame 352, the hybrid analog-digital simulation output can be merged to generate simulation Output.

In the frame 362 of the instantiation procedure 360 of Figure 13, numerical data can receive.In frame 364, institute can be up-sampled State numerical data.In frame 366, the data of the up-sampling can be filtered.It, can be to adopting on described in frame 368 Sample and filtered numerical data execute hybrid manipulation.In frame 370, can be executed to the hybrid digital data multiple times Interlaced sampling and holding operation.In frame 372, it is defeated to generate simulation with the output for selecting S/H to operate that switch operation can be executed Out.

As described herein, one or more features as described herein can be realized in wireless system and/or equipment.Example Such as, infrastructure base station may include the wireless system with one or more features as described herein.

It in some implementations, can include in example by the DAC system with one or more features as described herein As wireless device RF equipment in.Can be with one or more modular forms, or certain is combined with it, in the wireless device In be directly realized by this equipment and/or circuit.In certain embodiments, this wireless device may include such as cellular phone, Smart phone, with and without handheld wireless device, wireless flat computer of telephony feature etc..

Figure 14 describes the exemplary wireless device 400 with one or more favorable characteristics as described herein.Have herein In the context of the DAC100 of the one or more features, this circuit or equipment can be such as baseband subsystems 410 A part.

In exemplary wireless device 400, transceiver 414 is illustrated as interacting with baseband subsystems 410, inter alia, It is configured to provide for suitable for the data and/or voice signal of user and suitable for the conversion between the RF signal of transceiver 414.In order to Transmission, transceiver 414 can provide the RF signal not amplified to power amplifier 416 to generate amplified RF signal.It can be with The amplified RF signal is supplied to antenna 424 for example, by switch 422 (via duplexer 420).Transceiver 414 may be used also To be configured to processing received signal.Can by these received signals from antenna 424 by duplexer 420 be sent to one or Multiple LNA (not shown).Transceiver 414 is also illustrated as being connected to power management component 406, is configured to management for wirelessly setting The power of standby 400 operation.

Baseband subsystems 410 be shown connected to user interface 402 in order to be supplied to user and receive from it voice and/ Or the various inputs and output of data.Baseband subsystems 410 may be also connected to memory 404, be configured to storing data and/ Or instruction provides information storage in order to the operation of wireless device and/or for user.

Many other wireless device configurations can use one or more features as described herein.For example, wireless device is not It needs to be multiband equipment.In another example, wireless device may include such as diversity antenna additional antenna and Such as the additional connection features of Wi-Fi, bluetooth and GPS.

It in some implementations, can include in example by the DAC system with one or more features as described herein In the wireless system of wireless system such as associated with infrastructure base station.Figure 15 schematic depiction has one as described herein Or the example wireless system 500 of multiple favorable characteristics.Above and below the DAC100 with one or more features as described herein In zhang, this circuit or equipment can be a part of such as Digital Subsystem 502.Digital Subsystem 502 is configurable to mention For one or more functions associated with baseband subsystems.Digital Subsystem 502 can also include processor 504, configuration For control and/or convenient for Digital Subsystem 502 various functions.

In example wireless system 500, the transceiver 512 of RF subsystem 510 is illustrated as interacting with Digital Subsystem 502. Inter alia, Digital Subsystem 502 is configurable to provide the data for being suitable for user and/or voice signal and is suitable for transmitting-receiving Conversion between the RF signal of device 512.In order to transmit, transceiver 512 can provide the RF not amplified to power amplifier 514 to be believed Number, to generate amplified RF signal.It can be provided for example, by front end (FE) system 520 to antenna 522 described amplified RF signal.Transceiver 512 is also configured as processing received signal.It can will be received from antenna 520 by front end system 520 Signal be sent to low-noise amplifier (LNA) 516.Can include by many other components in wireless system 500 in order to It is operated.

In the context for converting digital signals into analog rf signal, this document describes various examples.As usually managed Solution, this analog signal processing being used for transmission can be first intermediate frequency (IF) signal by RF subsystem, and then processing is RF Signal.Accordingly, it will be understood that the RF signal that DAC as described herein is generated may include with times with wireless device and/or system The mould of what associated frequency in part or frequency range (including frequency associated with aforementioned IF and RF signal or frequency range) Quasi- signal.

The present disclosure describes various features, are totally responsible for benefit as described herein without one kind.Can understand can group Close, modification or omit various features described herein, this it will be apparent to those skilled in the art that.Except specifically describing herein Combination and sub-portfolio except those of outer combination and sub-portfolio it will be apparent to those skilled in the art that, and it is intended to Constitute a part of the displosure.Various methods are described herein in conjunction with each flow chart step and/or stage.It can understand in many In the case of, certain steps and/or stage can be merged, so as to hold multiple steps shown in the flowchart and/or stage One step of behavior and/or stage.Furthermore, it is possible to be the additional sub-component being performed separately by certain steps and/or stage resolutions. In some instances, the sequence in the step and/or stage can be rearranged, and can be completely omitted certain steps and/ Or the stage.In addition, method described herein is understood to open, so that can also be performed illustrated and described herein additional Step and/or stage.

Any combination that such as computer software, hardware, firmware or computer software, hardware and firmware can be used is advantageous Realize some aspects of system and method as described herein in ground.Computer software may include computer-readable medium (for example, non- Temporary computer-readable medium) in store computer-executable code, execute when execute function as described herein.At certain In a little embodiments, computer-executable code is executed by one or more general-purpose computer processors.According to the displosure, this field Technical staff can understand that the software that can be used and execute on general purpose computer can also use come any feature or function realized The various combination of hardware, software or firmware is realized.It is, for example, possible to use integrated circuit combinations completely with this mould of hardware realization Block.Alternatively or additionally, the special purpose computer for being designed as executing specific function as described herein can be used rather than general Computer realizes this feature or function completely or partially.

Multiple distributive computing facilities can replace any calculating equipment as described herein.In this distributed embodiments In, the function of a calculating equipment is distributed (for example, on network), thus in each of distributive computing facility It is upper to execute certain functions.

It can be illustrated with reference equation, algorithm and/or process to describe some embodiments.Can be used can be at one or more The computer program instructions executed on a computer realize these methods.These methods are also implemented as individual computer The component of program product or device or system.It in this regard, can be by hardware, firmware and/or including computer-readable program The software realization for the one or more computer program instructions implemented in code logic each equation, algorithm, flow chart box or Step and combinations thereof.As it will be appreciated, these any computer program instructions can be loaded into one or more computers, including But general purpose computer or special purpose computer or other programmable processing units are not limited to generate machine, so that one or more meters The computer program instructions that are executed on calculation machine or one or more of the other programmable processing equipment realize the equation, algorithm and/ Or the function of being specified in flow chart.It will also be appreciated that frame and combinations thereof in each equation, algorithm and/or process diagram can be by Dedicated hardware based computer system is realized, the finger of specialized hardware and computer readable program code logic device is executed Fixed function or step or combination.

Further, it is also possible to which the computer program instructions for example realized in computer readable program code logic are stored in In computer-readable memory (for example, non-transitory computer-readable medium), can guide one or more computers or Other programmable processing equipments are run in a specific way, so that the instruction stored in computer-readable memory realizes one or more The one or more functions specified in one or more frames of a flow chart.Can also by computer program instructions be loaded into one or Multiple computers or other programmable computation devices are so that one or more of computers or other programmable computation devices The series of operation steps of upper execution generate computer implemented process, so that the computer or other programmable processing units The instruction of upper execution is provided for realizing one or more equations, one or more algorithms and/or one or more flow charts The step of function is specified in one or more frames.

It can be executed by computer system and be fully automated some or all method and task as described herein.Certain In the case of, the computer system may include on network communicate and interoperate by execute the function it is multiple and different in terms of Calculation machine calculates equipment (for example, physical server, work station, storage array etc.).Each this calculating equipment generally includes Processor (or multiple processors) is executed and is stored in memory or other non-transitory computer-readable storage medias or equipment Program instruction or module.It can implement the various functions disclosed herein with these program instructions, although can be alternatively In the middle function disclosed in realizing some or all of the application specific circuitry (for example, ASIC or FPGA) of computer system.Described In the case that computer system includes multiple calculating equipment, these equipment can with but need not be and cooperate jointly.Can pass through by Such as the physical storage device of solid state memory chip and/or disk is transformed to different conditions, for good and all stores the disclosed side The result of method and task.

Unless context clearly requires otherwise, run through the whole instruction and claim, word " comprising " and " include, Etc. should be explained with the meaning of inclusive, and the meaning of nonexcludability or exhaustive；That is, with " including but not limited to " Meaning is explained.As usually used herein, word " coupling " reference can be directly connected to or by one or more cental elements Two or more elements of part connection.In addition, when used in this application, word " this paper ", " above ", " following " and similar The word of the meaning should refer to the application entirety, and not this Applicant's Abstract graph any specific part.When context allows, above specific It is in embodiment, using the word of singular or plural can also respectively include plural number or odd number.Mentioning two or more items List when word "or", which covers to the following explanation of the whole of the word: any item in list, complete in list Any combination of portion and the item in list.Word " exemplary " is used exclusively herein and " serves as example, use-case or reality to refer to Example ".Any implementation for being described herein as " exemplary " need not be construed to other implementations that are better than or are better than.

The disclosure is not limited to implementation shown in this article.Various repair is carried out to implementation described in the displosure Change, be for a person skilled in the art very it will be apparent that and generic principles defined herein can be applied to other realities Existing mode, without departing from the spirit or scope of the displosure.The introduction of present invention provided herein can be applied to other methods And system, and be not limited to above-mentioned method and system, and can combine element and the behavior of above-mentioned various embodiments with More embodiments are provided.Therefore, novel methods as described herein and system can be realized in the form of various other；In addition, Various omissions, substitutions and changes can be carried out to the form of methods described herein and system, without departing from the spirit of the disclosure. The attached claims and its equivalent are intended to cover the form or variation that these can fall into spirit and scope of the present disclosure.

Claims (16)

1. a kind of digital analog converter, comprising:

First circuit is configured to execute increased bandwidth of first operation to generate the digital analog converter, first circuit Comprising being configured as executing the hybrid circuit of mixed mode operations；And

Second circuit is configured to execute digital signal the second operation to generate the analog signal after conversion, the second circuit It is further configured to reduce or eliminate image in the increased bandwidth, the second circuit includes logical with the hybrid circuit The time interleaving d convertor circuit of letter, the time interleaving d convertor circuit include multiple samplings and holding circuit, Each sampling and holding circuit are configured to receive the corresponding part of the digital signal and generate the analog signal after conversion Corresponding part, the hybrid circuit are the multiplier circuit communicated with the multiple sampling and holding circuit, the mixed mode Operation is that the operation of product signal is generated based on the signal for inputting the hybrid circuit.

2. digital analog converter as described in claim 1 is configured to wherein first circuit further comprises up-sampling circuit With coefficient n up-sampling input signal to generate the digital signal, n is real number.

3. digital analog converter as claimed in claim 2, wherein the time interleaving d convertor circuit also include with it is described The clock of multiple samplings and holding circuit communication, the clock is configured to the multiple sampling and holding circuit is provided when interlocking Clock signal.

4. digital analog converter as claimed in claim 3, wherein the time interleaving d convertor circuit further includes and prolongs Slow circuit is configured at least one of described staggered clock signal and provides delay.

5. digital analog converter as claimed in claim 2, wherein executing the mixed mode operations in analog domain.

6. digital analog converter as claimed in claim 5, wherein the hybrid circuit includes and the multiple sampling and holding electricity The multiplier circuit of each of road communication, each multiplier circuit are configured to connect from its corresponding sampling and holding circuit Analog signal and mix clock signal after receiving the conversion, each multiplier circuit are further configured to based on the conversion Analog signal and the mix clock signal afterwards generates product signal.

It further comprise being communicated with each of multiple multiplier circuits 7. digital analog converter as claimed in claim 6 Summing circuit, the summing circuit are configured to receive the product signal from its corresponding multiplier circuit and turn for the digital-to-analogue Parallel operation generates analog output signal.

8. digital analog converter as claimed in claim 2, wherein executing the mixed mode operations in the digital domain.

9. digital analog converter as claimed in claim 8, wherein the hybrid circuit includes and the multiple sampling and holding electricity Each of road input communication multiplier circuit, the multiplier circuit be configured to receive up-sampling digital signal and Mix clock signal, the multiplier circuit are further configured to digital signal and the mix clock based on the up-sampling Signal is that the multiple sampling and holding circuit generate product signal.

10. digital analog converter as claimed in claim 9, further comprise with it is each in the multiple sampling and holding circuit The switching circuit of a output communication, the switching circuit are configured to receive every in the multiple sampling and holding circuit Analog signal and staggered clock signal after one conversion, the switching circuit are further configured to the digital-to-analogue Converter circuit generates analog output signal.

11. digital analog converter as claimed in claim 10, wherein being supplied to the staggered clock signal of the switching circuit It is to be mentioned from the clock for the time interleaving digital analog converter for providing staggered clock signal to the multiple sampling and holding circuit It supplies.

12. a kind of method for converting digital signals into analog signal, which comprises

The first operation is executed to generate the increased bandwidth of radiofrequency signal, first operation includes mixed mode operations, described Mixed mode operations are to generate the operation of product signal；And

Second operation is executed to the digital signal to generate analog signal, second operation is further in the increased band Image is reduced or eliminated in width, second operation is operated comprising the digital-to-analogue conversion of time interleaving, the digital-to-analogue of the time interleaving Conversion operation includes multiple samplings and holding operation, each samples and keep correspondence of the operation comprising receiving the digital signal Part and the corresponding part for generating the analog signal.

13. method as claimed in claim 12 further comprises up-sampling input signal to generate the digital signal.

14. method as claimed in claim 13, wherein executing the mixed mode operations in numeric field or analog domain.

15. method as claimed in claim 14 further comprises the output for merging the digital-to-analogue conversion operation of the time interleaving, Or one in the output of the digital-to-analogue conversion operation of the selection time interleaving.

16. a kind of baseband subsystems, comprising:

Processor is configured to generate digital signal；And

Digital analog converter is configured to being converted to the digital signal into radiofrequency signal, and the digital analog converter includes the first circuit, It is configured to execute increased bandwidth of first operation to generate the digital analog converter, first circuit includes to be configured as holding The hybrid circuit of row mixed mode operations, the digital analog converter further include second circuit, are configured to the number letter Number execute second operation to generate the radiofrequency signal for representing the digital signal, the second circuit is further configured to described Image is reduced or eliminated in increased bandwidth, the second circuit includes that the time interleaving digital-to-analogue communicated with the hybrid circuit turns Converter circuit, the time interleaving d convertor circuit include multiple samplings and holding circuit, each sampling and holding are electric Road is configured to receive the corresponding part of the digital signal and generates the corresponding part of the radiofrequency signal, and the hybrid circuit is The multiplier circuit communicated with the multiple sampling and holding circuit, the mixed mode operations are electric based on the mixing is inputted The signal on road generates the operation of product signal.