CN104125171A - Switching fabric and egress traffic processing method thereof - Google Patents
Switching fabric and egress traffic processing method thereof Download PDFInfo
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- CN104125171A CN104125171A CN201410163188.1A CN201410163188A CN104125171A CN 104125171 A CN104125171 A CN 104125171A CN 201410163188 A CN201410163188 A CN 201410163188A CN 104125171 A CN104125171 A CN 104125171A
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Abstract
A switching fabric of a network device has a load dispatcher, a plurality of store units, a storage device, a plurality of fetch units, and a load assembler. Each of the store units is used to perform a write operation upon the storage device. Each of the fetch units is used to perform a read operation upon the storage device. The load dispatcher is used to dispatch ingress traffic to the store units, wherein a data rate between the load dispatcher and each of the store units is lower than a data rate of the ingress traffic. The load assembler is used to collect outputs of the fetch units to generate egress traffic, wherein a data rate between the load assembler and each of the fetch units is lower than a data rate of the egress traffic.
Description
[technical field]
The embodiment that the present invention discloses has the forwarding (forwarding) about package, espespecially switch architecture of a kind of network equipment (switching fabric) and associated method, wherein this switch architecture uses memory cell and the extraction unit of multiple clock rates that operate in reduction.
[background technology]
The network switch is a kind of computer network device that links different electronic installations.For instance, the network switch can receive the input package being produced by the first electronic installation being connected, and received package is modified/do not modified, and only sends the specified second electronic device of this package to.In general, this network switch has packet buffer with to cushioning from the packet data of the received package of inbound port, and the plurality of package being stored in this packet buffer is forwarded to outbound port.For example, when the wire rate (line rate) too high (10Gbps or 100Gbps) of each inbound port and outbound port, and for example, when inbound port and outbound port quantity are quite large (64 or 128), this packet buffer is carried out to access and need to operate in very high clock rate, thereby need the clock of a large amount of time design chips, and may affect manufacture output (manufacture yield).
[summary of the invention]
In view of this, spy of the present invention provides following technical scheme:
The embodiment of the present invention provides a kind of switch architecture, for network equipment, includes storage device, multiple memory cell, multiple extraction unit, load dispatch device and load assembler.Wherein each memory cell is used for carrying out write operation for storage device; Each extraction unit is used for carrying out read operation for storage device; Load dispatch device is used for dispatching the inlet flow rate of multiple memory cell, and wherein the message transmission rate between load dispatch device and each memory cell is lower than the message transmission rate of inlet flow rate; And the output that load assembler is used for collecting multiple extraction units to be to produce rate of discharge, wherein the message transmission rate between load assembler and each extraction unit is lower than the message transmission rate of rate of discharge.
The embodiment of the present invention separately provides a kind of inlet flow rate processing method, for the treatment of the inlet flow rate of network equipment, include scheduling inlet flow rate to multiple memory cell, wherein the input message transmission rate of each memory cell is lower than the message transmission rate of inlet flow rate; Come to carry out write operation for storage device by each memory cell; With multiple extraction units each come for storage device carry out read operation; And in conjunction with the output of multiple extraction units to produce rate of discharge, wherein the output message transmission rate of each extraction unit is lower than the message transmission rate of rate of discharge.
Above-described switch architecture and inlet flow rate processing method can be processed by the clock speed reducing the flow of network equipment, easily reach the demand of chip sequential and improve and manufacture output.
[brief description of the drawings]
Fig. 1 is the embodiment of network equipment of the present invention.
Fig. 2 is the first embodiment of datum plane switch architecture of the present invention.
Fig. 3 is the second embodiment of datum plane switch architecture of the present invention.
Fig. 4 is the 3rd embodiment of datum plane switch architecture of the present invention.
Fig. 5 is the 4th embodiment of datum plane switch architecture of the present invention.
Fig. 6 is the first embodiment of control plane switch architecture of the present invention.
Fig. 7 is the flow chart of the embodiment of the method for the inlet flow rate of processing network equipment of the present invention.
[embodiment]
In the middle of specification and claims, use some vocabulary to censure specific assembly.One of skill in the art should understand, and same assembly may be called with different nouns by manufacturer.This specification and claims book is not used as distinguishing the mode of assembly with the difference of title, but the difference in function is used as the benchmark of distinguishing with assembly.In the whole text, in the middle of specification and claims, be open term mentioned " comprising ", therefore should be construed to " comprise but be not limited to ".In addition, " coupling " word comprises directly any and is indirectly electrically connected means at this.Therefore, be coupled to the second device if describe first device in literary composition, represent that first device can directly be electrically connected in the second device, or be indirectly electrically connected to the second device through other device or connection means.
Fig. 1 is the embodiment of network equipment of the present invention.For instance, but be not limited to this, network equipment 100 can be the network switch.Network equipment 100 include multiple inbound port 101_1,101_2 ... 101_N, multiple outbound port 102_1,102_2 ... 102_N, datum plane switch architecture 103, controller 104 and control plane switch architecture 105, wherein datum plane switch architecture 103 has packet buffer 106, and control plane switch architecture 105 has queue module (queue module) 107.Packet buffer 106 be used for store by inbound port 101_1,101_2 ... the packet data of the package that 101_N receives.Suppose each inbound port 101_1,101_2 ... the wire rate (message transmission rate (data rate)) of 101_N is R, and the equivalent line speed (message transmission rate) of the inlet flow rate of datum plane switch architecture 103 (traffic) (inputting the data flow of the packet data of package) is N × R.For instance, N can be 64 or 128, R can be 10Gbps or 100Gbps.Thus, many input interfaces of datum plane switch architecture 103 operate in the first clock rate CLK
1.Owing to having used multiplexed data bus, the clock of each data/address bus can not need to operate in high-frequency clock speed.
In this embodiment, datum plane switch architecture 103 is that the switch architecture framework based on proposed designs, and the switch architecture framework that wherein proposed can allow inlet flow rate at second clock speed CLK
2under carry out packet buffer and write, wherein CLK
1might not be higher than CLK
2.Can be learnt by Fig. 1, because the wire rate (message transmission rate) of each outbound port 102_1～102_N is also R, therefore the multiple output interface of datum plane switch architecture 103 also operates in this first clock rate CLK
1.For example, operate in higher clock rate than traditional datum plane switch architecture design its internal circuit element (single memory cell, single extraction unit and packet buffer), the internal circuit element (for example multiple memory cell, multiple extraction unit and/or a packet buffer) of the datum plane switch architecture 103 proposing is allowed to operate in lower clock rate.
Controller 104 can have multiple control circuits controls the package handoff functionality of network equipment 100.For instance, but be not limited to this, controller 104 can have (en-queuing) circuit of joining the team, scheduler (scheduler) and (de-queuing) circuit of falling out.This circuit of joining the team is used for the control information of package received inbound port 101_1～101_N (for example each receives the package identifier of package) to be added to queue module 107.This goes out column circuits and is used for the control information of package to take out from queue module 107, and wherein this output that goes out column circuits can be controlled the actual packaging data-flow between packet buffer 106 and outbound port 102_1～102_N.
As seen from Figure 1, many input interfaces of control plane switch architecture 105 operate in the 3rd clock rate CLK
3.Owing to having used multiplexed data bus, the clock of each data/address bus can not need to operate in high-frequency clock speed.Specifically, the equivalent line speed (message transmission rate) of this inlet flow rate (inputting the data flow of the packet data of package) is N × R.Because control plane switch architecture 105 is that another switch architecture framework based on proposed designs, therefore can allow at the 4th clock rate CLK
4under forward (forwarding en-queuing) event, the wherein CLK that join the team
3might not be higher than CLK
4.It should be noted, consider CLK depending on actual design
3can equate or be not equal to CLK
1.Can be learnt by Fig. 1, many input interfaces of control plane switch architecture 105 also operate in the 3rd clock rate CLK
3.Specifically, the equivalent line speed (message transmission rate) of rate of discharge (exporting the data flow of the control information of package) is N × R.Because control plane switch architecture 105 is that switch architecture framework based on proposed designs, therefore can allow the operation of the event of falling out under the clock rate reducing.
As from the foregoing, datum plane switch architecture 103 can be processed inlet flow rate and the rate of discharge in the datum plane of network equipment 100 by the clock rate reducing, and control plane switch architecture 105 can be processed inlet flow rate and the rate of discharge in the control plane of network equipment 100 by the clock rate reducing.Therefore be easier to reach the demand of chip sequential and improve and manufacture output.In following paragraph, will further describe for the details of datum plane switch architecture 103 and control plane switch architecture 105.
Fig. 2 is the schematic diagram of the first embodiment of datum plane switch architecture of the present invention.Datum plane switch architecture 103 shown in Fig. 1 can utilize the datum plane switch architecture 200 shown in Fig. 2 to realize.As shown in Figure 2, datum plane switch architecture 200 includes load dispatch device (dispatcher) 202, multiple memory cell 204_1,204_2 ... 204_K, the storage device 206 that utilizes one-port memory (a for example port static RAM) to realize, multiple extraction unit 208_1,208_2 ... 208_K and load assembler 210.In this embodiment, this storage device (being one-port memory 206) is as the packet buffer 106 shown in Fig. 1.Each memory cell 204_1,204_2 ... 204_K is used for carrying out write operation for this storage device (being single port storage device 206).Each extraction unit 208_1,208_2 ... 208_K is used for carrying out read operation for this storage device (being single port storage device 206).
Preferably, one-port memory 206 can adopt package buffer pool (packet buffer banking) framework.Specifically, one-port memory 206 has M storehouse, wherein M is greater than 1 integer, in the time that arbitrary extraction unit 208_1～208_K carries out access to the storehouse of this packet buffer, owing to having adopted the mechanism of package buffer pool, one of memory cell 204_1～204_K just can carry out access to other different sink of this packet buffer.In other words, can come the different storehouse of access simultaneously (read/write) to promote the throughput of packet-switched with package buffer pool.Therefore, memory cell 204_1～204_K and extraction unit 208_1～208_K can select the different sink of one-port memory 206 to carry out access packet data, allow well memory cell 204_1～204_K and extraction unit 208_1～208_K be able to the mnemon of read/write buffers simultaneously.
In this embodiment, realize this packet buffer with one-port memory 206.Because one-port memory (1RW) has single group address and control, so once can only carry out single access (read/write).In other words, one-port memory 206 only has a read port.Because packet-switched throughput is limited by the read operation of extraction unit 208_1～208_K, can only use the one-port memory 206 of a read port by operating under full speed clock rate (being the maximum clock speed that one-port memory 206 is supported) FS, to reach maximum packet-switched throughput simultaneously.
Load dispatch device 202 is used for receiving inlet flow rate (inputting the data flow of the packet data of package) PKT
dATA_ I, and by inlet flow rate PKT
dATA_ I is dispatched to memory cell 204_1～204_K.In this embodiment, the number of memory cell 204_1～204_K is K.Therefore, as inlet flow rate PKT
dATAwhen the message transmission rate of _ I is N × R, the message transmission rate between load dispatch device 202 and each memory cell 204_1～204_K is
in other words, the message transmission rate between load dispatch device 202 and each memory cell 204_1～204_K is lower than inlet flow rate PKT
dATAthe message transmission rate of _ I.Than directly processing inlet flow rate PKT with higher data transmission rate N × R
dATA_ I, utilizes lower data transmission rate
processing a part of inlet flow rate can allow this storage device (for example to operate in lower clock rate
).
The output that load assembler 210 is used for collecting extraction unit 208_1～208_K is to produce rate of discharge PKT
dATA_ E (exporting the data flow of the packet data of package).In this embodiment, the number of extraction unit 208_1～208_K is K.Therefore, as rate of discharge PKT
dATAwhen the message transmission rate of _ E is N × R, the message transmission rate between load assembler 210 and each extraction unit 208_1～208_K is
in other words, the message transmission rate between load assembler 210 and each extraction unit 208_1～208_K is lower than rate of discharge PKT
dATAthe message transmission rate of _ E.Than directly processing rate of discharge PKT with higher data transmission rate N × R
dATA_ E, utilizes lower data transmission rate
processing a part of rate of discharge can allow this extraction unit (for example to operate in lower clock rate
).
About the datum plane switch architecture 200 shown in Fig. 2, wherein memory cell 204_1～204_K and extraction unit 208_1～208_K are allowed to operate in the clock rate of reduction.So, be easier to reach the demand of chip sequential and improve and manufacture output.
Fig. 3 is the schematic diagram of the second embodiment of datum plane switch architecture of the present invention.Datum plane switch architecture 103 shown in Fig. 1 can utilize the datum plane switch architecture 300 shown in Fig. 3 to realize.The design of datum plane switch architecture 300 is similar with datum plane switch architecture 200, and main difference is that the storage device (being packet buffer) in datum plane switch architecture 300 for example, realizes with dual-ported memory (two-port memory) (dual-port static random access memory) 306.Write inbound port because dual-ported memory (1R1W) has a read port and one for address and control, therefore can reach double access of same time (read and write).As mentioned above, because packet-switched throughput is limited by the read operation of extraction unit 208_1～208_K, dual-ported memory 306 can only be write inbound port with a read port and one simultaneously and operate under full speed clock rate (being the maximum clock speed that one-port memory 306 is supported) FS, to reach maximum packet-switched throughput.
Fig. 4 is the schematic diagram of the 3rd embodiment of datum plane switch architecture of the present invention.Datum plane switch architecture 103 shown in Fig. 1 can utilize the datum plane switch architecture 400 shown in Fig. 4 to realize.The design of datum plane switch architecture 400 is similar with datum plane switch architecture 200, and main difference is that the storage device (being packet buffer) in datum plane switch architecture 400 for example, realizes with twin port memory (dual-port memory) (twin port static RAM) 406.Because twin port memory (2RW) has two group addresss and control, therefore can reach double access of same time (two read, two write or read and write).As mentioned above, because packet-switched throughput is limited by the read operation of extraction unit 208_1～208_K, twin port memory 406 can carry out the clock rate in reduction with two read ports simultaneously
under operate, wherein FS is clock rate (being the maximum clock speed that one-port memory 306 is supported) at full speed.It should be noted, the clock rate that 400 uses of datum plane switch architecture reduce (
) just can reach the same packet of datum plane switch architecture 300 under full speed clock rate (being FS) exchange throughput.
Fig. 5 is the schematic diagram of the 4th embodiment of datum plane switch architecture of the present invention.Datum plane switch architecture 103 shown in Fig. 1 can utilize the datum plane switch architecture 500 shown in Fig. 5 to realize.The design of datum plane switch architecture 500 is similar with datum plane switch architecture 200, and main difference is that the storage device (being packet buffer) in datum plane switch architecture 500 for example, realizes with multiport memory (multi-port memory) (multiport static RAM) 506.Because multiport memory (nRmW or nRW) has multiple read/write port (be n read port and m and write inbound port or n read port and the individual inbound port of writing of n) for address and control, therefore can reach same time multiple access (is that n reads and m writes; Or n read/write), wherein, in nRmW, n+m was greater than for 2 (or in nRW, n is not less than 2).About multiport memory (nR/mW), it has multiple read/write port (be n read port and m and write inbound port) for address and control, therefore can reach same time multiple access (being that n reads or m writes).In this embodiment, no matter multiport memory 506 is nRmW form, nRW form or nR/mW form, and the number of read port equals or is greater than 2 (being n≤2).It should be noted, consider depending on actual design, multiport memory 506 can be multiport memory or the algorithm multiport memory of physics.As mentioned above, because packet-switched throughput is limited by the read operation of extraction unit 208_1～208_K, multiport memory 506 can use the individual read port of n (n≤2) to carry out the clock rate reducing simultaneously
under operate, wherein FS is clock rate (being the maximum clock speed that one-port memory 506 is supported) at full speed.It should be noted, the clock rate that 500 uses of datum plane switch architecture reduce (
) just can reach the same packet of datum plane switch architecture 300 under full speed clock rate (being FS) exchange throughput.
Fig. 6 is the schematic diagram of the first embodiment of control plane switch architecture of the present invention.Control plane switch architecture 105 shown in Fig. 1 can utilize the control plane switch architecture 600 shown in Fig. 6 to realize.As shown in Figure 6, control plane switch architecture 600 includes load dispatch device 602, multiple memory cell 604_1,604_2 ... 604_K, storage device 606, multiple extraction unit 608_1,608_2 ... 608_K and load assembler 610.Wherein this storage device 606 include wire matrix 612 and multiple queue 614_1,614_2 ... 614_K.In the present embodiment, multiple queue 614_1,614_2 ... 614_K is as the queue module 107 shown in Fig. 1.Each memory cell 604_1,604_2 ... 604_K is used for carrying out write operation for storage device 606.Each extraction unit 608_1,608_2 ... 608_K is used for carrying out read operation for storage device 606.
Load dispatch device 602 is used for receiving inlet flow rate (inputting the data flow of the control information of package) PKT
iNF_ I, and by inlet flow rate PKT
iNF_ I is dispatched to memory cell 604_1～604_K.In this embodiment, the number of memory cell 604_1～604_K is K.Therefore, as inlet flow rate PKT
iNFwhen the message transmission rate of _ I is N × R, the message transmission rate between load dispatch device 602 and each memory cell 604_1～604_K is
in other words, the message transmission rate between load dispatch device 602 and each memory cell 604_1～604_K is lower than inlet flow rate PKT
iNFthe message transmission rate of _ I.Than directly processing inlet flow rate PKT with higher data transmission rate N × R
iNF_ I, utilizes lower data transmission rate
processing a part of inlet flow rate can allow this storage device to operate in lower clock rate.
The output that load assembler 610 is used for collecting extraction unit 608_1～608_K is to produce rate of discharge PKTINF_E (exporting the data flow of the control information of package).In this embodiment, the number of extraction unit 608_1～608_K is K.Therefore, as rate of discharge PKT
iNFwhen the message transmission rate of _ E is N × R, the message transmission rate between load assembler 610 and each extraction unit 608_1～608_K is
in other words, the message transmission rate between load assembler 610 and each extraction unit 608_1～608_K is lower than rate of discharge PKT
iNFthe message transmission rate of _ E.Than directly processing rate of discharge PKT with higher data transmission rate N × R
iNF_ E, utilizes lower data transmission rate
processing a part of rate of discharge can allow this extraction unit to operate in lower clock rate.
About the control plane switch architecture 600 shown in Fig. 6, wherein memory cell 604_1～604_K and extraction unit 608_1～608_K are allowed to operate in the clock rate of reduction.So, be easier to reach the demand of chip sequential and improve and manufacture output.
The same packet data of a package can be forwarded to a destination device or multiple destination device.Therefore, the control information of this package (for example this package identification) should suitably be added a queue entirety or Multiple input queues entirety.In order to reach this object, between the queue 614_1～614_K of storage device 606 and memory cell 604_1～604_K, wire matrix 612 is set.Can be learnt by Fig. 6, wire matrix 612 have multiple input node 611_1,611_2 ... 611_K and multiple output node 613_1,613_2 ... 613_K.Input node 611_1,611_2 ... 611_K is connected to respectively memory cell 604_1～604_K, output node 613_1,613_2 ... 613_K is connected to respectively queue 614_1～614_K.Each input node 611_1,611_2 ... 611_K can be connected to one or multiple output node.In other words, one of memory cell 604_1～604_K can be by the same event forwarding at least a portion (i.e. part or whole) to queue 614_1～614_K of joining the team.In the situation that particular packet exchanges, memory cell 604_1～604_K can be respectively by the event forwarding of respectively joining the team to same queue.But each extraction unit 608_1～608_K once only can provide the single event of falling out.In this embodiment, each queue 614_1～614_K use has a read port and K the multiport memory (for example multiport static RAM) of writing inbound port realized.
Fig. 7 is the flow chart of the embodiment of the method for the inlet flow rate of processing network equipment of the present invention.If can reach substantially identical result, might not carry out according to the sequence of steps in the flow process shown in Fig. 7, and the step shown in Fig. 7 not necessarily will carry out continuously, that is other steps also can be inserted wherein.In addition, some step in Fig. 7 can be omitted according to different embodiment or design requirement.The method of Fig. 7 can be applied in one of datum plane switch architecture or control plane switch architecture, and is described below.
Step 702: scheduling inlet flow rate (for example digital data stream or control data flow) is to multiple memory cell.
Step 704: come to carry out write operation for storage device by each memory cell.
Step 706: come to carry out read operation for this storage device with each extraction unit.
Step 708: in conjunction with the output of the plurality of extraction unit for example, to produce rate of discharge (digital data stream or control data flow).
Those skilled in the art, reading after the above-mentioned relevant paragraph about network equipment 100, should be able to understand the details of method 702～708, immediately therefore just further do not repeat for details at this.
The foregoing is only preferred embodiment of the present invention, the equivalence that those skill in the art related make according to spirit of the present invention changes and amendment, all should be encompassed in claims.
Claims (20)
1. a switch architecture, for network equipment, described switch architecture includes:
Storage device;
Multiple memory cell, wherein each memory cell is used for carrying out write operation for described storage device;
Multiple extraction units, wherein each extraction unit is used for carrying out read operation for described storage device;
Load dispatch device, is used for dispatching the inlet flow rate of described multiple memory cell, and the message transmission rate between wherein said load dispatch device and each memory cell is lower than the message transmission rate of described inlet flow rate; And
Load assembler, the output that is used for collecting described multiple extraction units is to produce rate of discharge, and the message transmission rate between wherein said load assembler and each extraction unit is lower than the message transmission rate of described rate of discharge.
2. switch architecture according to claim 1, is characterized in that, described switch architecture is datum plane switch architecture, and described inlet flow rate and described rate of discharge are the data flow of the packet data of package.
3. switch architecture according to claim 2, is characterized in that, described storage device is packet buffer, has multiple storehouses; And in the time of the first storehouse of packet buffer described in the access of one of described multiple extraction units, the second storehouse of packet buffer described in the access for a moment of described multiple memory cell, wherein said the second storehouse is different from described the first storehouse.
4. switch architecture according to claim 2, is characterized in that, described storage device is packet buffer, realized by the one-port memory with a read port, and the clock rate operation at full speed of described one-port memory.
5. switch architecture according to claim 2, is characterized in that, described storage device is packet buffer, realized by the dual-ported memory with a read port, and the clock rate operation at full speed of described dual-ported memory.
6. switch architecture according to claim 2, it is characterized in that, described storage device is packet buffer, realized by the twin port memory with two read ports, and described twin port memory is with clock rate FS/2 operation, and wherein FS is the full speed clock rate of described twin port memory.
7. switch architecture according to claim 2, it is characterized in that, described storage device is packet buffer, realized by the multiport memory with n read port, and described multiport memory operates with clock rate FS/n, the full speed clock rate that wherein FS is described multiport memory, and n is greater than/equals 2 integer.
8. switch architecture according to claim 1, is characterized in that, described switch architecture is control plane switch architecture, and the data flow of described inlet flow rate and the described rate of discharge control information that is package.
9. switch architecture according to claim 8, is characterized in that, described storage device includes:
Wire matrix, has multiple input nodes and multiple output node, and wherein said multiple input nodes are coupled to respectively described multiple memory cell; And
Multiple queues, are coupled to respectively described multiple output node, and wherein each queue is coupled between one of one of described multiple output nodes and described multiple extraction units.
10. switch architecture according to claim 9, is characterized in that, each queue realizes to have a read port and K the multiport memory of writing inbound port, and K equals the number of described multiple memory cell.
11. 1 kinds of inlet flow rate processing methods, for the treatment of the inlet flow rate of network equipment, include:
Dispatch described inlet flow rate to multiple memory cell, wherein the input message transmission rate of each memory cell is lower than the message transmission rate of described inlet flow rate;
Come to carry out write operation for storage device by each memory cell;
Come to carry out read operation for described storage device by each of multiple extraction units; And
In conjunction with the output of described multiple extraction units, to produce rate of discharge, wherein the output message transmission rate of each extraction unit is lower than the message transmission rate of described rate of discharge.
12. inlet flow rate processing methods according to claim 11, is characterized in that, described method is applied to the datum plane of described network equipment, and the data flow of described inlet flow rate and the described rate of discharge packet data that is package.
13. inlet flow rate processing methods according to claim 12, is characterized in that, described storage device is packet buffer, has multiple storehouses; And in the time of the first storehouse of packet buffer described in the access of one of described multiple extraction units, the second storehouse of packet buffer described in the access of one of described multiple memory cell, wherein said the second storehouse is different from described the first storehouse.
14. inlet flow rate processing methods according to claim 12, is characterized in that, described storage device is packet buffer, realized, and described method separately include by the one-port memory with a read port:
Set the clock rate operation at full speed of described one-port memory.
15. inlet flow rate processing methods according to claim 12, is characterized in that, described storage device is packet buffer, realized, and described method separately include by the dual-ported memory with a read port:
Set the clock rate operation at full speed of described dual-ported memory.
16. inlet flow rate processing methods according to claim 12, is characterized in that, described storage device is packet buffer, realized, and described method separately include by the twin port memory with two read ports:
Set described twin port memory with clock rate FS/2 operation, wherein FS is the full speed clock rate of described twin port memory.
17. inlet flow rate processing methods according to claim 12, is characterized in that, described storage device is packet buffer, realized, and described method separately include by the multiport memory with n read port:
Set described multiport memory with clock rate FS/n operation, the full speed clock rate that wherein FS is described multiport memory, and n is greater than/equals 2 integer.
18. inlet flow rate processing methods according to claim 11, is characterized in that, described method is applied to the control plane of described network equipment, and the data flow of described inlet flow rate and the described rate of discharge control information that is package.
19. inlet flow rate processing methods according to claim 18, is characterized in that, described storage device includes wire matrix and multiple queue, and described method separately includes:
Multiple input nodes of described wire matrix are coupled to respectively to described multiple memory cell; And
Multiple output nodes of described wire matrix are coupled to respectively to described multiple queue, and wherein each queue is coupled between one of one of described multiple output nodes and described multiple extraction units.
20. inlet flow rate processing methods according to claim 19, is characterized in that, each queue realizes to have a read port and K the multiport memory of writing inbound port, and K equals the number of described multiple memory cell.
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| US201361816258P | 2013-04-26 | 2013-04-26 | |
| US61/816,258 | 2013-04-26 | ||
| US14/203,543 US20140321471A1 (en) | 2013-04-26 | 2014-03-10 | Switching fabric of network device that uses multiple store units and multiple fetch units operated at reduced clock speeds and related method thereof |
| US14/203,543 | 2014-03-10 |
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| US20050207436A1 (en) * | 2004-03-18 | 2005-09-22 | Anujan Varma | Switching device based on aggregation of packets |
| US20060106946A1 (en) * | 2004-10-29 | 2006-05-18 | Broadcom Corporation | Method and apparatus for hardware packets reassembly in constrained networks |
| US20070121499A1 (en) * | 2005-11-28 | 2007-05-31 | Subhasis Pal | Method of and system for physically distributed, logically shared, and data slice-synchronized shared memory switching |
| CN101873253A (en) * | 2009-04-27 | 2010-10-27 | Lsi股份有限公司 | Buffered crossbar switch system |
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| CN110290072A (en) * | 2018-03-19 | 2019-09-27 | 华为技术有限公司 | Flow control methods, device, the network equipment and storage medium |
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