CN104124270B - Heterojunction bipolar transistor layout structure - Google Patents
Heterojunction bipolar transistor layout structure Download PDFInfo
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- CN104124270B CN104124270B CN201310146581.5A CN201310146581A CN104124270B CN 104124270 B CN104124270 B CN 104124270B CN 201310146581 A CN201310146581 A CN 201310146581A CN 104124270 B CN104124270 B CN 104124270B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
Abstract
Disclosed is a heterojunction bipolar transistor layout structure including one or more heterojunction bipolar transistors, each of which comprises a base electrode, an emitter electrode and a collector electrode. A passive layer, a first dielectric layer, a collector re-distribution layer, one or more emitter copper pillars and one or more collector copper pillars are disposed above the heterojunction bipolar transistors; the passive layer comprises an emitter welding pad and a collector welding pad; the first dielectric layer is provided with one or more emitter guide holes and collector guide holes which are respectively located above the emitter welding pad and the collector welding pad; the emitter copper pillars are located on the emitter guide holes and are electrically connected to the emitter electrode; and the collector copper pillars are arranged above the collector re-distribution layer and electrically connected to the collector electrode so that the layout of the emitter copper pillars and the collector copper pillars can be flexible and the heat dissipating efficiency of components can be simultaneously improved.
Description
Technical field
The present invention is a kind of relevant heterojunction bipolar transistor layout structure, espespecially a kind of to have redistribution layer simultaneously
The heterojunction bipolar transistor layout structure of (redistribution layer, RDL) and copper post.
Background technology
With flourishing for Mobile Communications industry, high-performance, the demand of the electronic component of small volume are also increasingly increased,
Because compound semiconductor heterojunction bipolar transistor integrated circuit has the advantages that high power, low noise, small size, at present
In being widely used in Mobile Communications electronic product, therefore, if the brilliant electricity of compound semiconductor heterojunction bipolar electricity can be improved
The performance and size on road, can effectively improve product competitiveness.
Traditional Flip Chip in the application of GaAs heterojunction bipolar transistor unit, in order to lift elements dissipate
Thermal characteristicss, copper post can be covered in the emitter-base bandgap grading top of element, and original plain conductor process technique of arranging in pairs or groups sets up the collection of element
Pole, base stage copper post, but due to the restriction for having minimum range on processing procedure between copper post, make component size to therefore suffer from limiting and nothing
Method reduces, and causes the space waste between copper post and copper post, and product competitiveness in the market is greatly reduced, additionally, because of heterojunction pair
The emitter-base bandgap grading of gated transistors is big with collector epitaxial layer height fall, height of the copper pillar is arranged thereon and is difficult unanimously, to cause wafer package
Shi Rongyi produces the problem of solder joint loose contact, limits the lifting of wafer package yield.
The content of the invention
Present invention is primarily targeted at provide it is a kind of have simultaneously redistribution layer (redistribution layer) with
The heterojunction bipolar transistor layout structure of copper post, by integrating Flip Chip and wire weight cloth technology, imitates element radiating
Rate is lifted, and the layout of emitter-base bandgap grading copper post and collector copper post has elasticity, and collocation is using having low-k and excellent flat
The dielectric material of smoothization ability, enables the emitter-base bandgap grading copper post in traditional Flip Chip to be contracted by with the difference in height of collector copper post, and then
Improving product yield.
Another object of the present invention is to provide it is a kind of have simultaneously redistribution layer (redistribution layer) with
The heterojunction bipolar transistor layout structure of copper post, it can utilize the elasticity of emitter-base bandgap grading copper post and collector copper post layout, and can fill
Divide using the passive device needed for die space setting circuit, reach the purpose of wafer size micro.
It is still another object of the present invention to provide it is a kind of have simultaneously redistribution layer (redistribution layer) with
The heterojunction bipolar transistor layout structure of copper post, it is by the height of filling up guide hole to compensate emitter-base bandgap grading copper post and collector copper post
Difference, further improving product yield.
It is that, up to above-mentioned purpose, the present invention provides a kind of heterojunction bipolar transistor layout structure, and it includes one or more
Heterojunction bipolar transistor, a passive layer, one first dielectric layer, a collector redistribution layer, one or more emitter-base bandgap grading copper posts and
One or more collector copper posts, wherein aforementioned one or more heterojunction bipolar transistor-baseds are formed at a surface, wherein often
One heterojunction bipolar transistor includes a base electrode, an emitter-base bandgap grading electrode and a collector electrode；Aforementioned passive layer is shape
Into in heterojunction bipolar transistor top, including an emitter-base bandgap grading weld pad and a collector weld pad, wherein aforementioned emitter-base bandgap grading weld pad system is electric
Property is connected to each emitter-base bandgap grading electrode, and aforementioned collector weld pad is electrically coupled to each collector electrode；Aforementioned first dielectric
Series of strata are covered on the passive layer, and form the emitter-base bandgap grading of one or more insertions first dielectric layer in aforementioned emitter-base bandgap grading weld pad top
Guide hole, and form the collector guide hole of one or more insertions first dielectric layer in the collector weld pad top；Aforementioned collector redistribution
Layer is located on aforementioned first dielectric layer, and is extended into aforementioned collector guide hole and be electrically connected at aforementioned collector weld pad；Before
Each stated in emitter-base bandgap grading copper post is to be located at least one aforementioned emitter-base bandgap grading guide hole top and fill up the emitter-base bandgap grading guide hole and be electrically connected with
In aforementioned emitter-base bandgap grading weld pad；And aforementioned one or more collector copper posts are to be located on aforementioned collector redistribution layer and be electrically connected at this
Collector redistribution layer.Additionally, a kind of heterojunction bipolar transistor layout structure provided by the present invention, can be situated between in aforementioned first
An emitter-base bandgap grading redistribution layer is included in electric layer, it extends between aforementioned emitter-base bandgap grading copper post and emitter-base bandgap grading guide hole and is electrically connected at aforementioned
Emitter-base bandgap grading weld pad.
It is the purpose up to size micro, the present invention provides several layout designs in above-mentioned heterojunction bipolar transistor layout
Copper post and the passive device needed for circuit are formed in structure：
Aforementioned collector weld pad is adjacent with the emitter-base bandgap grading copper post；Each in aforementioned collector copper post is to be located at aforementioned at least one
On individual aforementioned collector guide hole and fill up the collector guide hole；Aforementioned heterojunction bipolar transistor layout structure further include one or
Multiple electric capacity and resistance, are coupled to aforementioned heterojunction bipolar transistor, and one or more electric capacity and resistance be arranged at it is aforementioned
Between collector weld pad and emitter-base bandgap grading weld pad in the passive layer in region；
Aforementioned collector weld pad is adjacent with the emitter-base bandgap grading copper post；Aforementioned collector copper post is formed on aforementioned collector weld pad,
Region outside aforementioned collector guide hole top；And aforementioned emitter-base bandgap grading copper post compensates emitter-base bandgap grading copper post and collector copper by filling up emitter-base bandgap grading guide hole
The difference in height of post；Aforementioned heterojunction bipolar transistor layout structure further includes one or more electric capacity and resistance, is coupled to aforementioned
Heterojunction bipolar transistor, and be arranged between aforementioned collector weld pad and emitter-base bandgap grading weld pad in the passive layer in region；
Extend the collector redistribution layer in above-mentioned heterojunction bipolar transistor layout structure, make the collector copper post can be from aforementioned
The position adjacent with emitter-base bandgap grading copper post moves to him sentences and makes full use of die space, and then reduces wafer size；Aforementioned collector is divided again
Layer of cloth forms a collector redistribution layer elongated area on aforementioned first dielectric layer, and aforementioned collector copper post is formed at aforementioned collection
Position on the redistribution layer elongated area of pole, beyond aforementioned collector guide hole top, and aforementioned emitter-base bandgap grading copper post is by filling up the emitter-base bandgap grading
Guide hole compensates the difference in height of the emitter-base bandgap grading copper post and collector copper post；Aforementioned heterojunction bipolar transistor layout structure further include one or
Multiple electric capacity and resistance, are coupled to aforementioned heterojunction bipolar transistor；Before aforementioned one or more electric capacity and resistance system are arranged at
In stating the passive layer between emitter-base bandgap grading weld pad and collector weld pad outside region, at neighbouring aforementioned emitter-base bandgap grading weld pad, or it is arranged at aforementioned emitter-base bandgap grading
In copper post lower section, the passive layer between aforementioned emitter-base bandgap grading weld pad and collector weld pad outside region, at neighbouring aforementioned emitter-base bandgap grading weld pad；
In addition the collector weld pad in above-mentioned heterojunction bipolar transistor layout structure is also may extend away, makes the collector guide hole can be from
Aforementioned adjacent position parallel with emitter-base bandgap grading guide hole moves to him sentences and makes full use of die space, and then reduces wafer size；It is aforementioned
Collector weld pad forms a collector weld pad elongated area in aforementioned passive layer, and at least one is in aforementioned one or more collector guide holes
It is formed on the collector weld pad elongated area, each in aforementioned collector copper post is prolonged positioned at least one collector weld pad
The collector guide hole is stretched on the collector guide hole of overlying regions and fills up, and aforementioned emitter-base bandgap grading copper post is by filling up the emitter-base bandgap grading guide hole compensation
The difference in height of the emitter-base bandgap grading copper post and collector copper post；Aforementioned heterojunction bipolar transistor layout structure further includes one or more electric capacity
And resistance, it is coupled to aforementioned heterojunction bipolar transistor；Aforementioned one or more electric capacity and resistance are disposed on aforementioned emitter-base bandgap grading weldering
In passive layer between pad and collector weld pad outside region, at neighbouring aforementioned emitter-base bandgap grading weld pad, or be arranged at below aforementioned emitter-base bandgap grading copper post,
In passive layer between aforementioned emitter-base bandgap grading weld pad and collector weld pad outside region, at neighbouring aforementioned emitter-base bandgap grading weld pad.
When implementing, aforesaid base plate is with compound semiconductor materials GaAs (GaAs), gallium nitride (GaN), carborundum
(SiC) or sapphire (sapphire) formed.
The present invention while offer there is redistribution layer and the heterojunction bipolar transistor layout structure of copper post really may be used
Expected purpose is reached, while radiating using emitter-base bandgap grading copper post, wafer size can be reduced, and the height point of copper post can be improved
Cloth, and then improve encapsulation yield.
It is that for can have a better understanding with effect the characteristics of the present invention, hereby mat embodiment coordinates after schema is specified in.
Description of the drawings
Figure 1A is a kind of plan structure of embodiment of heterojunction bipolar transistor layout structure provided by the present invention
Schematic diagram.
Figure 1B and 1C are the cross-sectional view of the dotted line AA ' and dotted line BB ' along Figure 1A.
Fig. 1 D are the vertical view knot of another kind of embodiment of heterojunction bipolar transistor layout structure provided by the present invention
Structure schematic diagram.
Fig. 1 E are the cross-sectional view of the dotted line AA ' along Fig. 1 D.
Fig. 1 F and Fig. 1 G are another two kinds of embodiments of heterojunction bipolar transistor layout structure provided by the present invention
Overlooking the structure diagram.
Fig. 2A and 2B are bowing for another kind of embodiment of heterojunction bipolar transistor layout structure provided by the present invention
The cross-sectional view of dotted line AA ' depending on structural representation and along 2A figures.
Fig. 2 C and 2D are bowing for another kind of embodiment of heterojunction bipolar transistor layout structure provided by the present invention
The cross-sectional view of dotted line AA ' depending on structural representation and along 2C figures.
Fig. 3 A and 3B are bowing for another two kinds of embodiments of heterojunction bipolar transistor layout structure provided by the present invention
Depending on structural representation.
Description of reference numerals：100 substrates；110 heterojunction bipolar transistors；111 collector layers；112 collector layers；113
Base layer；114 emitter layers；121 base electrodes；122 emitter-base bandgap grading electrodes；123 collector electrodes；130 passive layers；131 the first metal layers；
132 second metal layers；131a, 131b weld pad；132a emitter-base bandgap grading weld pads；132b collector weld pads；132c collector weld pads elongated area；
133rd, 134,135 coating；141 emitter-base bandgap grading redistribution layers；142 collector redistribution layers；142a collector redistribution layers elongated area；
151 first dielectric layers；152 second dielectric layers；161 emitter-base bandgap grading copper posts；162 collector copper posts；163rd, 164 soldered ball；Penetrate 171 pole guide holes；
172 collector guide holes；181 electric capacity；182 resistance.
Specific embodiment
Figure 1A -1C are a kind of signal of embodiment of heterojunction bipolar transistor layout structure provided by the present invention
Figure, wherein Figure 1B is the generalized section of the dotted line AA ' along Figure 1A, and Fig. 1 C are the generalized section of the dotted line BB ' along Figure 1A.Such as
Shown in figure, the heterojunction bipolar transistor layout structure includes one or more heterojunction bipolar transistors 110, a passive layer
130th, one first dielectric layer 151, a collector redistribution layer 142, an emitter-base bandgap grading copper post 161 and a collector copper post 162, wherein aforementioned
One or more heterojunction bipolar transistors 110 are to be located at the top of a substrate 100, each of which heterojunction bipolar transistor
Comprising collector layer 111, a collector layer 112, a base layer 113 and an emitter layer 114, wherein base layer 113 is provided with
One base electrode 121, emitter layer 114 is provided with an emitter-base bandgap grading electrode 122, and secondary collector layer 111 is provided with a collector electrode 123；
Passive layer 130 is formed at the top of heterojunction bipolar transistor 110, including an emitter-base bandgap grading weld pad 132a and a collector weld pad
132b, wherein emitter-base bandgap grading weld pad 132a are electrically coupled to each emitter-base bandgap grading electrode 122, and collector weld pad 132b systems are electrically connected at
Each collector electrode 123；First dielectric layer 151 is covered on passive layer 130, and is formed in emitter-base bandgap grading weld pad 132a tops
The emitter-base bandgap grading guide hole 171 of one the first dielectric layer of insertion 151, and form first dielectric layer of insertion 151 in collector weld pad 132b tops
Collector guide hole 172；Collector redistribution layer 142 is to be located on the first dielectric layer 151 and extend into collector guide hole 172 and electric
Property is connected to collector weld pad 132b；Emitter-base bandgap grading copper post 161 is to be located at the top of emitter-base bandgap grading guide hole 171 and fill up emitter-base bandgap grading guide hole 171 and electric
Property is connected to emitter-base bandgap grading weld pad 132a；Collector copper post 162 is a top of collector guide hole 172 and fills up collector guide hole 172 and electrical
It is connected to collector redistribution layer 142；Can form in emitter-base bandgap grading copper post 161 and collector copper post 162 and respectively a soldered ball 163 and 164.On
State heterojunction bipolar transistor layout structure more can form an emitter-base bandgap grading redistribution layer 141 on the first dielectric layer 151, such as scheme
Shown in 1D and 1F, emitter-base bandgap grading redistribution layer 141 is simultaneously extended between emitter-base bandgap grading copper post 161 and emitter-base bandgap grading guide hole 171 and is electrically connected at
Aforementioned emitter-base bandgap grading weld pad 132a.
In the above-described embodiments, the emitter-base bandgap grading electrode of heterojunction bipolar transistor can be parallel finger electrodes；Emitter-base bandgap grading weld pad
132a and collector weld pad 132b is strip, and its major axis is arranged in parallel；Emitter-base bandgap grading guide hole 171, collector guide hole 172 with it is disposed thereon
The emitter-base bandgap grading copper post 161 of side is also strip with collector copper post 162, and collector copper post 162 is, its major axis adjacent with emitter-base bandgap grading copper post 161
For arranged in parallel；Spacing d of emitter-base bandgap grading copper post and collector copper post edge1Limited by Flip Chip, usually between 10 to 75 μm
Between；Space between collector weld pad and emitter-base bandgap grading weld pad may be used to arrange the passive device needed for circuit to save die space,
As shown in Figure 1A -1E, one or more electric capacity are set in the passive layer 130 in region between collector weld pad 132b and emitter-base bandgap grading weld pad 132a
181 and resistance 182, and make it be coupled to heterojunction bipolar transistor 110.
In previous embodiment, also can replace long strip type collector copper posts using one or more circular collector copper posts, and use one
Or multiple shorter collector guide holes replace a long strip type collector guide hole, each circular collector copper post 162 to be disposed on a collector
The top of guide hole 172, and make collector copper post 162 fill up collector guide hole 172, as shown in fig. 1f；Additionally, also can be by aforementioned circle collection
Pole copper post 162 is arranged at the region beyond the top of collector guide hole 172, and passes through collector redistribution layer 142 and be electrically connected at collector
Weld pad 132b, as shown in Figure 1 G.In order to reach good heat sinking function, it will usually using the emitter-base bandgap grading copper with larger sectional area
Post, and its generation height of the emitter-base bandgap grading copper post with larger sectional area can be higher than finally often the less collector copper of sectional area in processing procedure
Post, makes to cause loose contact because of the height fall of copper post after component encapsulation；In embodiment provided by the present invention, emitter-base bandgap grading copper
Post can compensate emitter-base bandgap grading and collector height of the copper pillar drop (such as Fig. 1 G), emitter-base bandgap grading copper post and collector copper post all positions by filling up emitter-base bandgap grading guide hole
When guide hole top, can also pass through the size (such as Fig. 1 D and 1F) of control guide hole or whether emitter-base bandgap grading redistribution layer (such as Figure 1A) is set
Etc. method compensation emitter-base bandgap grading and collector height of the copper pillar drop.
Extend the collector redistribution layer in above-mentioned heterojunction bipolar transistor layout structure, and by collector copper post from aforementioned
Adjacent position parallel with emitter-base bandgap grading copper post moves to elsewhere, can so make full use of die space, reaches the mesh for reducing wafer size
's；Fig. 2A to 2D be another kind of embodiment provided by the present invention, wherein collector redistribution layer 142 in the first dielectric layer 151 it
One collector redistribution layer elongated area 142a of upper formation, by collector copper post 162 collector redistribution layer elongated area 142a is arranged at
The collector guide hole of the position beyond the upper, top of collector guide hole 172, collector weld pad and its top therefore can be more with collector redistribution layer
It is close to emitter-base bandgap grading copper post 161, to reduce wafer size；The edge of emitter-base bandgap grading copper post 161 is with the edge of collector redistribution layer 142 most
Small distance is set to d2, d2Size and no maximum d when so implementing2With less as better, d in the present embodiment2Usually arrive between 1
Between 30 μm, preferably between 1 to 20 μm, more preferably between 1 to 10 μm, most preferably between 1 to 5 μm；This
The outer area that can also reduce collector weld pad, further to reduce wafer size, while saving manufacture material.
In above-described embodiment, collector weld pad and emitter-base bandgap grading bonding pads separation after shortening, the such as electric capacity of the passive device needed for circuit
And resistance then region moves to the outer rim of heterojunction bipolar transistor between collector weld pad and emitter-base bandgap grading weld pad, such as Fig. 2A and 2B institutes
Show, 130 are arranged in the passive layer between emitter-base bandgap grading weld pad 132a and collector weld pad 132b outside region, at neighbouring emitter-base bandgap grading weld pad 132a
One or more electric capacity 181 and resistance 182, and make it be coupled to heterojunction bipolar transistor 110；By emitter-base bandgap grading weld pad 132a and its
The heterojunction bipolar transistor epitaxial layer of lower section is moved toward collector weld pad 132b directions, makes the lower section of emitter-base bandgap grading copper post 161 and substrate
Between form a space, this space be available for arrange circuit needed for passive device, further to reduce wafer size, such as Fig. 2 C
And shown in 2D, in the lower section of emitter-base bandgap grading copper post 161, between emitter-base bandgap grading weld pad 132a and collector weld pad 132b outside region, neighbouring emitter-base bandgap grading weld pad
130 arrange one or more electric capacity 181 and resistance 182 in passive layer at 132a, and make it be coupled to heterojunction bipolar crystal
Pipe 110.
Fig. 3 A and 3B be another kind of embodiment provided by the present invention, wherein collector weld pad 132b shapes in passive layer 130
Into a collector weld pad elongated area 132c, collector guide hole 172 is disposed on this collector weld pad extension area with collector redistribution layer 142
On the 132c of domain, collector copper post 162 is then arranged on collector guide hole 172 and fills up the collector guide hole, and collector weld pad therefore can
It is more close to emitter-base bandgap grading weld pad 132a, to reduce wafer size；The edge of emitter-base bandgap grading weld pad 132a and the edge of collector weld pad 132b
Minimum range is set to d3, d3Size and no maximum d when so implementing3With less as better, d in the present embodiment3Usually between 1
To between 20 μm, preferably between 1 to 15 μm, more preferably between 1 to 10 μm, most preferably between 1 to 5 μm.
In above-described embodiment, with emitter-base bandgap grading bonding pads separation after shortening, the passive device needed for circuit must be arranged collector weld pad
In the outer rim of heterojunction bipolar transistor, as shown in Figure 3A, between emitter-base bandgap grading weld pad 132a and collector weld pad 132b outside region,
130 arrange one or more electric capacity 181 and resistance 182 in passive layer at neighbouring emitter-base bandgap grading weld pad 132a, and it is heterogeneous to be coupled to it
Junction bipolar transistor 110；By emitter-base bandgap grading weld pad 132a with heterojunction bipolar transistor epitaxial layer below toward collector weld pad
132b directions are moved, and make to form a space between the lower section of emitter-base bandgap grading copper post 161 and substrate, and this space is available for arranging the quilt needed for circuit
Dynamic element, further to reduce wafer size, as shown in Figure 3 B, in the lower section of emitter-base bandgap grading copper post 161, emitter-base bandgap grading weld pad 132a and collector
130 arrange one or more electric capacity 181 and resistance in passive layer between weld pad 132b outside region, at neighbouring emitter-base bandgap grading weld pad 132a
182, and make it be coupled to heterojunction bipolar transistor 110.
Passive layer provided by the present invention 130 can include more metal layers, and wherein at least has and connect with heterogeneous positioned at orlop
One the first metal layer 131 of the base stage, collector and emitter-base bandgap grading electrode contact of face bipolar transistor 110, and positioned at the superiors and weight
One second metal layer 132 of distribution layer contact, the first metal layer 131 can be formed on transistor electrodes weld pad (such as 131a and
131b) or wire, because with heterojunction bipolar transistor directly contact, its generally by being formed containing golden metal and not comprising copper, with
Copper atom is avoided to pollute electronic component；The second metal layer of the superiors is to form emitter-base bandgap grading weld pad 132a and collector weld pad
132b, due to will not directly contact electronic component, it can contain metal or copper-containing metal is formed；The first metal layer 131 and
One layer or more metal level can be further included between two metal levels 132 to be used for interconnection；On heterojunction bipolar transistor and per two-layer
Region between metal level in addition in electrical contact is used with a coating (such as 133-135) covering for insulation and protection, is covered
Cap rock is that the material to have insulating properties is formed, wherein being preferable with silicon nitride (SiN)；Metal level in passive layer 130 removes conduct
Electrically connect and be used, also can be used to make the passive devices such as electric capacity, as shown in Figure 1B, 1E, 2B and 2D, the first metal layer 131, second
Metal level 132 may be used to form a metal-insulator-metal (metal-insulator- with in-between coating 134
Metal, MIM) electric capacity, more one layer or more metal level and coating can be inserted in first and second metal level, to form one
Stack type metal-insulator-metal (stacked MIM) electric capacity.
Heterojunction bipolar transistor in previous embodiment is a compound semiconductor electrical element, substrate below
100 is with compound semiconductor materials GaAs (GaAs), gallium nitride (GaN), carborundum (SiC) or sapphire (sapphire)
Formed, wherein being preferable with GaAs；Emitter-base bandgap grading redistribution layer 141 can be by containing the electric conductivity such as gold or copper with collector redistribution layer 142
Good metal is formed, wherein being formed as preferable with copper-containing metal；And electricity is formed on the first dielectric layer using redistribution layer
Sense, to fill space surface of the part using chip；The need of surface planarisation in reach heterojunction bipolar transistor encapsulation procedure
Ask, the first dielectric layer 151 with excellent pore filling ability and the spun-on dielectric of excellent planarization characteristics being formed as
Preferably, dielectric material is coated on the coating of the superiors via spin coating (spin coating) technology, then solid with mode of heating
Change, the first dielectric layer 151 can with dielectric material polyimides (polyimide), benzocyclobutene (benzocyclobutene,
BCB) or polyphenyl oxazole (polybenzoxazole, PBO) is formed, wherein polyphenyl oxazole (PBO) has low-k and high draws
Intensity is stretched, and this material has higher cured thickness, can effectively fill up the height of heterojunction bipolar layer and collector
Degree drop, enables the conduction copper column being formed thereon to have consistent height, is that preferable dielectric material is selected；Additionally, institute of the present invention
The heterojunction bipolar transistor layout structure of offer can further include one second dielectric layer 152, and it is to be covered in the first dielectric layer
151st, it is electrically connected with emitter-base bandgap grading copper post 161 and collector copper post 162 on emitter-base bandgap grading redistribution layer 141 and collector redistribution layer 142
Region in addition；Second dielectric layer 152 can be with dielectric material polyimides (polyimide), benzocyclobutene
(benzocyclobutene, BCB) or polyphenyl oxazole (polybenzoxazole, PBO) are formed, wherein with polyphenyl oxazole (PBO)
For preferable.
Design provided by the present invention, the chip made by any embodiment according to Figure 1A -1G, compared to previous
Technology its size can about reduce 16%；Chip according to made by Fig. 2A illustrated embodiments, compared to prior art, its size about may be used
Reduce 34%；And the chip according to made by Fig. 2 C illustrated embodiments, compared to prior art, its size reduction rate more may be up to about
40%, therefore, design provided by the present invention can effectively reduce component size really.
The present invention has advantages below：
1. in heterojunction bipolar transistor layout structure provided by the present invention, emitter-base bandgap grading copper post can be directly arranged at different
On the emitter-base bandgap grading of matter junction bipolar transistor, therefore the radiating efficiency of heterojunction bipolar transistor can be promoted.
2. in heterojunction bipolar transistor layout structure provided by the present invention, when emitter-base bandgap grading weld pad and collector bonding pads separation
From it is larger when, can by the passive devices such as electric capacity and resistance be arranged at emitter-base bandgap grading weld pad arranged in parallel and collector weld pad between region,
Energy effectively utilizes die space, reduces wafer size.
3. in heterojunction bipolar transistor layout structure provided by the present invention, by redistribution layer, copper post can be set
It is placed on optional position, therefore is avoided that restriction of the Flip Chip to adjacent copper post minimum spacing, reaches and reduce wafer size
Purpose, and the size of collector weld pad can be reduced, more further reduce wafer size and save manufacture material；Additionally, the present invention can
Shorten the distance between emitter-base bandgap grading weld pad and collector weld pad, make emitter-base bandgap grading copper post be changed into part and cover emitter-base bandgap grading weld pad, the quilt such as electric capacity and resistance
Dynamic element then may be disposed at the space below emitter-base bandgap grading copper post, further reduce wafer size.
4. in heterojunction bipolar transistor layout structure provided by the present invention, using spin-coating Jie of low-k
Electric material, can effectively fill up the height fall of heterojunction bipolar layer and collector, make the conductive copper being formed thereon
Post can have consistent height；And there is the emitter-base bandgap grading copper post of larger sectional area, emitter-base bandgap grading and collector can be compensated by filling up emitter-base bandgap grading guide hole
Height of the copper pillar drop, thus improves encapsulation yield.
In sum, there is redistribution layer to tie with the heterojunction bipolar transistor layout of copper post while the present invention is provided
Structure can reach expected purpose really, while radiating using emitter-base bandgap grading copper post, can reduce wafer size, and can improve copper post
Highly it is distributed, and then improves encapsulation yield.The value that its true tool industry is utilized, whence proposes patent application in accordance with the law.
Again described above and diagram are only to illustrate embodiments of the invention, and all ripe personages in this industry skill still may be used
Equivalent localized variation and modification are done, its technology and spirit without departing from the present invention.
Claims (10)
1. a kind of heterojunction bipolar transistor layout structure, it is characterised in that include：
One or more heterojunction bipolar transistors, it is formed at a surface, each of which heterojunction bipolar crystal
Pipe includes a base electrode, an emitter-base bandgap grading electrode and a collector electrode；
One passive layer, it is formed at the heterojunction bipolar transistor top, including a first metal layer, an emitter-base bandgap grading weld pad and
Collector weld pad, the wherein the first metal layer are formed and not comprising copper by the metal containing gold, and the first metal layer is located at the passive layer
Orlop and with the base electrode, the collector electrode and the emitter-base bandgap grading electrode contact, the emitter-base bandgap grading weld pad is by the first metal layer
Each emitter-base bandgap grading electrode is electrically connected at, and the collector weld pad is to be electrically connected at each collector electricity by the first metal layer
Pole；
One first dielectric layer, it is covered on the passive layer, and in emitter-base bandgap grading weld pad top formed one or more insertions this
The emitter-base bandgap grading guide hole of one dielectric layer, and the collector of one or more insertions of formation first dielectric layer is led above the collector weld pad
Hole；
One collector redistribution layer, it is located on first dielectric layer and extends into the collector guide hole and be electrically connected at the collection
Pole weld pad；
One or more emitter-base bandgap grading copper posts, each of which is to be located at least one emitter-base bandgap grading guide hole top and fill up the emitter-base bandgap grading guide hole and electric
Property is connected to the emitter-base bandgap grading weld pad；
One or more collector copper posts, on the collector redistribution layer and are electrically connected at the collector redistribution layer；And
One emitter-base bandgap grading redistribution layer, on first dielectric layer and extends between emitter-base bandgap grading copper post and emitter-base bandgap grading guide hole and electrically connects
It is connected to the emitter-base bandgap grading weld pad.
2. heterojunction bipolar transistor layout structure according to claim 1, it is characterised in that the collector redistribution layer
A collector redistribution layer elongated area is formed on first dielectric layer, the collector copper post is formed at the collector redistribution layer
Position on elongated area, beyond the collector guide hole top；The emitter-base bandgap grading copper post compensates the emitter-base bandgap grading copper by filling up the emitter-base bandgap grading guide hole
The difference in height of post and collector copper post.
3. heterojunction bipolar transistor layout structure according to claim 2, it is characterised in that further include one or more
Electric capacity and resistance, are coupled to the heterojunction bipolar transistor；One or more electric capacity and resistance are disposed on the emitter-base bandgap grading weld pad
In the passive layer between the collector weld pad outside region, at the neighbouring emitter-base bandgap grading weld pad.
4. heterojunction bipolar transistor layout structure according to claim 2, it is characterised in that further include one or more
Electric capacity and resistance, are coupled to the heterojunction bipolar transistor；One or more electric capacity and resistance are disposed on the emitter-base bandgap grading copper post
In lower section, the passive layer between the emitter-base bandgap grading weld pad and the collector weld pad outside region, at the neighbouring emitter-base bandgap grading weld pad.
5. heterojunction bipolar transistor layout structure according to claim 1, it is characterised in that the collector weld pad is in this
A collector weld pad elongated area is formed in passive layer, at least one is formed at the collector weld pad in one or more collector guide holes
On elongated area, each in the collector copper post is that the collector being located above at least one collector weld pad elongated area is led
On hole and fill up the collector guide hole；The emitter-base bandgap grading copper post compensates the emitter-base bandgap grading copper post with collector copper post by filling up the emitter-base bandgap grading guide hole
Difference in height.
6. heterojunction bipolar transistor layout structure according to claim 5, it is characterised in that further include one or more
Electric capacity and resistance, are coupled to the heterojunction bipolar transistor；One or more electric capacity and resistance are disposed on the emitter-base bandgap grading weld pad
With between the collector weld pad outside region, in the passive layer of the neighbouring emitter-base bandgap grading weld pad.
7. heterojunction bipolar transistor layout structure according to claim 5, it is characterised in that further include one or more
Electric capacity and resistance, are coupled to the heterojunction bipolar transistor；One or more electric capacity and resistance are disposed on the emitter-base bandgap grading copper post
In lower section, the passive layer between the emitter-base bandgap grading weld pad and the collector weld pad outside region, at the neighbouring emitter-base bandgap grading weld pad.
8. heterojunction bipolar transistor layout structure according to claim 1, it is characterised in that the collector copper post be with
The emitter-base bandgap grading copper post is adjacent；Each in the collector copper post is to be located at least one collector guide hole and fill up the collector to lead
Hole；The heterojunction bipolar transistor layout structure further includes one or more electric capacity and resistance, is coupled to the heterojunction bipolar
Transistor, and one or more electric capacity and resistance are disposed on the passive layer in region between the collector weld pad and the emitter-base bandgap grading weld pad
In.
9. heterojunction bipolar transistor layout structure according to claim 1, it is characterised in that the collector copper post be with
The emitter-base bandgap grading copper post is adjacent；Each in the collector copper post is on the collector weld pad, outside collector guide hole top
Region；The emitter-base bandgap grading copper post compensates the difference in height of emitter-base bandgap grading copper post and collector copper post by filling up the emitter-base bandgap grading guide hole；The heterojunction is double
Gated transistors layout structure further includes one or more electric capacity and resistance, is coupled to the heterojunction bipolar transistor, and this one or
Multiple electric capacity and resistance are disposed between the collector copper post and the emitter-base bandgap grading copper post in the passive layer in region.
10. heterojunction bipolar transistor layout structure according to claim 1, it is characterised in that the substrate is to change
Compound semi-conducting material GaAs, gallium nitride, carborundum or sapphire are formed.
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