CN104124201A - Forming method of electric conduction structure - Google Patents
Forming method of electric conduction structure Download PDFInfo
- Publication number
- CN104124201A CN104124201A CN201310156920.8A CN201310156920A CN104124201A CN 104124201 A CN104124201 A CN 104124201A CN 201310156920 A CN201310156920 A CN 201310156920A CN 104124201 A CN104124201 A CN 104124201A
- Authority
- CN
- China
- Prior art keywords
- layer
- opening
- formation method
- conductive
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A forming method of an electric conduction structure comprises providing a substrate, wherein the surface of the substrate is provided with a dielectric layer and the dielectric layer is provided with an opening; forming seed layers on surfaces of the lateral wall and the bottom of the opening; implanting modified ions into partial seed layer on the lateral wall surface which is close to the top of the opening through the iron implantation technology; utilizing the thermal annealing technology after the iron implantation technology to enable the partial seed layer with the modified irons being implanted to form into a sacrificial layer, wherein materials of the sacrificial layer and the seed layer are different; removing the sacrificial layer; forming an electric conducting layer in the opening after the sacrificial layer is removed, wherein the opening is full of the electric conducting layer. The formed electric conducting layer is free of gaps internally and good in quality.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of conductive structure.
Background technology
In ic manufacturing process, often adopt conductive plunger to be used for electricity between device interconnected.Along with the fast development of ic manufacturing technology, impel the size of semiconductor device constantly to dwindle, make the technique that forms conductive plunger also be subject to challenge.
The cross-sectional view of the process of prior art formation conductive plunger as shown in Figures 1 to 4.
Please refer to Fig. 1, substrate 100 surfaces have dielectric layer 101, have the opening 102 that is used to form conductive plunger in described dielectric layer 101.
Please refer to Fig. 2, in sidewall and lower surface deposited barrier layer 105 and the Seed Layer 103 of described substrate 100 surfaces, opening 102.
Please refer to Fig. 3, adopt electroplating technology to form conductive film 104 on described Seed Layer 103 surfaces, the surface of described conductive film 104 is higher than dielectric layer 101 surfaces.
Please refer to Fig. 4, adopt CMP (Chemical Mechanical Polishing) process to remove the conductive film 104 higher than dielectric layer 101 surfaces, in described opening, form conductive plunger 104a.
But along with the characteristic size of device is constantly dwindled, the width dimensions of described conductive plunger is corresponding dwindling also, in the conductive plunger forming, easily produce space (Void), the conductive plunger forming is of poor quality, easily affects device performance.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of conductive structure, makes tight in formed conductive structure, quality good.
For addressing the above problem, the invention provides a kind of formation method of conductive structure, comprising: substrate is provided, and described substrate surface has dielectric layer, in described dielectric layer, has opening; Sidewall and lower surface at described opening form Seed Layer; Adopt ion implantation technology to inject modification ion to the Some Species sublayer of the sidewall surfaces near open top; After described ion implantation technology, carry out thermal anneal process, make the Some Species sublayer of injecting modification ion form sacrifice layer, the material of described sacrifice layer is different from the material of Seed Layer; Remove described sacrifice layer; After removing described sacrifice layer, in described opening, form the conductive layer of filling full described opening.
Optionally, the material of described Seed Layer is copper, and the material of described conductive layer is copper.
Optionally, the formation technique of described conductive layer is: adopt electroplating technology or chemical plating process to form the conductive film of filling full gate mouth on described Seed Layer surface; Adopt CMP (Chemical Mechanical Polishing) process to remove the conductive film higher than dielectric layer surface, and expose dielectric layer surface.
Optionally, described modification ion is oxonium ion, and described sacrifice layer is cupric oxide.
Optionally, the technique of described removal sacrifice layer is wet-etching technology, and etching liquid is acetic acid.
Optionally, described ion implantation technology is: implant angle is 0 degree～30 degree, injects metering for 1*10
5～1*10
7atom/square centimeter, Implantation Energy is 50KeV～150KeV.
Optionally, in described ion implantation technology process, horizontally rotate described substrate, described in the angle that horizontally rotates be 0 degree or 180 degree.
Optionally, the formation method of described opening is: form mask layer on dielectric layer surface, described mask layer exposes part dielectric layer surface; Taking described mask layer as mask, adopt described in anisotropic dry etch process etching dielectric layer to form opening.
Optionally, described mask layer comprises silicon oxide layer and is positioned at the metal nitride layer on silicon oxide layer surface, and the material of described metal nitride layer comprises titanium nitride or tantalum nitride.
Optionally, described Seed Layer is also formed at top and the sidewall surfaces of described mask layer, and described modification ion also injects the Seed Layer that is positioned at mask layer top and sidewall surfaces.
Optionally, also comprise: form stop-layer at substrate surface, dielectric layer is formed at described stop-layer surface, the material of described stop-layer is different from dielectric layer, the technique of described etching dielectric layer stops at described stop-layer surface, and after the technique of described etching dielectric layer, remove the stop-layer of open bottom.
Optionally, the formation technique of described Seed Layer is atom layer deposition process or physical gas-phase deposition.
Optionally, described thermal anneal process is: temperature is 150 degrees Celsius～300 degrees Celsius, and the time is 10 minutes～10 minutes.
Optionally, also comprise: before forming described Seed Layer, form barrier layer in sidewall and the lower surface of dielectric layer surface and opening, the material on described barrier layer is titanium nitride or tantalum nitride; Form Seed Layer at described barrier layer surface.
Optionally, described substrate comprises: Semiconductor substrate; Be formed at the device of described semiconductor substrate surface; Be formed at the insulating barrier of semiconductor substrate surface the described device of electricity isolation.
Optionally, described substrate is Semiconductor substrate.
Optionally, the material of described dielectric layer is low-K material or super low-K material.
Optionally, the depth-to-width ratio of described opening is greater than 5:1.
Optionally, also comprise: adopt CMP (Chemical Mechanical Polishing) process to remove the conductive layer higher than dielectric layer surface, until expose dielectric layer surface, in opening, form conductive plunger.
Compared with prior art, technical scheme of the present invention has the following advantages:
After the sidewall and lower surface formation Seed Layer of opening, adopt ion implantation technology to inject modification ion to the Some Species sublayer of the sidewall surfaces near open top, after follow-up thermal annealing, inject the Some Species sublayer formation sacrifice layer of modification ion; Because cambial material is different from the Seed Layer that is not injected into modification ion, therefore described sacrifice layer and Seed Layer have higher selection in etching technics, can either remove described sacrifice layer by etching technics, and retain the Seed Layer that is not injected into modification ion; In the Seed Layer of described modification Implantation near open top, be that sacrifice layer is positioned at the sidewall surfaces near open top, remove after sacrifice layer, can make the width dimensions of open top become large, thereby can suppress in the process of follow-up formation conductive layer, open top too early closed and in conductive layer interstitial problem.Fine and close in the conductive layer forming, can ensure its electric conductivity, make formed performance of semiconductor device more stable.
Further, the material of described Seed Layer is copper, and described modification ion is oxonium ion, and the material of the sacrifice layer that formed is cupric oxide; Because cupric oxide is basic anhydride, easily react neutralization with acidulous material, and metallic copper can not react with acidulous material, therefore adopt acetic acid can remove as etching liquid the sacrifice layer that described cupric oxide is material, can not cause damage to the remaining Seed Layer taking copper as material simultaneously; In increasing open top width dimensions, ensure that the pattern on residue Seed Layer surface is good, be conducive to the measured conductive layer of follow-up formation matter.
Further, the modification Ion Phase injecting is for dielectric layer surface tilt, angle of inclination is in the scope of 0 degree to 30 degree, by controlling the angle of described ion implantation technology, can control the bottom in Implantation region to the distance on dielectric layer surface, controlled the sacrifice layer bottom of follow-up formation to the distance on dielectric layer surface, the size of sacrifice layer is controlled; Secondly, can control by controlling Implantation Energy the degree of depth of injecting ion, thus the thickness of follow-up the formed sacrifice layer of control; Therefore, the size of the sacrifice layer of required removal and thickness are all controlled, are conducive to form the measured conductive layer of matter.
Brief description of the drawings
Fig. 1 to Fig. 4 is the cross-sectional view that prior art forms the process of conductive plunger;
Fig. 5 to Figure 12 is the cross-sectional view of the forming process of the conductive structure described in the embodiment of the present invention.
Embodiment
As stated in the Background Art, in the conductive plunger that prior art forms, easily produce space, its of poor quality, unstable properties.
Study discovery through the present inventor, please continue to refer to Fig. 1 to Fig. 4, along with device feature size constantly dwindles, the width at described opening 102 tops also constantly dwindles, cause the depth-to-width ratio (Aspect Ratio) of described opening 102 to improve, the opening depth-to-width ratio that is used to form at present conductive plunger is greater than 5:1.Described Seed Layer 103 adopts atom layer deposition process or physical gas-phase deposition to be formed at sidewall and the lower surface of opening 102, but, along with the depth-to-width ratio of opening 102 increases, the top width size of opening 102 is dwindled, the material sidewall surfaces that are deposited near opening 102 tops of Seed Layer more; After causing formation Seed Layer, opening 102 top width sizes are less than bottom width size; In the process of follow-up formation conductive film 104, easily cause not also being filled in opening 102 when full, the top of described opening 102 is closed, thereby in opening, forms space, and then produces space in the conductive plunger 104a of formation glossing after.Described space easily affects the electric conductivity of conductive plunger 104a, makes formed device performance not good.
Further study through the present inventor, after the sidewall and lower surface formation Seed Layer of opening, adopt ion implantation technology to inject modification ion to the Some Species sublayer of the sidewall surfaces near open top, after follow-up thermal annealing, the Some Species sublayer of injecting modification ion forms sacrifice layer; Because the material of sacrifice layer is different from the Seed Layer that is not injected into modification ion, therefore described sacrifice layer and Seed Layer have higher selection in etching technics, can either remove described sacrifice layer by etching technics, and retain the Seed Layer that is not injected into modification ion; In the Seed Layer of described modification Implantation near open top, be that sacrifice layer is positioned at the sidewall surfaces near open top, remove after sacrifice layer, can make the width dimensions of open top become large, thereby can suppress in the process of follow-up formation conductive layer, open top too early closed and in conductive layer interstitial problem.Fine and close in the conductive plunger forming, can ensure its electric conductivity, make formed performance of semiconductor device more stable.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 5 to Figure 12 is the cross-sectional view of the forming process of the conductive structure described in the embodiment of the present invention.
Please refer to Fig. 5, substrate 200 is provided, described substrate 200 surfaces have dielectric layer 201, form mask layer 202 on dielectric layer 201 surfaces, and described mask layer 202 exposes part dielectric layer 201 surfaces.
Described substrate 200 provides workbench for subsequent technique; In the present embodiment, described substrate 200 comprises; Semiconductor substrate (not shown), be formed at the device (not shown) of described semiconductor substrate surface and be formed at semiconductor substrate surface and the insulating barrier (not shown) of the described device of electricity isolation; Described Semiconductor substrate comprises silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V compounds of group substrate (such as gallium nitride or GaAs etc.); Described device comprises transistor, memory, capacitor, inductor, fuse or metal interconnection wire etc.; The material of described insulating barrier is silica, silicon nitride or silicon oxynitride.Follow-up formed conductive plunger connects at the point of integrated circuit for realizing described device.In another embodiment, described substrate is Semiconductor substrate, and follow-up formed conductive plunger is positioned at semiconductor substrate surface.
The material of described dielectric layer 201 is low-K material or super low-K material, effectively follow-up the formed conductive plunger of electricity isolation; The formation technique of described dielectric layer 201 is depositing operation, preferably chemical vapor deposition method; The interior follow-up conductive plunger that is used to form of described dielectric layer 201.
Described mask layer 202 comprises silicon oxide layer (not shown) and is positioned at the metal nitride layer (not shown) on silicon oxide layer surface, and the material of described metal nitride layer comprises titanium nitride or tantalum nitride; Described mask layer 202 is for defining the follow-up position that need to form opening; The formation technique of described mask layer is: at dielectric layer surface deposition mask film, in the present embodiment, described mask film comprises silicon oxide film and is positioned at the metal nitride film on silicon oxide film surface; Adopt photoetching process to form photoresist layer at described mask film surface, described photoresist layer has defined the position that need to form opening; Taking photoresist layer as mask, mask film described in etching until expose dielectric layer 201 surfaces, forms mask layer 202, removes afterwards photoresist layer.
In one embodiment, form stop-layer (not shown) on substrate 200 surfaces, described dielectric layer 201 is formed at described stop-layer surface, and the material of described stop-layer is different from dielectric layer 201, the formation technique of described stop-layer is depositing operation, for example chemical vapor deposition method; In the process of subsequent etching opening, stop-layer has Etch selectivity with respect to dielectric layer 201, and the technique that subsequent etching dielectric layer forms opening stops at described stop-layer surface, avoids etching technics to cause damage to substrate 200 surfaces.After the technique of described etching dielectric layer, can adopt wet processing to remove the stop-layer of open bottom.
Please refer to Fig. 6, taking described mask layer 202 as mask, adopt dielectric layer 201 described in anisotropic dry etch process etching, and form opening 203.
The formation technique of described opening 203 is anisotropic dry etch process, for example plasma dry etch process, and the design parameter of described etching technics determines according to the size of the material of dielectric layer and thickness and opening 203.
Along with the characteristic size of semiconductor device continues to dwindle, the integrated level of integrated circuit improves constantly, cause the width dimensions of conductive plunger also constantly to dwindle, and described conductive plunger need to meet the interconnected demand of electricity in integrated circuit, its length can correspondingly not dwindled, thereby causes the depth-to-width ratio of the opening 203 that is used to form conductive plunger to increase.In the present embodiment, the top width of described opening 203 is of a size of 30nm～50nm, and the depth-to-width ratio of described opening 203 is greater than 5:1.
The follow-up depositing operation that need to adopt forms barrier layer and Seed Layer in sidewall and the lower surface of described opening 203, then forms the conductive film of filling full gate mouth with electroplating technology on Seed Layer surface, to form conductive plunger.But, along with the depth-to-width ratio of described opening 203 increases, the width dimensions at described opening 203 tops dwindles, follow-up in the process of the interior formation conductive film of opening 203, easily in the time that opening 203 is not also filled completely, be closed, cause generation space in formed conductive layer.
Please refer to Fig. 7, form barrier layer 210 in sidewall and the lower surface of described opening 203, form Seed Layer 204 at described barrier layer surface.
The material on described barrier layer 210 is titanium nitride or tantalum nitride, and the thickness on described barrier layer 210 is 50 dust～150 dusts, and forming technique is atom layer deposition process or physical gas-phase deposition; Described barrier layer 210, for stoping the material of conductive layer of follow-up formation to dielectric layer 201 or the interior diffusion of substrate 200, has ensured the electric performance stablity of the conductive plunger forming.
The material of described Seed Layer 204 is copper, and thickness is 50 dust～150 dusts, and the formation technique of described Seed Layer 204 is atom layer deposition process or physical gas-phase deposition; Described Seed Layer 204 is conducted electricity in follow-up electroplating technology, and at described Seed Layer 204 superficial growth electric conducting materials to form the conductive film of filling opening 203.
In the present embodiment, owing to not removing mask layer 202 before forming barrier layer 210, described Seed Layer 204 is also formed at top and the sidewall surfaces of described mask layer 202 by depositing operation, the conductive film of described mask layer 202 follow-up formation is also positioned at described mask layer 202 surfaces; Stop position when described mask layer 202 can define subsequent chemical-mechanical polishing conductive film.
Because the depth-to-width ratio of described opening 203 is larger, be greater than 5:1, and described opening 203 top width sizes are less, for 30nm～50nm, be formed at Seed Layer 204 and barrier layer 210 thinner thicknesses of opening 203 bottoms, meanwhile, thicker near the Seed Layer 203 of opening 203 top sidewalls; In the time that following adopted electroplating technology forms conductive film on Seed Layer 203 surfaces, the top of described opening 203 is easily first closed, and in described opening 203, be not also filled completely simultaneously, make to there is space in formed conductive plunger, affect the conductive capability of described conductive plunger, the stability of device reduces.
Please refer to Fig. 8, adopt ion implantation technology to inject modification ion to the Some Species sublayer 204 of the sidewall surfaces near opening 203 tops.
Described modification ion is used for the material modification of the Seed Layer 204 of the sidewall surfaces that makes close opening 203 tops, thereby after subsequent thermal annealing process, make the material of the Some Species sublayer 204 of injecting modification ion, different from the material of Seed Layer 204 that does not inject modification ion, therefore described Seed Layer 204 was injected the part of modification ion and was not injected between the part of modification ion and had Etch selectivity, follow-uply can adopt etching technics to remove in Seed Layer 204 to inject the part of modification ion, and retain Seed Layer 204 and do not inject the part of modification ion; And, the part that described Seed Layer 204 was injected modification ion is positioned at the sidewall surfaces near opening 203 tops, can remove Seed Layer 204 and be positioned at the bossing of opening 203 top side wall surfaces, thereby can be suppressed in follow-up electroplating technology, opening 203 tops are the problem of closure too early.
In the present embodiment, described modification ion is oxonium ion, after subsequent thermal annealing process, the sacrificial layer material that the part of injecting modification ion by described Seed Layer 204 forms is cupric oxide, described cupric oxide can react with acidulous material, and acidulous material can not cause damage to the Seed Layer 204 taking copper as material, therefore can, in removing sacrifice layer, retain the residue Seed Layer 204 of not injecting modification ion.
Described ion implantation technology is: implant angle is 0 degree～30 degree, injects metering for 1*105～1*107 atom/square centimeter, and Implantation Energy is 50KeV～150KeV; In described ion implantation technology process, horizontally rotate described substrate 200, described in the angle that horizontally rotates be 0 degree or 180 degree; Wherein, horizontally rotate 0 degree in ion implantation process, do not rotate substrate 200; And horizontal rotary turnback refers to: first described substrate 200 be set for initial position and carry out Implantation, making afterwards described substrate 200 around its central horizontal Rotate 180 degree, and proceed Implantation; Make substrate 200 horizontal rotary turnbacks can make modification ion enter the arbitrary sidewall surfaces near opening 203 tops of described opening 203, make the arbitrary sidewall surfaces near top of follow-up opening 203 form sacrifice layer.In the present embodiment, described Seed Layer 204 is also formed at top and the sidewall surfaces of mask layer 202, and described modification ion also injects the Seed Layer 204 that is positioned at mask layer 202 tops and sidewall surfaces.
It should be noted that, adjust by the parameter to ion implantation technology, for example, strengthen Implantation Energy, can control the degree of depth of injecting modification ion, control the thickness of the sacrifice layer forming, thereby can remove according to concrete process requirements the sacrifice layer of desired thickness size; And, can inject the degree of depth of modification ion that the angle control of ion is injected by adjustment, can control the bottom of sacrifice layer of follow-up required removal to the distance at opening 203 tops.
In other embodiments, the modification ionic species injecting can be adjusted, and has Etch selectivity and only need to meet between follow-up formed sacrifice layer and Seed Layer 204.
Please refer to Fig. 9, after described ion implantation technology, carry out thermal anneal process, make the Some Species sublayer 204 of injecting modification ion form sacrifice layer 205, the material of described sacrifice layer 205 is different from the material of Seed Layer 204.
Described thermal anneal process is: temperature is 150 degrees Celsius～300 degrees Celsius, and the time is 1 minute～10 minutes; Described thermal anneal process makes to inject the material of the ion formation sacrifice layer 205 in modification ion and Seed Layer 204; And described thermal anneal process can make the more smooth densification of described Seed Layer 204, Stability Analysis of Structures, is conducive to form the second best in quality conductive plunger.In the present embodiment, the material of described Seed Layer 204 is copper, and described modification ion is oxonium ion, and the material of the sacrifice layer 205 that formed is cupric oxide.
Because described cupric oxide can react with acidulous material, therefore can adopt faintly acid liquid to carry out etching to described sacrifice layer 205; Meanwhile, the seed taking copper as material can not react with acidulous material, therefore, in the time of etching sacrificial layer 205, can not damage the Seed Layer 204 of not injecting modification ion.Therefore, follow-uply can remove sacrifice layer 205 by etching, make opening 203 become large near the width dimensions at top, thereby while suppressing follow-up formation conductive film, the problem that opening 203 tops are first closed, avoids producing space in formed conductive plunger.
Please refer to Figure 10, remove described sacrifice layer 205(as shown in Figure 9).
The technique of described removal sacrifice layer is wet-etching technology.In the present embodiment, because the material of Seed Layer 204 is copper, the material of sacrifice layer 205 is cupric oxide, described silica can with weakly acidic acetic acid (CH
3cOOH) reaction, and described acetic acid can not damage copper; Concrete, the course of reaction of described acetic acid and cupric oxide is: CuO+2CH
3cOOH → Cu
2++ 2CH
3cOO
-+ H
2o; Therefore, the etching liquid of described etching technics is acetic acid, after removing sacrifice layer 205, can not damage remaining Seed Layer 204.After removing sacrifice layer 205, as shown in Figure 8, Seed Layer 204 is removed near the bossing of the sidewall surfaces at opening 203 tops.
In the present embodiment, remove sacrifice layer 205 and expose barrier layer 210, be removed completely near the Seed Layer of opening 203 top side wall surfaces, in the time of following adopted electroplating technology growth conductive film 206, in the time of Seed Layer 204 superficial growth copper product, the barrier layer surface being exposed out near the opening 203 top sidewalls copper product of can simultaneously not growing, copper product is after filling the full opening 203 being covered by Seed Layer 204, just can be to opening 203 grown on top, therefore avoided opening 203 problem of closure too early, tight in follow-up formed conductive plunger, electric conductivity is good.
Please refer to Figure 11, removing after described sacrifice layer 205, at described opening 203(as shown in figure 10) in Seed Layer 204 surfaces form and fill the completely conductive film 206 of described opening 203.
The material of described conductive film 206 is copper, and the formation technique of described conductive film 206 is copper electroplating technology (ECP, electro-coppering plating) or chemical plating process.In described copper electroplating technology, electric conducting material starts growth from Seed Layer 204 surfaces, until fill the grown on top to opening 203 after full gate mouth 203, until the conductive film 206 forming is higher than the top of opening 203; In the present embodiment, due to the material conduction on barrier layer 210, the barrier layer therefore mask layer 202 surfaces being exposed applies voltage, to implement copper electroplating technology; And, the Time dependent of described copper electroplating technology the thickness of the conductive film 206 that forms, therefore can, by controlling the process time, accurately control described conductive film 206 and fill full gate mouth 203.
In the present embodiment, inject modification ion by the Seed Layer near opening 203 top side wall surfaces, and the part that makes Seed Layer inject modification ion by thermal anneal process forms sacrifice layer, the part that makes sacrifice layer and Seed Layer 204 not inject modification ion has Etch selectivity, can remove sacrifice layer and retain the Seed Layer 204 of not injecting modification ion by etching technics, remove the bossing of Seed Layer 204 near opening 203 top side wall surfaces; Thereby in described copper electroplating technology, described opening 203 is can be too early closed, ensure that described conductive film can fully fill completely described opening, thereby made follow-up formed conductive layer densification and tight, the electric conductivity of the conductive plunger forming is good.
Please refer to Figure 12, adopt CMP (Chemical Mechanical Polishing) process to remove higher than conductive film 206, barrier layer 210 and the mask layer 202(on dielectric layer 201 surfaces as shown in figure 11), at opening 203(as shown in figure 10) in formation conductive plunger 207.
In described CMP (Chemical Mechanical Polishing) process, described because mask layer 202 is different from the material of Seed Layer and conductive film 206, the stop position that can be used in definition glossing, after being polished to described mask layer 202, carried out polishing to expose dielectric layer 201 surfaces.In the present embodiment, through after glossing, the interior remaining conductive film 206 of opening 201 and Seed Layer 204 form conductive plunger.Due to the interior fine and close tight of formed conductive film 206, quality and the electric conductivity of the conductive plunger forming are good, are conducive to device stability and improve.
In the present embodiment, after the sidewall of mask layer surface and opening and lower surface form the Seed Layer taking copper as material, the Seed Layer near open top sidewall is injected to oxonium ion; After thermal anneal process, the part that Seed Layer is injected modification ion forms the sacrifice layer that cupric oxide is material; Because cupric oxide and copper have Etch selectivity, easily and acetic acid reaction, and acetic acid can not damage copper to described cupric oxide; Therefore remove cupric oxide sacrifice layer with acetic acid, and Seed Layer can not sustain damage; Thereby Seed Layer is removed near the bossing of open top sidewall surfaces, in the time that following adopted copper electroplating technology forms conductive film, the top of damage opening can be first not closed, avoided forming space in conductive film.Therefore,, after glossing, by through fine and close tight in the Seed Layer of polishing and conductive plunger that conductive film forms, its electric conductivity is good.
In sum, after the sidewall and lower surface formation Seed Layer of opening, adopt ion implantation technology to inject modification ion to the Some Species sublayer of the sidewall surfaces near open top, after follow-up thermal annealing, the Some Species sublayer of injecting modification ion forms sacrifice layer; Because cambial material is different from the Seed Layer that is not injected into modification ion, therefore described sacrifice layer and Seed Layer have higher selection in etching technics, can either remove described sacrifice layer by etching technics, and retain the Seed Layer that is not injected into modification ion; In the Seed Layer of described modification Implantation near open top, be that sacrifice layer is positioned at the sidewall surfaces near open top, remove after sacrifice layer, can make the width dimensions of open top become large, thereby can suppress in the process of follow-up formation conductive layer, open top too early closed and in conductive layer interstitial problem.Fine and close in the conductive layer forming, can ensure its electric conductivity, make formed performance of semiconductor device more stable.
Further, the material of described Seed Layer is copper, and described modification ion is oxonium ion, and the material of the sacrifice layer that formed is cupric oxide; Because cupric oxide is basic anhydride, easily react neutralization with acidulous material, and metallic copper can not react with acidulous material, therefore adopt acetic acid can remove as etching liquid the sacrifice layer that described cupric oxide is material, can not cause damage to the remaining Seed Layer taking copper as material simultaneously; In increasing open top width dimensions, ensure that the pattern on residue Seed Layer surface is good, be conducive to the measured conductive layer of follow-up formation matter.
Further, the modification Ion Phase injecting is for dielectric layer surface tilt, angle of inclination is 0 degree～30 degree, by controlling the angle of described ion implantation technology, can control the bottom in Implantation region to the distance on dielectric layer surface, controlled the sacrifice layer bottom of follow-up formation to the distance on dielectric layer surface, the size of sacrifice layer is controlled; Secondly, can control by controlling Implantation Energy the degree of depth of injecting ion, thus the thickness of follow-up the formed sacrifice layer of control; Therefore, the size of the sacrifice layer of required removal and thickness are all controlled, are conducive to form the measured conductive layer of matter.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (19)
1. a formation method for conductive structure, is characterized in that, comprising:
Substrate is provided, and described substrate surface has dielectric layer, in described dielectric layer, has opening;
Sidewall and lower surface at described opening form Seed Layer;
Adopt ion implantation technology to inject modification ion to the Some Species sublayer of the sidewall surfaces near open top;
After described ion implantation technology, carry out thermal anneal process, make the Some Species sublayer of injecting modification ion form sacrifice layer, the material of described sacrifice layer is different from the material of Seed Layer;
Remove described sacrifice layer;
After removing described sacrifice layer, in described opening, form the conductive layer of filling full described opening.
2. the formation method of conductive structure as claimed in claim 1, is characterized in that, the material of described Seed Layer is copper, and the material of described conductive layer is copper.
3. the formation method of conductive structure as claimed in claim 2, is characterized in that, the formation technique of described conductive layer is: adopt electroplating technology or chemical plating process to form the conductive film of filling full gate mouth on described Seed Layer surface; Adopt CMP (Chemical Mechanical Polishing) process to remove the conductive film higher than dielectric layer surface, and expose dielectric layer surface.
4. the formation method of conductive structure as claimed in claim 2, is characterized in that, described modification ion is oxonium ion, and described sacrifice layer is cupric oxide.
5. the formation method of conductive structure as claimed in claim 4, is characterized in that, the technique of described removal sacrifice layer is wet-etching technology, and etching liquid is acetic acid.
6. the formation method of conductive structure as claimed in claim 1, is characterized in that, described ion implantation technology is: implant angle is 0 degree～30 degree, injects metering for 1*10
5～1*10
7atom/square centimeter, Implantation Energy is 50KeV～150KeV.
7. the formation method of groove isolation construction as claimed in claim 6, is characterized in that, in described ion implantation technology process, horizontally rotates described substrate, described in the angle that horizontally rotates be 0 degree or 180 degree.
8. the formation method of conductive structure as claimed in claim 1, is characterized in that, the formation method of described opening is: form mask layer on dielectric layer surface, described mask layer exposes part dielectric layer surface; Taking described mask layer as mask, adopt described in anisotropic dry etch process etching dielectric layer to form opening.
9. the formation method of conductive structure as claimed in claim 8, is characterized in that, described mask layer comprises silicon oxide layer and be positioned at the metal nitride layer on silicon oxide layer surface, and the material of described metal nitride layer comprises titanium nitride or tantalum nitride.
10. the formation method of conductive structure as claimed in claim 8, is characterized in that, described Seed Layer is also formed at top and the sidewall surfaces of described mask layer, and described modification ion also injects the Seed Layer that is positioned at mask layer top and sidewall surfaces.
The formation method of 11. conductive structures as claimed in claim 8, it is characterized in that, also comprise: form stop-layer at substrate surface, dielectric layer is formed at described stop-layer surface, the material of described stop-layer is different from dielectric layer, the technique of described etching dielectric layer stops at described stop-layer surface, and after the technique of described etching dielectric layer, removes the stop-layer of open bottom.
The formation method of 12. conductive structures as claimed in claim 1, is characterized in that, the formation technique of described Seed Layer is atom layer deposition process or physical gas-phase deposition.
The formation method of 13. conductive structures as claimed in claim 1, is characterized in that, described thermal anneal process is: temperature is 150 degrees Celsius～300 degrees Celsius, and the time is 1 minute～10 minutes.
The formation method of 14. conductive structures as claimed in claim 1, it is characterized in that, also comprise: before forming described Seed Layer, form barrier layer in sidewall and the lower surface of dielectric layer surface and opening, the material on described barrier layer is titanium nitride or tantalum nitride; Form Seed Layer at described barrier layer surface.
The formation method of 15. conductive structures as claimed in claim 1, is characterized in that, described substrate comprises: Semiconductor substrate; Be formed at the device of described semiconductor substrate surface; Be formed at the insulating barrier of semiconductor substrate surface the described device of electricity isolation.
The formation method of 16. conductive structures as claimed in claim 1, is characterized in that, described substrate is Semiconductor substrate.
The formation method of 17. conductive structures as claimed in claim 1, is characterized in that, the material of described dielectric layer is low-K material or super low-K material.
The formation method of 18. conductive structures as claimed in claim 1, is characterized in that, the depth-to-width ratio of described opening is greater than 5:1.
The formation method of 19. conductive structures as claimed in claim 1, is characterized in that, also comprises: adopt CMP (Chemical Mechanical Polishing) process to remove the conductive layer higher than dielectric layer surface, until expose dielectric layer surface, form conductive plunger in opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310156920.8A CN104124201B (en) | 2013-04-28 | 2013-04-28 | The forming method of conductive structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310156920.8A CN104124201B (en) | 2013-04-28 | 2013-04-28 | The forming method of conductive structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104124201A true CN104124201A (en) | 2014-10-29 |
| CN104124201B CN104124201B (en) | 2017-12-01 |
Family
ID=51769567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310156920.8A Active CN104124201B (en) | 2013-04-28 | 2013-04-28 | The forming method of conductive structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104124201B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107369645A (en) * | 2016-05-13 | 2017-11-21 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN108336060A (en) * | 2017-01-19 | 2018-07-27 | 南亚科技股份有限公司 | Conduction connecting structure |
| CN108735797A (en) * | 2017-04-25 | 2018-11-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| WO2019023945A1 (en) * | 2017-08-01 | 2019-02-07 | 深圳华大基因研究院 | Fluidic channel structure device and manufacturing method therefor |
| CN110021560A (en) * | 2018-01-10 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN111326290A (en) * | 2018-12-14 | 2020-06-23 | 海安科技株式会社 | Method for producing transparent conductive film |
| CN112530856A (en) * | 2019-09-18 | 2021-03-19 | 长鑫存储技术有限公司 | Semiconductor device, semiconductor structure and manufacturing method of interconnection structure |
| CN112736030A (en) * | 2019-10-29 | 2021-04-30 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN113506771A (en) * | 2021-07-23 | 2021-10-15 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor structure and semiconductor structure |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02185025A (en) * | 1989-01-12 | 1990-07-19 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| US6291332B1 (en) * | 1999-10-12 | 2001-09-18 | Advanced Micro Devices, Inc. | Electroless plated semiconductor vias and channels |
| TW593770B (en) * | 1999-05-10 | 2004-06-21 | Air Prod & Chem | Method for anisotropic etching of copper thin films with a beta-diketone, a beta-ketoimine, or a breakdown product thereof |
| US20070178692A1 (en) * | 2001-10-18 | 2007-08-02 | Lsi Logic Corporation | Multi-step process for forming a barrier film for use in copper layer formation |
| US20110256717A1 (en) * | 2010-04-19 | 2011-10-20 | Samsung Electronics Co., Ltd. | Methods for fabricating semiconductor devices |
| US20120100715A1 (en) * | 2006-08-25 | 2012-04-26 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device including through electrode |
| CN102543835A (en) * | 2010-12-15 | 2012-07-04 | 中国科学院微电子研究所 | Opening filling method |
-
2013
- 2013-04-28 CN CN201310156920.8A patent/CN104124201B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02185025A (en) * | 1989-01-12 | 1990-07-19 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| TW593770B (en) * | 1999-05-10 | 2004-06-21 | Air Prod & Chem | Method for anisotropic etching of copper thin films with a beta-diketone, a beta-ketoimine, or a breakdown product thereof |
| US6291332B1 (en) * | 1999-10-12 | 2001-09-18 | Advanced Micro Devices, Inc. | Electroless plated semiconductor vias and channels |
| US20070178692A1 (en) * | 2001-10-18 | 2007-08-02 | Lsi Logic Corporation | Multi-step process for forming a barrier film for use in copper layer formation |
| US20120100715A1 (en) * | 2006-08-25 | 2012-04-26 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device including through electrode |
| US20110256717A1 (en) * | 2010-04-19 | 2011-10-20 | Samsung Electronics Co., Ltd. | Methods for fabricating semiconductor devices |
| CN102543835A (en) * | 2010-12-15 | 2012-07-04 | 中国科学院微电子研究所 | Opening filling method |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107369645A (en) * | 2016-05-13 | 2017-11-21 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN107369645B (en) * | 2016-05-13 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN108336060B (en) * | 2017-01-19 | 2020-03-06 | 南亚科技股份有限公司 | Conductive connection structure |
| CN108336060A (en) * | 2017-01-19 | 2018-07-27 | 南亚科技股份有限公司 | Conduction connecting structure |
| CN108735797A (en) * | 2017-04-25 | 2018-11-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108735797B (en) * | 2017-04-25 | 2022-05-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| WO2019023945A1 (en) * | 2017-08-01 | 2019-02-07 | 深圳华大基因研究院 | Fluidic channel structure device and manufacturing method therefor |
| CN110753580A (en) * | 2017-08-01 | 2020-02-04 | 深圳华大生命科学研究院 | Flow passage structure device and manufacturing method thereof |
| CN110753580B (en) * | 2017-08-01 | 2022-02-08 | 深圳华大生命科学研究院 | Flow passage structure device and manufacturing method thereof |
| CN110021560A (en) * | 2018-01-10 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN111326290A (en) * | 2018-12-14 | 2020-06-23 | 海安科技株式会社 | Method for producing transparent conductive film |
| CN112530856A (en) * | 2019-09-18 | 2021-03-19 | 长鑫存储技术有限公司 | Semiconductor device, semiconductor structure and manufacturing method of interconnection structure |
| CN112736030A (en) * | 2019-10-29 | 2021-04-30 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN113506771A (en) * | 2021-07-23 | 2021-10-15 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN113506771B (en) * | 2021-07-23 | 2022-12-09 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor structure and semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104124201B (en) | 2017-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104124201A (en) | Forming method of electric conduction structure | |
| US10943823B2 (en) | Conductive feature formation and structure using bottom-up filling deposition | |
| US9490345B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN105428304A (en) | Semiconductor Structures And Methods For Forming Isolation Between Fin Structures Of Finfet Devices | |
| CN105448841B (en) | The forming method of semiconductor structure | |
| CN107799422A (en) | The method for forming semiconductor devices | |
| KR20190064375A (en) | Conductive Feature Formation and Structure | |
| US20110309457A1 (en) | Method for Forming a Notched Gate Insulator for Advanced MIS Semiconductor Devices and Devices Thus Obtained | |
| CN107230727A (en) | The method for making semiconductor element | |
| CN105719947B (en) | The forming method of semiconductor devices | |
| US20220238660A1 (en) | Method of Forming Backside Power Rails | |
| CN105576018A (en) | Semiconductor structure and formation method thereof | |
| CN107039535A (en) | Capacitor element and forming method thereof | |
| CN104752228B (en) | Semiconductor device structure and its manufacturing method | |
| CN108321083A (en) | Semiconductor structure and forming method thereof | |
| CN105261566A (en) | Method for forming semiconductor structure | |
| CN105513969B (en) | The forming method of transistor | |
| CN104008974A (en) | Semiconductor device and manufacturing method | |
| CN103187280A (en) | Manufacturing method of fin type field effect transistor | |
| CN109920733A (en) | The forming method of semiconductor structure and transistor | |
| CN109103102A (en) | Semiconductor structure and forming method thereof | |
| CN105789131B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN106571341A (en) | Semiconductor structure and forming method thereof | |
| CN105655288A (en) | Formation method of semiconductor structure | |
| CN102054674A (en) | Metal gate electrode and method for manufacturing metal gate electrode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |