CN104112747B - Memory device, manufacturing method and access method of memory device - Google Patents
Memory device, manufacturing method and access method of memory device Download PDFInfo
- Publication number
- CN104112747B CN104112747B CN201310138397.6A CN201310138397A CN104112747B CN 104112747 B CN104112747 B CN 104112747B CN 201310138397 A CN201310138397 A CN 201310138397A CN 104112747 B CN104112747 B CN 104112747B
- Authority
- CN
- China
- Prior art keywords
- transistor
- memory device
- substrate
- capacitor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
Abstract
The invention discloses a memory device, manufacturing method and access method of the memory device. According to one embodiment of the invention, the memory device may comprises a substrate, a transistor which is formed on the substrate and includes a gate stack as well as a source region and a drain region located at two sides of the gate stack, and a capacitor structure which is formed in the substrate, wherein at least one part of the capacitor structure extends towards a space below a trench region of the transistor; the memory device may further comprise a tunneling channel between the capacitor structure and the drain region of the transistor; and the tunneling channel is configured to allow carriers in the trench region of the transistor to enter the capacitor structure or release carriers stored in the capacitor structure through a tunneling effect, when the transistor turned on and a certain voltage difference exists between the source region of the transistor and the capacitor structure.
Description
Technical field
It relates to semiconductor applications, more particularly, to a kind of memory device and its manufacture method and access method.
Background technology
A kind of common flush memory device implementation of floating gate transistor structures.However, being increasingly miniaturized with device, float
The electric charge that can store in grid is fewer and feweri.This leads to the threshold voltage of device to fluctuate and therefore lead to error.Further, since it is floating
Gate transistor structure needs two-layer gate dielectric layer, therefore, it is difficult to further miniaturization, because total grid medium thickness is larger.
Content of the invention
The purpose of the disclosure is to provide a kind of memory device and its manufacture method and access method at least in part.
According to an aspect of this disclosure, there is provided a kind of memory device, including：Substrate；The crystal being formed on substrate
Pipe, stacks source region and the drain region of both sides including grid stacking and grid；The capacitor arrangement being formed in the substrate, this capacitor arrangement
At least a portion extend to below the channel region of transistor, wherein, this memory device also includes capacitor arrangement and transistor
Drain region between tunnelling passage, this tunnelling passage is configured in transistor turns and the source region of transistor and capacitor arrangement
Between when there is certain voltage difference, by tunneling effect it is allowed to the carrier in transistor channel region enters capacitor arrangement
In or releasing capacitor structure in storage carrier.
According to another aspect of the present disclosure, there is provided a kind of method of manufacture memory device, including：Form ditch in the substrate
Groove；Form capacitor arrangement and tunnelling passage in the trench；On substrate formed transistor, this transistor include grid stacking and
The source region of grid stacking both sides and drain region are so that the channel region of this transistor is at least partially situated above capacitor arrangement, and leak
Area is adjoined with tunnelling passage；Wherein, tunnelling passage is configured in transistor turns and the source region of transistor and capacitor arrangement
Between when there is certain voltage difference, by tunneling effect it is allowed to the carrier in channel region enter in capacitor arrangement or
The carrier of storage in releasing capacitor structure.
A kind of another further aspect according to the disclosure, there is provided method that line access is entered to above-mentioned memory device, including：Pass through
Wordline applies conducting voltage so that transistor turns, and applies the first biasing so that carrier can enter by bit line to source electrode
Enter and be stored in capacitor arrangement, thus storing first state in this memory device；And electric conduction is applied by wordline
Pressure is so that transistor turns, and applies the second biasing so that carrier can be released from capacitor arrangement by bit line to source electrode
Put, thus storing the second state in this memory device, wherein, transistor threshold voltage in the first state is different from crystal
Pipe threshold voltage in the second condition.
According to the exemplary embodiment of the present invention, memory device includes being formed at the capacitor below the channel region of transistor
Structure.This capacitor arrangement can serve as the backgate of transistor, and therefore can be with the threshold voltage of controlling transistor.This storage
Device setting contributes to increasing the fluctuation that (in capacitor arrangement) stores the space of electric charge and therefore reduce threshold voltage.This
Outward, by optimizing the electrolyte leakage current between backgate electric capacity and drain region and backgate electric capacity, memory device disclosed herein can
For use as dynamic random access memory (DRAM).
Brief description
By the description to the embodiment of the present disclosure referring to the drawings, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 (a) shows the sectional view of the memory device according to one embodiment of the disclosure, and Fig. 1 (b) shows this
The sectional view that the example of memory device connects；
The showing of multiple stages in the flow process that Fig. 2-15 shows according to the manufacture memory device of another embodiment of the disclosure
It is intended to；
Figure 16 shows the schematic diagram of the access principle of the memory device according to another embodiment of the disclosure.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are simply exemplary
, and it is not intended to limit the scope of the present disclosure.Additionally, in the following description, eliminate the description to known features and technology, with
Avoid unnecessarily obscuring the concept of the disclosure.
Various structural representations according to the embodiment of the present disclosure shown in the drawings.These figures are not drawn to scale
, wherein for the purpose of clear expression, it is exaggerated some details, and some details may be eliminated.Shown by figure
Various regions, the shape of layer and the relative size between them, position relationship are only exemplary, in practice because of system
Make tolerance or technical limitations and deviation, and in addition those skilled in the art can design with difference according to actually required
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when by one layer/element be referred to as be located at another layer/element " on " when, this layer/element can
To be located immediately on this another layer/element, or between them, there may be intermediate layer/element.In addition, if in a kind of direction
In one layer/element be located at another layer/element " on ", then when turn towards when, this layer/element may be located at this another layer/unit
Part D score.
In accordance with an embodiment of the present disclosure, there is provided a kind of memory device (for example, flash memory).This memory device can include
On substrate formed transistor and formed in the substrate capacitor arrangement (therefore, it can formed 1T1C memorizer join
Put).At least a portion of this capacitor arrangement extends to below the channel region of transistor, and therefore, it is possible to serve as transistor
Backgate.
This memory device can also include the tunnelling passage between capacitor arrangement and transistor (for example, its drain region).Should
Tunnelling passage allows to pass through tunneling effect exchange charge (most current-carrying of such as transistor between transistor AND gate capacitor arrangement
Son, is electronics such as n-type device, is hole for p-type device).For example, such tunnelling passage can include and capacitor
Conductive channel between the adjacent tunnel dielectric layer of structure and this tunnel dielectric layer and transistor (for example, its drain region).
The thickness of this Tunneling dielectric is arranged to tunneling effect.Specifically, the thickness of tunnel dielectric layer can
To be arranged so that the carrier being flowed due to transistor turns for example deposited between the source region of transistor and capacitor arrangement
This dielectric layer, e.g., from about 0.3-15nm can be tunneled through in certain voltage difference.For example, when transistor turns and current-carrying
Sub (for example, electronics), when source region flows to drain region, carrier can pass through tunnel passage, and is tunneled through tunnel dielectric layer,
Hence into and be therefore stored in capacitor arrangement；On the other hand, when the transistor conducts, by source region and/or drain region
The suitable biasing of upper applying, so that the carrier (if present) of storage is tunneled through tunnelling electricity in capacitor arrangement
Dielectric layer, and discharged by conductive channel.So, this memory device can show (at least) two states：Capacitor arrangement
In be stored with electric charge, do not store electric charge in capacitor arrangement (for example, it is possible to the state by the electric charge that is stored with capacitor arrangement
It is considered logical one, and the state not storing electric charge in capacitor arrangement is considered logical zero；Vice versa).
On the other hand, because capacitor arrangement can serve as the backgate of transistor, the electric charge in backgate can affect transistor
Threshold voltage.So, whether store electric charge according in backgate capacitor, transistor can show different threshold voltages simultaneously
Therefore show different electrology characteristics.Therefore, it can the electrology characteristic according to transistor, to read the state of memory device
(or, " data ").
According to an example, capacitor arrangement and tunnelling passage can be formed at the groove extending to substrate interior from substrate surface
In.It is unlikely to affect the setting of transistor in order to backgate can either be formed, opening at substrate surface for this groove can position again
In transistor (for example, its drain region) side, and this groove can extend at least of channel region in the substrate from this side
Below point.So, groove can have from opening to the Part I of general vertical extension in substrate and from this Part I
The Part II extending generally transverse towards below channel region.That is, groove prolongs in the opening positioned at transistor side is to substrate
Stretch, and the roundabout region bypassing formation transistor.On the other hand, in order to realize electric charge storage/release, groove (for example, its first
Part) can adjoin with transistor (for example, its drain region) so that the tunnelling passage being formed in groove can be handed over and transistor between
Change electric charge.
In this case, capacitor arrangement can be implemented as groove-shaped capacitor.For example, capacitor arrangement can include
Capacitor dielectric on a part of inwall of groove and formation adjacent with capacitor dielectric in groove
Capacitor pole flaggy, and also the conductive region being adjoined with capacitor dielectric that can include being formed in the substrate (served as
Another pole plate of capacitor).The thickness of capacitor dielectric may be thicker than the thickness of tunnel dielectric layer, for example, about 1-
45nm.
According to an advantageous example of the disclosure, transistor is implemented as N-shaped (thus adulterating in its source region and drain region) for N-shaped.
In this case, when the transistor conducts, in channel region, the carrier of flowing is mainly electronics.Electronics is easier to be tunneled through
Tunnel dielectric layer, thus realize the storage/release of electric charge.Now, transistor can be formed in the p-type well region in substrate.
In addition, in the case that transistor is for n-type transistor, another pole plate of capacitor can be implemented as the n in substrate
Type well region.Now, for the ease of manufacturing the contact site with this pole plate of capacitor, can be formed in the substrate and extend from substrate surface
N-shaped doped region (with transistor isolation) to N-shaped well region.So, the contact site of this N-shaped doped region need to only be arrived it is possible to realize
Electrical contact to this pole plate of capacitor.
According to some examples of the disclosure, memory device can be as making of getting off.For example, it is possible to form ditch in the substrate
Groove, to form capacitor arrangement and tunnelling passage in the trench.Capacitor arrangement and tunnelling passage can by groove according to
Secondary filling dielectric layer and conductive layer, and suitably etched to be formed.Then, transistor can be formed on substrate.For example,
Grid stacking can be formed on substrate, and carry out suitable source drain implant to form transistor.Can be formed with control gate stacking
Position (it determines the position of channel region) so that channel region be at least partially situated in groove formed capacitor arrangement above,
So that capacitor arrangement potentially acts as backgate.In addition, in source drain implant, so that one of source region and drain region (for example, are leaked
Area) adjacent with the tunnelling passage of formation in groove, to realize effective charge-exchange.
Groove for example can be formed as including the general vertical Part I extending and second extended generally transverse
Point, as mentioned above.This groove for example can be formed by following manner.Specifically, ion implanting can be passed through, in substrate
The modified zone that middle formation extends generally transverse.Here, so-called " modified zone ", referring to can be with respect to region unmodified in substrate
There is the part of Etch selectivity.It is then possible to form the opening extending to this modified zone from substrate surface general vertical.This is opened
The lateral dimension of mouth can be less than the lateral dimension in this remodeling area.Via this opening, selective etch modified zone, it is gone
Remove.So, (opening corresponds roughly to " Part I ", and the space being formed after removing modified zone is substantially right to be the formation of groove
Ying Yu " Part II ").
According to an advantageous example, opening is located substantially in the middle part of modified zone.So, capacitor arrangement and tunnel are formed in the trench
After break-through road, can be in the approximate mid-section position formation isolation area of opening, and therefore, it is possible to lead to capacitor arrangement and tunnelling
Road is divided into two parts of electric isolution, and they may be respectively used for two different memory element.This is conducive to device integrated.
The disclosure can present in a variety of manners, some of them example explained below.
Fig. 1 (a) shows the sectional view of the memory device according to one embodiment of the disclosure.As shown in Fig. 1 (a), should
Memory device includes substrate 100.Substrate 100 can include body Semiconductor substrate such as Si, Ge, and compound semiconductor substrate is such as
SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, semiconductor-on-insulator substrate
(SO1) etc..For convenience of description, it is described below taking body silicon substrate and silicon systems material as a example.
This memory device is additionally may included in the transistor formed on substrate 100.Transistor includes being formed on the substrate 100
Grid stacking, including gate dielectric layer 128 and grid conductor layer 130.In addition, stacking both sides in grid, it is formed with grid side wall (spacer)
132.For example, gate dielectric layer 128 can include various suitable dielectric substances, preferably high-k dielectrics material, such as HfO2,
Its thickness for example, about 2-10nm.Grid conductor layer 130 can include polysilicon, metal such as Ti, Co, Ni, Al, W or its alloy etc.,
Its thickness for example, about 50-150nm.Include high-k dielectrics material in gate dielectric layer 128 and grid conductor layer 130 includes metal
In the case of, work function regulating course (not shown) can also be accompanied between them.Grid side wall 132 can include nitride (for example, nitrogen
SiClx), its thickness for example, about 40-100nm.In addition, this transistor is additionally included in the substrate of grid stacking both sides for example passing through
Ion implanting and the source/drain region 134 that formed.For example, source/drain region 134 includes n-type dopant, thus this transistor is N-shaped device
Part.The channel region of transistor grid stack below, between source region and drain region.
It is to be herein pointed out illustrate only a kind of sample implementation of transistor in Fig. 1.People in the art
Member knows applicable other transistor implementation numerous.In example below, so that transistor is as N-shaped as a example it is described.
It should be noted however that disclosure not limited to this.Those skilled in the art can be by suitably changing various doping polarity
And the technology of the disclosure is applied to p-type device.
This memory device is additionally may included in the capacitor arrangement formed in substrate 100, including capacitor dielectric
114th, the second pole plate that the conductive region 126 in conductive material is made the first pole plate 116 and substrate 100 is formed.Capacitor
Dielectric layer 114 can include various suitable dielectric substances, such as oxide (as silicon oxide), high-k dielectrics material such as
HfO2Or a combination thereof etc., its thickness for example, about 1-45nm.First pole plate 116 can include various suitable conductive materials, example
Polysilicon or metallic alloy such as TiN, W or a combination thereof as doping.Second pole plate 126 can include for example passing through ion implanting
And the well region (for example, N-shaped) being formed in substrate 100.Preferably, capacitor arrangement is with its transistor faced by dielectric layer 114
(particularly its channel region).That is, the second pole plate 126 is substantially shaped as adjoining with the lower surface of capacitor dielectric 114.
So, capacitor arrangement can serve as the backgate of transistor, and capacitor dielectric 114 for example can serve as backgate medium.
In addition, this memory device can also include the tunnelling passage between capacitor arrangement and the drain region of transistor, including
Tunnel dielectric layer 118 and conductive channel 120.Tunnel dielectric layer 118 is adjoined with capacitor arrangement, and on the one hand makes it possible to
To in capacitor arrangement, storage electric charge/release electric charge (for example, by tunneling effect) from capacitor arrangement, on the other hand will again
Capacitor arrangement is electrically insulated with transistor.Tunnel dielectric layer 118 can include various suitable dielectric substances, for example, aoxidize
Thing (as silicon oxide), low-k dielectric materials such as SiOF, SiCOH, SiO, SiCO, SiCON or a combination thereof etc., its thickness is, for example,
About 0.3-15nm.Conductive channel 120 can include various suitable conductive materials, the polysilicon of such as doping or metallic alloy
As TiN, W or a combination thereof.This conductive channel 120 can be made electrical contact with one of source/drain region 134 (for example, drain region).So, it is derived from
The electric charge of transistor can pass through this conductive channel 120, and is tunneled through in tunnel dielectric layer 118 entrance capacitor arrangement；
Or, in capacitor arrangement, the electric charge of storage can be tunneled through tunnel dielectric layer 118, and is released by conductive channel 120
Put.
According to an advantageous example, capacitor arrangement and tunnelling passage be formed so that capacitor arrangement (particularly its first
Pole plate 116) will not make electrical contact with the source/drain region 134 of transistor.For example, in the example of Fig. 1 (a), the entirety of capacitor arrangement
It is located substantially on below transistor, tunnel dielectric layer 118 can cover the first pole plate 116 in capacitor dielectric 114 phase
Anti- side whole surface (the first pole plate 116 capacitor dielectric 114 side surface by this capacitor dielectric
114 coverings), effectively to guarantee the electric isolution between capacitor arrangement and source/drain region 134.
In the example of Fig. 1 (a), transistor (and capacitor arrangement and tunnelling passage) is shown as being formed at by shallow ridges
Groove is isolated in the active area that (STI) 124 is isolated.In this case, well region 142 can be included in substrate 100 (for example, right
In n-type transistor, it is p-type well region), this well region 142 can serve as the body area (body) of transistor.In addition, showing in Fig. 1 (a)
In example, the second pole plate 126 (well region) of capacitor arrangement is formed as extending to outside this active area.As such, it is possible in this active area
It is easily manufactured into outward the contact site of the second pole plate 126.
Fig. 1 (b) shows the sectional view that the example of memory device shown in Fig. 1 (a) connects.As shown in Fig. 1 (b), Ke Yi
Deposit is for example passed through on the surface of structure shown in Fig. 1 (a) and forms interlevel dielectric layer 136.This interlevel dielectric layer 136 can wrap
Include various suitable dielectric substance such as oxides.Grid stacking, the source/drain region with transistor in this interlevel dielectric layer 136
At corresponding position, the contact site with them can be formed；Furthermore it is also possible to form the second pole plate with capacitor arrangement
126 contact site 138.In order to avoid formed extend in quasiconductor with the contact site of the second pole plate 126 directly contact (long and
It is not easy to make), can form conductive region 144 in substrate 100, for example, doping polarity (in this example for N-shaped) and the
Two pole plate 126 identical doped region.So, contact site 138 can be electrically connected with the second pole plate 126 by this conductive region 144
Connect.
The showing of multiple stages in the flow process that Fig. 2-15 shows according to the manufacture memory device of another embodiment of the disclosure
It is intended to.
As shown in Fig. 2 providing substrate 1000, such as body silicon substrate.On substrate 1000, for example, can be formed by deposit
Pad (pad) oxide skin(coating) 1002 of one thin (for example, thickness is about 3-20nm).Have necessarily to be formed in this substrate 1000
The groove of horizontal expansion, can be carried out as follows process.
Specifically, photoresist 1004 can be formed on pad oxide skin(coating) 1002, and it is patterned, with shape wherein
Become opening.The lateral dimension of this opening substantially determines the lateral extension of the groove subsequently being formed in the substrate, for example,
About 60-460nm.Subsequently, carry out ion implanting (implant n-type impurity in this example), to form embedment in substrate 1000
Modified zone 1006.Control the energy of ion implanting so that modified zone 1006 is at a certain distance from the lower face of substrate 1000.
Photoresist 1004 can be removed afterwards.
Then, as shown in figure 3, deposit can for example be passed through on pad oxide skin(coating) 1002 to form mask layer 1008.For example,
Mask layer 1008 includes nitride, and thickness is about 50-200nm.On mask layer 1008, form photoresist 1010, and it is entered
Row composition, to form opening wherein.The lateral dimension of this opening can be less than the lateral dimension of modified zone 1006, for example, about
20-100nm, and may be located at the approximate mid-section of modified zone 1006.
Subsequently, as shown in figure 4, with the photoresist 1010 of composition as mask, successively to mask layer 1008, pad oxide skin(coating)
1002 and substrate 1000 perform etching, such as reactive ion etching (RIE).Etching may proceed to reach modified zone 1006 so that its
Till exposing.Afterwards, photoresist 1010 can be removed.
Because modified zone 1006 is exposed, can be as shown in figure 5, with respect to the unaltered portion in substrate 1000, selectivity
Etching modified zone 1006, thus form groove 1012 in substrate 1000.Groove 1012 can include the of general vertical extension
The a part of 1012-1 and Part II 1012-2 extending generally transverse.
Here, in order to more effectively remove the residual impurity around modified zone 1006, can enter to substrate 1000 further
Row necessarily etches a little.So, groove 1012 can be to its periphery slight enlargement.Preferably, as shown in fig. 6, the ditch ultimately forming
The roof of the Part II 1012-2 of groove 1012 can be about 10-50nm away from substrate surface apart from D, is guaranteed with one side
Form transistor above it, on the other hand guarantee that the capacitor being formed in groove 1012 can be carried out to transistor as backgate
Effect (for example, the threshold voltage of controlling transistor).
Next, capacitor arrangement and tunnelling passage can be formed in groove 1012 formed as discussed above.
Specifically, as shown in fig. 6, for example the electric capacity of one thin (such as thickness is about 1-45nm) can be formed by deposit
Device dielectric layer 1014.This capacitor dielectric 1014 can include oxide, high-k dielectrics or a combination thereof.It is then possible to
The polysilicon of filling conductive material such as doping or metal, to form capacitor pole flaggy 1016 in the trench.For example, this can lead to
Crossing depositing conductive material makes it be full of groove, is then etched back to be formed.According to an advantageous example, conductive material is etched back to its base
It is only positioned in basis in the Part II 1012-2 of groove.This advantageously ensures that between capacitor arrangement and the transistor subsequently forming
Isolation.According to another advantageous example, after eat-back conductive material, further isotropism can also be carried out to conductive material
Etching is so that capacitor pole flaggy 1016 is recessed in the horizontal with respect to the Part I 1012-1 of groove, as shown in Figure 7.This
Kind laterally recessed contribute to improving subsequently form isolation in the groove in the case of led to due to dislocation that may be present
Ohmic contact problem.
Then, as shown in figure 8, for example tunnel dielectric layer 1018 and conductive material can be sequentially formed by deposit
1020.For example, tunnel dielectric layer 1018 includes oxide, low-K dielectric or a combination thereof, and thickness is about 0.3-15nm.Conductive
Material 1020 can include polysilicon or the metal adulterating, and it is full of groove 1012.
Next, as shown in figure 9, conductive material 1020 can be etched back.According to an advantageous example, by conductive material
It is etched back to it to be substantially only positioned in the Part II 1012-2 of groove.According to another advantageous example, in eat-back conductive material
It is also possible to further isotropic etching be carried out to conductive material 1020 so as to Part I with respect to groove after 1020
1012-1 is recessed in the horizontal.Its recessed degree is relatively small, not destroy tunnel dielectric layer 1018 to capacitor pole flaggy
1016 encapsulating.
It is then possible to the Tunneling dielectric layer segment that the conductive material 1020 after eat-back is exposed and capacitor dielectric
Part carries out selective etch successively.Because conductive material 1020 is substantially only positioned in the Part II 1012-2 of groove, and
Can be recessed in the horizontal with respect to the Part I 1012-1 of groove, such that it is able to guarantee to remove the Part I of groove
Dielectric layer 1014 and 1018 (conductive channel subsequently manufacturing is passed through this side wall and made electrical contact with transistor) on the wall of 1012-1 side.
Next, as shown in Figure 10, (for example, being then etched back by deposit) conduction material can be filled further in groove
The polysilicon of material such as doping or metal.This conductive material can be identical or different with conductive material 1020, and they are constituted together leads
Electric channel.In the following description, both will not be distinguished, and they will be collectively shown as 1020.Favorably show according to one
Example, the top surface of conductive channel 1020 is not less than the surface of substrate 1000.As such, it is possible to conductive channel 1020 with formed afterwards
Form good Ohmic contact between transistor.
In the case of manufacturing multiple memory devices (for example, manufacturing memory cell array), each memorizer can also be formed
Isolation between part, such as STI.Specifically, as shown in figure 11, photoresist 1022 can be formed in the structure shown in Figure 10,
And be patterned be need formed STI position there is opening.One of opening can be located substantially at first of groove
Divide the middle part of 1012-1.Finally, with the photoresist 1022 of this composition as mask, perform etching such as RIE, to form groove T.Pass through
The filling dielectric such as oxide in groove T, forms STI1024, as shown in figure 12.By STI1024, by capacitor arrangement and
Tunnelling channel separation is two parts, and they may be respectively used for two different memory devices.Afterwards, for example can be by heat
Phosphoric acid, removes mask layer 1008.
So, STI technique is effectively incorporated in the technique of this technology, is favorably improved manufacture efficiency.But, this public affairs
Open not limited to this.For example, it is possible to first form STI in the substrate to isolate the active area of each device, then shape in each active area
Become corresponding memory device.In this case, capacitor arrangement fabricated as described above and tunnelling passage can be formed at individually
Active area in, thus being only used for single memory device (being equivalent to the situation that there is not middle STI in Figure 12).In addition,
In this case, the Part I 1012-1 of groove can be in alignment with one end of Part II 1012-2.That is, formed " └ " or
" ┘ " type groove, rather than above-mentioned " ⊥ " type groove.
Then, as shown in figure 13, ion implanting (in this example, implant n-type impurity) can be passed through, in substrate 1000
Form conductive well region 1026, to serve as another pole plate of capacitor arrangement.After ion implantation, can be annealed, to swash
The impurity of injection alive.Here, the energy of ion implanting can be controlled so that conductive well region 1026 is substantially only situated between with capacitor electricity
The downside surface of matter layer 1014 adjoins.According to an advantageous example, conductive well region 1026 can be formed as crossing on the downside of it
STI1024, thus this pole plate of each capacitor links together.As such, it is possible to provide shared contact site for all capacitors,
To electrically connect with their this pole plate.
Although form implant in this example in the trench forms conductive well region 1026 later, the disclosure does not limit
In this.For example, it is possible to be formed for conductive well region 1026 after formation groove 1012 as shown in Figure 5.
So, capacitor arrangement and tunnelling passage are just completed.Subsequently, can come in substrate according to various appropriate process
On 1000, (in the active area of particularly STI1024 isolation) forms transistor.For example, as shown in figure 14, can be aoxidized with removal pad
Nitride layer 1002.Then, gate dielectric layer 1028 and grid conductor layer 1030 are sequentially formed on substrate 1000, and structure is carried out to them
Figure, to form grid stacking.It is then possible to grid are stacked as mask, carry out haloing (halo) injection and extension area (extension) note
Enter.Then, form grid side wall 1032 in grid stacking both sides, and with grid stacking and grid side wall as mask, carry out source/drain (S/D) note
Enter.Can be annealed, to activate the impurity of injection, and therefore be formed source/drain region 1034.According to an advantageous example, removing
After pad oxide skin(coating) 1002, ion implanting can be carried out, to form p-type well region (not shown) in substrate 1000, serve as crystalline substance
Ti Guanti area.
So, just obtained the memory device according to this embodiment.As shown in figure 14, this memory device can be included in lining
The transistor being formed on bottom 1000 and capacitor arrangement (thus forming the configuration of 1T1C).Capacitor arrangement extends to transistor
It is possible to serve as the backgate of transistor below channel region (below grid stacking, being sandwiched between source region and drain region).Specifically,
Capacitor arrangement can be with its capacitor dielectric 1014 in the face of channel region.One of conductive channel 1020 and source/drain region are (for example,
Drain region) 1034 electrical contacts.In addition, pressing from both sides between conductive channel 1020 and capacitor arrangement (specifically, capacitor pole flaggy 1016)
There is tunnel dielectric layer 1018.Thus it is possible, on the one hand, not being conductively connected between capacitor arrangement and transistor；On the other hand, electricity
Lotus can be tunneled through tunnel dielectric layer 1018 again, such that it is able to the storage electric charge/from capacitor arrangement in capacitor arrangement
Release electric charge.
After memory device formed as discussed above, various electrical contacts can also be formed.As shown in figure 15, can be in Figure 14
Interlayer dielectric (ILD) layer 1036 is deposited on the surface of shown structure.This ILD layer 1036 for example can include oxide.Permissible
Planarization process such as CMP is carried out to ILD layer 1036 so as to surface general planar.Then, for example can pass through photoetching, be formed
Contact hole, and fill conductive material such as metal (for example, W or Cu etc.) in the contact hole, to form contact site 1038, such as with grid
The contact site of the contact site of stacking and source/drain region and the contact site with capacitor arrangement (particularly conductive well region 1026).Root
According to an advantageous example, can be connected to the wordline of memory device with the contact site of grid stacking, can be connected with the contact site of source region
Bit line to memory device.
In addition, in order to reduce contact resistance, silicidation can also be carried out, to form gold before forming ILD layer 1036
Belong to silicide 1040.
Below, the storage according to the embodiment of the present disclosure will be described in conjunction with Figure 16 (corresponding to the memory device shown in Fig. 1 (b))
The operation principle of device.
For example, it is possible to make conductive well region 126 be grounded by contact site 138, make the drain region of transistor electrically floating, and pass through position
The source region of transistor is carried out certain negative bias by line.In this case, when by wordline to grid 130 apply conducting voltage
And when making transistor turns, there may be the carrier from source region to drain region (in this example, being electronics) flowing.These current-carrying
Son can pass through conductive channel 120, and is tunneled through tunnel dielectric layer 118, and enter and be therefore stored in capacitor arrangement
In, as shown in the solid arrow in Figure 16.
On the other hand, conductive well region 126 can be made to be grounded by contact site 138, make the drain region of transistor electrically floating, and lead to
Cross bit line and the source region of transistor is carried out certain positive bias.In this case, when by wordline to grid 130 apply conducting
Voltage and when making transistor turns, can be by the electric charge storing in capacitor arrangement (if present) pull-out capacitor knot
Structure, as shown in the dotted arrow in Figure 16.As such, it is possible to discharge to capacitor arrangement.
Therefore, this memory device at least can store two states：Be stored with capacitor arrangement the state (example of electric charge
As logical one can be considered as), and the state (for example, it is possible to being considered as logical zero) not storing electric charge in capacitor arrangement.
In capacitor arrangement, the presence or absence of electric charge can affect the threshold voltage of transistor and (for example, for n-type device, deposits in capacitor arrangement
The threshold voltage vt 1 containing transistor during electronics can be higher than the threshold value electricity of transistor when not storing electronics in capacitor arrangement
Pressure Vt2), thus transistor can externally show different electrology characteristics.Can be poor according to this electrology characteristic of transistor
Different, the storage state of memory device is detected.
For example, when needing memory device is read out, conductive well region 126 can be made to be grounded by contact site 138, lead to
Crossing contact site makes drain region be grounded it is possible to bit line is precharged to predetermined voltage.At this point it is possible to apply one by wordline to grid
Fixed biasing.This biasing for example can be between Vt1 and Vt2.Now, the voltage on bit line is by the state according to memory device
Different.For example, when memory device is " 0 " state (threshold voltage vt 2, relatively low), the biasing that wordline applies can make crystal
Pipe turns on.Now, the voltage on bit line will be changed due to the electric current between the source region of transistor and drain region.And work as memory device
For (threshold voltage vt 1, higher) during one state, the biasing that wordline applies is insufficient to allow transistor turns.Now, on bit line
Voltage will not change.Therefore, it can the difference according to bit-line voltage, the state of storage in reading memory device is (or, " count
According to ").
In addition, for example can be similar with the operation of write " 0 " to the erasing operation of memory device.
In the above description, the ins and outs such as the composition of each layer, etching are not described in detail.But
It will be appreciated by those skilled in the art that layer, region of required form etc. can be formed by various technological means.In addition, being
Formation same structure, those skilled in the art can be devised by the not identical method with process as described above.
Although in addition, respectively describing each embodiment above, but it is not intended that the measure in each embodiment can not be favourable
Be used in combination.
Embodiment of this disclosure is described above.But, the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by claims and its equivalent.Without departing from this public affairs
The scope opened, those skilled in the art can make multiple replacements and change, and these substitute and modification all should fall in the disclosure
Within the scope of.
Claims (18)
1. a kind of memory device, including：
Substrate；
The transistor being formed on substrate, stacks source region and the drain region of both sides including grid stacking and grid；
The capacitor arrangement being formed in the substrate, at least a portion of this capacitor arrangement extends under the channel region of transistor
Side,
Wherein, this memory device also includes the tunnelling passage between capacitor arrangement and the drain region of transistor, this tunnelling passage quilt
When being configured in transistor turns and there is certain voltage difference between the source region of transistor and capacitor arrangement, imitated by tunnelling
Should be it is allowed to the carrier in transistor channel region enters the current-carrying storing in capacitor arrangement or in releasing capacitor structure
Son.
2. memory device according to claim 1, wherein, tunnelling passage includes：
The tunnel dielectric layer adjacent with capacitor arrangement；And
Conductive channel between this tunnel dielectric layer and drain region,
Wherein, the thickness of described tunnel dielectric layer is arranged so that and described tunneling effect can occur.
3. memory device according to claim 2, wherein, the thickness of tunnel dielectric layer is 0.3-15nm.
4. memory device according to claim 1, wherein,
Capacitor arrangement and tunnelling passage are formed at from the groove that substrate surface extends to substrate interior, and wherein this groove is in lining
The opening of bottom surface is located at drain region side, and this groove extends at least of channel region in the substrate from drain region side
Below point.
5. memory device according to claim 4, wherein, this groove is in roof below transistor away from substrate surface
Distance is 10-50nm.
6. memory device according to claim 4, wherein,
Capacitor arrangement includes capacitor dielectric on a part of inwall of groove and in groove and capacitor
The capacitor pole flaggy of the adjacent formation of dielectric layer, and also include formed in the substrate with capacitor dielectric adjoin
Conductive region.
7. memory device according to claim 6, wherein, the thickness of capacitor dielectric is 1-45nm.
8. memory device according to claim 6, wherein, transistor is n-type transistor, and conductive region is in substrate
N-shaped well region.
9. memory device according to claim 8, also includes the p-type well region being formed in substrate, the wherein source of transistor
Area and drain region are formed in this p-type well region.
10. memory device according to claim 8, also includes extending to the N-shaped doped region of N-shaped well region from substrate surface,
Wherein N-shaped well region can be externally connected by this N-shaped doped region.
A kind of 11. methods manufacturing memory device, including：
Form groove in the substrate；
Form capacitor arrangement and tunnelling passage in the trench；
Transistor is formed on substrate, this transistor includes grid stacking and grid stack the source region of both sides and drain region so that this crystalline substance
The channel region of body pipe is at least partially situated above capacitor arrangement, and drain region is adjoined with tunnelling passage；
Wherein, tunnelling passage is configured in transistor turns and exists certain between the source region of transistor and capacitor arrangement
During voltage difference, by tunneling effect it is allowed to the carrier in channel region enters in capacitor arrangement or releasing capacitor structure
The carrier of middle storage.
12. methods according to claim 11, wherein, form groove and include：
By ion implanting, form modified zone in the substrate；
Form the opening extending to modified zone from substrate surface；
Via opening, selective etch modified zone.
13. methods according to claim 12, also include：
Via opening, a certain amount of substrate of further selective etch.
14. methods according to claim 11, wherein, form capacitor arrangement and tunnelling passage include：
Form capacitor dielectric on forming fluted substrate；
Fill the first conductive material in the trench and be etched back, to form capacitor pole flaggy；
Form tunnel dielectric layer；
Fill the second conductive material in the trench and be etched back；
Selective etch is exposed by the second conductive material after being etched back successively Tunneling dielectric layer segment and capacitor dielectric
Layer segment；
Fill the 3rd conductive material further in the trench；And
By ion implanting, form the conductive well region serving as another pole plate of capacitor arrangement in the substrate.
15. methods according to claim 14, wherein, the top surface of the 3rd conductive material is not less than the surface of substrate.
16. methods according to claim 11, also include：
Form isolation area, the capacitor arrangement being formed in groove and tunnelling passage are divided into two portions of electric isolution by this isolation area
Point.
A kind of 17. methods that line access is entered to memory device according to claim 1, including：
Conducting voltage is applied so that transistor turns by wordline, and the first biasing is applied to source electrode by bit line so that current-carrying
Son can enter and be stored in capacitor arrangement, thus storing first state in this memory device；And
Conducting voltage is applied so that transistor turns by wordline, and the second biasing is applied to source electrode by bit line so that current-carrying
Son can discharge from capacitor arrangement, thus storing the second state in this memory device,
Wherein, transistor threshold voltage in the first state is different from transistor threshold voltage in the second condition.
18. methods according to claim 17, also include：
Bit line is precharged to a voltage；
One bias voltage is applied on wordline；And
Whether changed according to the voltage on bit line, to determine storage first state or the second state in memory device,
Wherein, between the threshold voltage under described bias voltage threshold voltage and the second state in the first state.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310138397.6A CN104112747B (en) | 2013-04-19 | 2013-04-19 | Memory device, manufacturing method and access method of memory device |
| PCT/CN2013/076481 WO2014169505A1 (en) | 2013-04-19 | 2013-05-30 | Memory device, and manufacturing method and access method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310138397.6A CN104112747B (en) | 2013-04-19 | 2013-04-19 | Memory device, manufacturing method and access method of memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104112747A CN104112747A (en) | 2014-10-22 |
| CN104112747B true CN104112747B (en) | 2017-02-08 |
Family
ID=51709478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310138397.6A Active CN104112747B (en) | 2013-04-19 | 2013-04-19 | Memory device, manufacturing method and access method of memory device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104112747B (en) |
| WO (1) | WO2014169505A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113206093B (en) * | 2021-04-29 | 2022-10-21 | 复旦大学 | Dynamic random access memory and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1236996A (en) * | 1998-05-27 | 1999-12-01 | 世界先进积体电路股份有限公司 | Memory cell structure with piled grids and its manufacture method |
| US6009011A (en) * | 1996-12-27 | 1999-12-28 | Sharp Kabushiki Kaisha | Non-volatile memory and method for operating the same |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06244384A (en) * | 1993-02-19 | 1994-09-02 | Sony Corp | Complex memory cell having compounded dram cell and non-volatile memory cell and manufacture thereof |
| US6700154B1 (en) * | 2002-09-20 | 2004-03-02 | Lattice Semiconductor Corporation | EEPROM cell with trench coupling capacitor |
| KR100640616B1 (en) * | 2004-12-21 | 2006-11-01 | 삼성전자주식회사 | Field effect transistor structure comprising a buried gate pattern and method of manufacturing a semiconductor device comprising the field effect transistor structure |
| CN100446257C (en) * | 2005-10-12 | 2008-12-24 | 茂德科技股份有限公司 | Dynamic random access memory and mfg. method thereof |
| US7705387B2 (en) * | 2006-09-28 | 2010-04-27 | Sandisk Corporation | Non-volatile memory with local boosting control implant |
| CN101174621B (en) * | 2006-11-01 | 2010-07-21 | 力晶半导体股份有限公司 | Semiconductor device with capacitor and its producing method |
| CN102938406B (en) * | 2012-11-21 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory and forming method thereof |
-
2013
- 2013-04-19 CN CN201310138397.6A patent/CN104112747B/en active Active
- 2013-05-30 WO PCT/CN2013/076481 patent/WO2014169505A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6009011A (en) * | 1996-12-27 | 1999-12-28 | Sharp Kabushiki Kaisha | Non-volatile memory and method for operating the same |
| CN1236996A (en) * | 1998-05-27 | 1999-12-01 | 世界先进积体电路股份有限公司 | Memory cell structure with piled grids and its manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104112747A (en) | 2014-10-22 |
| WO2014169505A1 (en) | 2014-10-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9627399B2 (en) | Three-dimensional memory device with metal and silicide control gates | |
| US9666594B2 (en) | Multi-charge region memory cells for a vertical NAND device | |
| US10453798B2 (en) | Three-dimensional memory device with gated contact via structures and method of making thereof | |
| US10256248B2 (en) | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof | |
| CN104134668B (en) | Memory device and fabrication method and access method thereof | |
| US8564046B2 (en) | Vertical semiconductor devices | |
| KR100718255B1 (en) | DRAM device and method for manufacturing the same | |
| US8058162B2 (en) | Nonvolatile semiconductor memory and method of manufacturing the same | |
| US11637119B2 (en) | Three-dimensional memory device containing auxiliary support pillar structures and method of making the same | |
| US11706920B2 (en) | Three-dimensional memory devices and fabrication methods thereof | |
| CN106684088A (en) | Nitride-free spacer or oxide spacer for embedded flash memory | |
| CN113540111B (en) | Three-dimensional memory device and manufacturing method thereof | |
| CN104112748B (en) | Memory device and manufacture method thereof and access method | |
| KR101198532B1 (en) | 3D Non-volatile memory device | |
| US7952133B2 (en) | Flash memory and method for manufacturing the same | |
| US20230389325A1 (en) | Memory devices and methods of manufacturing thereof | |
| US11637118B2 (en) | Three-dimensional memory device containing auxiliary support pillar structures and method of making the same | |
| US11398497B2 (en) | Three-dimensional memory device containing auxiliary support pillar structures and method of making the same | |
| CN105845686A (en) | Integration techniques for plate capacitors with flash memory and/or high-k metal gate CMOS technology | |
| US20230369429A1 (en) | Tri-gate orthogonal channel transistor and methods of forming the same | |
| KR20170055031A (en) | Capacitorless 1t dram cell device using tunneling field effect transistor, fabrication method thereof and memory array using the same | |
| US20100032762A1 (en) | Stack-Type Semiconductor Device | |
| CN104112747B (en) | Memory device, manufacturing method and access method of memory device | |
| CN104241289B (en) | Memory device and its manufacturing method | |
| CN116097919A (en) | Preparation method of three-dimensional memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |