CN104104410A - Descrambling and despreading device for data channel - Google Patents
Descrambling and despreading device for data channel Download PDFInfo
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- CN104104410A CN104104410A CN201310116377.9A CN201310116377A CN104104410A CN 104104410 A CN104104410 A CN 104104410A CN 201310116377 A CN201310116377 A CN 201310116377A CN 104104410 A CN104104410 A CN 104104410A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
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- H04B2201/70714—Reducing hardware requirements
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Abstract
The invention provides a descrambling and despreading device for a data channel. The descrambling and despreading device comprises a chip rotation and associated circuit and a chip accumulation and rotation circuit. The chip rotation and associated circuit uses S one-from-two switches to choose antenna data of S chips which participates the associated accumulation from antenna data of 2S chips ant_data0ant_data (2S-1) according to the chip offset chip_offset, performs associated operations on antenna data of S chips and pseudo-random random chips, and outputs the S chips after the association Chip0-Chip (S-1), wherein S=2X, 0<=chip_offset<S, S,X,and chip_offset are integers. The chip accumulation and rotation circuit is used for performing accumulation on the adjacent SF chips in the Chip0-Chip(S-1) according to the spreading factors SF, rotating the chips in the process of the accumulation and obtaining associated accumulation result of the S chips which are correctly sorted, wherein the SF=2j, j is an integer. The descrambling and despreading device of the invention can reduce multiplexers required by the descrambling and dispreading of the data channel and can reduce the realization area.
Description
Technical field
The present invention relates to the communications field, more specifically, relate to a kind of descrambling and de-spreading device for data channel.
Background technology
UMTS (Universal Mobile Telecommunications System, Universal Mobile Telecommunications System) as a complete 3G mobile communication technology standard, the first-selected WCDMA (Wideband Code Division Multiple Access, Wideband Code Division Multiple Access (WCDMA)) that adopts is as its air-interface standard.WCDMA belongs to spread spectrum communication, adopts Bidirectional closed-loop power control, transmits and receives diversity, RAKE receives the technology such as anti-multipath fading, convolution code and Turbo code channel decoding.
Mobile telecommunication channel and fixed communication channel are very different, the electromagnetic wave that when receiver moves, antenna is received can be arrived by straight line after transmitter antenna transmitting, also can after the mulitpath delay transits such as reflection, diffraction, arrive, therefore receiving signal has a lot of multipath (finger) time delay, these multipath results interfere with each other, and form the multipath fading of wireless channel.
At WCDMA band receiver of base end, utilize the correlation of Pilot PN code, to received signal in distinguishable multipath component follow the tracks of respectively, receive, the output baseband signal walking along the street footpath of going forward side by side merges, the mode of this reception signal is called RAKE correlation reception.RAKE receives each multipath is carried out respectively to correlation demodulation, and these Correlation Demodulators are also referred to as multipath reception device (RAKE fingers), then the output of these multipath reception devices are merged, and send into channel decoder and carry out processing below.RAKE correlation reception utilizes multipath component, has increased equivalently the transmitting power receiving, and reaches the object of anti-multipath fading.
In addition, in order to make the high speed data transfers of WCDMA support uplink, the R6 of 3rd Generation Partnership Project (3GPP) has introduced enhancement mode physical uplink channel E-DCH (Enhanced Dedicated Channel, enhancement mode physical channel), it allows minimum SF (Spreading Factor, spreading factor) to equal 2.
For data channel demodulation, it is the first step that chip-level is processed, chip-level is processed multipath tracking and the descrambling and de-spreading function that mainly completes WCDMA physical layer, sampled data is changed into symbol data, and descrambling and de-spreading is chip data to be converted into the key technology of symbol data.
Data channel demodulation generally adopts secondary despreading mode, and in the descrambling and de-spreading processing procedure the present invention relates to, 32 chips (chip) of usining are correlated with and are added up as Yi Ge unit, are referred to as an IP (Iteration Period).Between a plurality of multipaths (finger), there is chip offset (chip offset) in same channel, with respect to antenna system regularly, after having and first having.Because the chip offset of different multipaths is different, want the antenna data of 32 chips of demodulation, in the situation that peak excursion is 1 IP, just need to once read the antenna data of 64 chips, then according to finger chip offset separately, from 64 chips, take out 32 chips and be correlated with and add up.This selection course of taking out 32 chips from 64 chips, is referred to as the phase rotating of chip.
The method of common phase rotating, from 64 chips, according to chip offset, select 32 chips exactly, and in the implementation procedure of circuit design, because the span of chip offset is 0～31, to need N individual 32 to select 1 MUX (MUX), if the data of each chip are 12bit, need to select 32 chips, need altogether 384 32 to select 1 MUX.The circuit delay that this method realizes is long again, and area is large (32 areas that select 1 MUX to take in circuit realization are larger) again.Even if be divided into two-stage, 384 8 of the first order are selected 1 MUX, and 1 MUX is selected in 384 4 of the second level, and time delay relatively can be short, but the number of MUX still can not reduce.
Summary of the invention
For solving technological deficiency described above, the invention provides and a kind ofly can reduce required MUX, reduce to realize the descrambling and de-spreading device of the data channel of area.
For solving the problems of the technologies described above, the present invention takes following technical scheme:
A descrambling and de-spreading device for data channel, this device comprises:
Chip rotation and interlock circuit, be used for according to chip offset chip_offset, with S either-or switch, from 2S chip antenna data ant_data0～ant_data (2S-1), choose and participate in relevant S cumulative chip antenna data, then this S chip antenna data and pseudo noise code are done to associative operation, S chip Chip0～Chip (S-1) after output is relevant, wherein, S=2
x, 0 <=chip_offset < S, S, X, chip_offset are positive integer;
Chip adds up and rotation circuit, for according to spreading factor SF, adjacent S F the chip of Chip0～Chip (S-1) being added up, and in cumulative process, chip is rotated, and obtains the relevant accumulation result of S chip of correct sequence, wherein, and SF=2
j, j is positive integer.
Preferably, chip rotation and interlock circuit comprise:
Either-or switch circuit, comprise S either-or switch Switch_i, each either-or switch Switch_i according to a gating signal select_i from input two chip antenna data ant_data (i) and ant_data (i+S) selection an output, wherein, i=0,1 ..., (S-1);
Decoding circuit, for generate the gating signal select_i of each either-or switch according to chip offset chip_offset, make when i < chip_offset, either-or switch Switch_i exports ant_data (i+S), during i >=chip_offset, either-or switch Switch_i exports ant_data (i);
Chip interlock circuit, for chip and the pseudo noise code of the output of either-or switch circuit are carried out to associative operation, S the chip Chip0～Chip (S-1) after output is relevant.
Preferably, chip adds up and rotation circuit comprises X rank circuit, wherein:
Firstorder circuit comprises 2
(X-1)individual the 1st exponent arithmetic(al) unit step0_M and 2
(X-1)individual latch units, M=0,1 ... (2
(X-1)-1), wherein:
Each the 1st exponent arithmetic(al) unit step0_M comprises a cumulative rotary unit, be used at chip_offset[0]=0 o'clock, the accumulation result of output Chip (2M) and Chip (2M+1), at chip_offset[0]=1 o'clock, the accumulation result of output Chip (2M+1) and Chip (2M+2);
Each latch units is exported for after the output step0_symbol (M) of the 1st exponent arithmetic(al) unit step0_M of correspondence is latched to a timeticks;
X rank circuit comprises 2
(X-x)individual x exponent arithmetic(al) unit step (x-1) _ Z and 2
(X-x)individual latch units, x=2,3 ..., (X-1), Z=0,1 ... (2
(X-x)-1), wherein:
Each x exponent arithmetic(al) unit step (x-1) _ Z comprises a cumulative rotary unit, be used at chip_offset[x-1]=0 o'clock, the accumulation result of output step (x-2) _ symbol (2Z) and step (x-2) _ symbol (2Z+1), at chip_offset[x-1]=1 o'clock, the accumulation result of output step (x-2) _ symbol (2Z+1) and step (x-2) _ symbol (2Z+2);
Each latch units is exported for after output step (x-1) _ symbol (Z) of x exponent arithmetic(al) unit step (the x-1) _ Z of correspondence is latched to a timeticks;
X rank circuit comprises an X exponent arithmetic(al) unit and a latch units, wherein:
This X exponent arithmetic(al) unit step (X-1) _ 0 comprises an adder, for by output step (the X-2) _ symbol (0) of two X-1 exponent arithmetic(al) unit and step (X-2) _ symbol (1);
This latch units, for exporting after timeticks of the output latch of this adder, obtains the relevant accumulation result of S chip of correct sequence.
Preferably, the cumulative rotary unit in the 1st exponent arithmetic(al) unit step0_M comprises:
Either-or switch, at gating signal chip_offset[0]=1 o'clock, from two input Chip (2M) and Chip (2M+2), select Chip (2M+2) output, at chip_offset[0]=0 o'clock, selection Chip (2M) exports;
Adder, for output after the output of the either-or switch of same unit and Chip (2M+1) is cumulative;
Cumulative rotary unit in x exponent arithmetic(al) unit step (x-1) _ Z comprises:
Either-or switch, be used at gating signal chip_offset[x-1]=1 o'clock, from two input step (x-2) _ symbol (2Z) and step (x-2) _ symbol (2Z+2), select step (x-2) _ symbol (2Z+2) output, at chip_offset[1]=0 o'clock, step (x-2) _ symbol (2Z) output selected;
Adder, for output after the output of the either-or switch of same unit and step (x-2) _ symbol (2Z+1) is cumulative.
Preferably, each x exponent arithmetic(al) unit step (x-1) _ Z also comprises an x rank bypass rotary unit step (x-1) _ Z_BR and x rank selected cell step (x-1) _ Z_SL, x=2, and 3 ..., X, Z=0,1 ... (2
(X-x)-1), wherein:
X rank bypass rotary unit step (x-1) _ Z_BR comprises (x-1) individual bypass gyrator unit step (x-1) _ Z_BR (2
j), bypass gyrator unit step (x-1) _ Z_BR (2
j) for SF=2
jtime bypass and rotation to input chip, j=1,2 ..., (x-1), at Z+1 <=chip_offset[p:q] < Z+2
(X-x)+ 1 o'clock, front 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), rear 2
(X-x)clap output step (x-2) _ symbol (Z), at chip_offset[p:q] < Z+1 or chip_offset[p:q] >=Z+2
(X-x)+ 1 o'clock, front 2
(X-x)clap output step (x-2) _ symbol (Z), rear 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), q=j, p=j+X-x;
X rank selected cell step (x-1) _ Z_SL is connected with (x-1) individual bypass gyrator unit in x exponent arithmetic(al) unit step (x-1) _ Z and the output of cumulative rotary unit, in SF <=2
(x-1)time, output step (the x-1) _ symbol (Z) using the output of bypass gyrator unit step (x-1) _ Z_BR (SF) as this x exponent arithmetic(al) unit step (x-1) _ Z, at SF > 2
(x-1)time, output step (the x-1) _ symbol (Z) using the output of this cumulative rotary unit as this x exponent arithmetic(al) unit step (x-1) _ Z.
Preferably, bypass gyrator unit step (x-1) _ Z_BR (2
j) comprising:
X rank decoder, for according to chip offset and timeticks output gating signal, makes at Z+1 <=chip_offset[p:q] < Z+2
(X-x)+ 1 o'clock, the either-or switch of same subelement was front 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), rear 2
(X-x)clap output step (x-2) _ symbol (Z), at chip_offset[p:q] < Z+i or chip_offset[p:q] >=Z+2
(X-x)+ 1 o'clock, the either-or switch of same subelement was front 2
(X-x)clap output step (x-2) _ symbol (Z), rear 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x));
Either-or switch, for according to the gating signal of the x rank decoder output of same subelement, inputs step (x-2) _ symbol (Z) and step (x-2) _ symbol (Z+2 from two
(X-x)) output of middle selection.
Preferably, S=2,4,8,16,32,64,128 or 256.
Preferably, this descrambling and de-spreading device, for a descrambling and de-spreading of WCDMA system data channel demodulation, is supported the various SF of this system regulation, and wherein SF minimum is 2.
Take above-described technical scheme, compare with common descrambling and de-spreading, reduced the quantity of the required MUX of using, thereby reduce the area that design realizes.And can support the WCDMA physical layer protocol of various version, comprise high-speed data service user's the demodulation tasks of the multi-code transmission of spreading factor SF=2 or 4.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and exemplary embodiment of the present invention and explanation thereof are used for explaining the present invention, are not construed as limiting the invention; In the accompanying drawings:
Fig. 1 is the chip rotation of the embodiment of the present invention and the structure chart of interlock circuit;
Fig. 2 is the schematic diagram of the cumulative and rotation circuit of the chip of the embodiment of the present invention;
Fig. 3 is the structure chart of the 1st exponent arithmetic(al) unit and latch units in the firstorder circuit of Fig. 2;
Fig. 4 is the structure chart of the 2nd exponent arithmetic(al) unit and latch units in the second-order circuit in Fig. 2;
Fig. 5 is the structure chart of the 3rd exponent arithmetic(al) unit and latch units in the 3rd rank circuit in Fig. 2;
Fig. 6 is the structure chart of the 4th exponent arithmetic(al) unit and latch units in the quadravalence circuit in Fig. 2; And
Fig. 7 is the structure chart of the 5th exponent arithmetic(al) unit and latch units in the 5th rank circuit in Fig. 2.
Embodiment
In order to make technical scheme of the present invention clearer, below in conjunction with the drawings and specific embodiments, the present invention is elaborated further.It should be noted that, in the situation that not conflicting, embodiment and the variety of way in embodiment in the application can combine mutually.
Embodiment mono-
The descrambling and de-spreading device of the data channel of the present embodiment comprises:
Chip rotation and interlock circuit, be used for according to chip offset chip_offset, with S either-or switch, from 2S chip antenna data ant_data0～ant_data (2S-1), choose and participate in relevant S cumulative chip antenna data, then this S chip antenna data and pseudo noise code are done to associative operation, S chip Chip0～Chip (S-1) after output is relevant, wherein, S=2
x, 0 <=chip_offset < S, S, X, chip_offset are positive integer;
Chip adds up and rotation circuit, for according to spreading factor SF, adjacent S F the chip of Chip0～Chip (S-1) being added up, and in cumulative process, chip is rotated, and obtains the relevant accumulation result of S chip of correct sequence, wherein, and SF=2
j, j is positive integer.
Chip rotation and interlock circuit comprise:
Either-or switch circuit, comprise S either-or switch Switch_i, each either-or switch Switch_i according to a gating signal select_i from input two chip antenna data ant_data (i) and ant_data (i+S) selection an output, wherein, i=0,1 ..., (S-1);
Decoding circuit, for generate the gating signal select_i of each either-or switch according to chip offset chip_offset, make when i < chip_offset, either-or switch Switch_i exports ant_data (i+S), during i >=chip_offset, either-or switch Switch_i exports ant_data (i);
Chip interlock circuit, for chip and the pseudo noise code of the output of either-or switch circuit are carried out to associative operation, exports S the chip Chip0～Chip (S-1) after described being correlated with.
Chip adds up and rotation circuit comprises X rank circuit, wherein:
Firstorder circuit comprises 2
(X-1)individual the 1st exponent arithmetic(al) unit step0_M and 2
(X-1)individual latch units, M=0,1 ... (2
(X-1)-1), wherein:
Each the 1st exponent arithmetic(al) unit step0_M comprises a cumulative rotary unit, be used at chip_offset[0]=0 o'clock, the accumulation result of output Chip (2M) and Chip (2M+1), at chip_offset[0]=1 o'clock, the accumulation result of output Chip (2M+1) and Chip (2M+2); This cumulative rotary unit can comprise: either-or switch, be used at gating signal chip_offset[0]=1 o'clock, from two input Chip (2M) and Chip (2M+2), select Chip (2M+2) output, at chip_offset[0]=0 o'clock, Chip (2M) output selected; And adder, for output after the output of the either-or switch of same unit and Chip (2M+1) is cumulative;
Each latch units is exported for after the output step0_symbol (M) of the 1st exponent arithmetic(al) unit step0_M of correspondence is latched to a timeticks;
X rank circuit comprises 2
(X-x)individual x exponent arithmetic(al) unit step (x-1) _ Z and 2
(X-x)individual latch units, x=2,3 ..., (X-1), Z=0,1 ... (2
(X-x)-1), wherein:
Each x exponent arithmetic(al) unit step (x-1) _ Z comprises a cumulative rotary unit, be used at chip_offset[x-1]=0 o'clock, the accumulation result of output step (x-2) _ symbol (2Z) and step (x-2) _ symbol (2Z+1), at chip_offset[x-1]=1 o'clock, the accumulation result of output step (x-2) _ symbol (2Z+1) and step (x-2) _ symbol (2Z+2); This cumulative rotary unit can comprise: either-or switch, be used at gating signal chip_offset[x-1]=1 o'clock, from two input step (x-2) _ symbol (2Z) and step (x-2) _ symbol (2Z+2), select step (x-2) _ symbol (2Z+2) output, at chip_offset[1]=0 o'clock, step (x-2) _ symbol (2Z) output selected; Adder, for output after the output of the either-or switch of same unit and step (x-2) _ symbol (2Z+1) is cumulative.
Each latch units is exported for after output step (x-1) _ symbol (Z) of x exponent arithmetic(al) unit step (the x-1) _ Z of correspondence is latched to a timeticks;
X rank circuit comprises an X exponent arithmetic(al) unit and a latch units, wherein:
This X exponent arithmetic(al) unit step (X-1) _ 0 comprises an adder, for output step (the X-2) _ symbol (0) of two X-1 exponent arithmetic(al) unit and step (X-2) _ symbol (1) is cumulative;
This latch units, for exporting after timeticks of the output latch of this adder, obtains the relevant accumulation result of S chip of correct sequence.
Above-mentioned descrambling and de-spreading device is if support multiple SF, as 2,4 ... 16,32 ... etc., in each exponent arithmetic(al) unit that need to start on the 2nd rank, increase bypass rotary unit and selected cell, specific as follows:
Each x exponent arithmetic(al) unit step (x-1) _ Z also comprises an x rank bypass rotary unit step (x-1) _ Z_BR and x rank selected cell step (x-1) _ Z_SL, x=2, and 3 ..., X, Z=0,1 ... (2
(X-x)-1), wherein:
X rank bypass rotary unit step (x-1) _ Z_BR comprises (x-1) individual bypass gyrator unit step (x-1) _ Z_BR (2
j), bypass gyrator unit step (x-1) _ Z_BR (2
j) for SF=2
jtime bypass and rotation to input chip, j=1,2 ..., (x-1), at Z+1 <=chip_offset[p:q] < Z+2
(X-x)+ 1 o'clock, front 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), rear 2
(X-x)clap output step (x-2) _ symbol (Z), at chip_offset[p:q] < Z+1 or chip_offset[p:q] >=Z+2
(X-x)+ 1 o'clock, front 2
(X-x)clap output step (x-2) _ symbol (Z), rear 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), q=j, p=j+X-x;
X rank selected cell step (x-1) _ Z_SL is connected with (x-1) individual bypass gyrator unit in x exponent arithmetic(al) unit step (x-1) _ Z and the output of cumulative rotary unit, in SF <=2
(x-1)time, output step (the x-1) _ symbol (Z) using the output of bypass gyrator unit step (x-1) _ Z_BR (SF) as this x exponent arithmetic(al) unit step (x-1) Z, at SF > 2
(x-1)time, output step (the x-1) _ symbol (Z) using the output of this cumulative rotary unit as this x exponent arithmetic(al) unit step (x-1) _ Z.
When specific implementation, bypass gyrator unit step described above (x-1) Z_BR (2
j) can comprise:
X rank decoder, for according to chip offset and timeticks output gating signal, makes at Z+1 <=chip_offset[p:q] < Z+2
(X-x)+ 1 o'clock, the either-or switch of same subelement was front 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), rear 2
(X-x)clap output step (x-2) _ symbol (Z), at chip_offset[p:q] < Z+1 or chip_offset[p:q] >=Z+2
(X-x)+ 1 o'clock, the either-or switch of same subelement was front 2
(X-x)clap output step (x-2) _ symbol (Z), rear 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x));
Either-or switch, for according to the gating signal of the x rank decoder output of same subelement, inputs step (x-2) _ symbol (Z) and step (x-2) _ symbol (Z+2 from two
(X-x)output of middle selection.
The above-mentioned descrambling and de-spreading device of the present embodiment can be used for a descrambling and de-spreading in WCDMA system data channel demodulation, supports the various SF of this system regulation, and S is as can be 2,4,8,16,32,64,128 or 256.
Embodiment bis-
The processing of the present embodiment data channel chip-level descrambling and de-spreading is based on embodiment mono-, take 32 chips as the unit operation of being correlated with and adding up.Due to after the chip data of a plurality of finger in same channel regularly have and first have with respect to antenna system, different finger is differentiated with respect to antenna system skew regularly, and we are called chip offset (chip offset) it.For example, the chip offset of a finger equals 7, when carrying out data channel demodulation, be from the chip of the 7th in the time slot of antenna data, and take 32 chips as the unit operation of being correlated with and adding up.Because the chip offset of different finger is different, for 32 chips are processing unit, chip offset is 31 chips to the maximum, be that chip offset scope is 0～31, when processing a plurality of finger of same channel, need to once take out the antenna data of 64 chips, then according to finger chip offset separately, from 64 chips, taking out 32 chips is correlated with and adds up, the chip offset of take equals 7 as example, correct order for 32 relevant and cumulative chip data is: chip7, chip8, chip9, chip10, ..., chip30, chip31, chip32, chip33, chip34, chip35, chip36, chip37, chip38 (taking out successively from small to large 32 from chip corresponding to chip offset).The selection course of this chip, is called the phase rotating of chip.Can find out, the granularity of phase rotating is directly related with the processing granularity of chip-level descrambling and de-spreading, be not quantitatively strict restriction, and the present embodiment just processing granularity based on 32chip is discussed.
After the phase rotating of chip, obtaining is for the relevant data of solid size sheet, carries out relevantly to PN code, and the chip data after relevant add up.For data channel descrambling and de-spreading, because SF is different, the cumulative number of chip is also different, such as SF equals 2, is that 2 adjacent chips are summed into symbol and then export, and it is that 4 adjacent chips are summed into symbol and then export that SF equals 4, by that analogy.Because descrambling and de-spreading is to take 32 chips to be correlated with and to add up as unit, here relevant is also 32 rank, so maximum 32 data accumulations.For SF, be less than 32, be added to SF, SF is more than or equal to 32, is added to 32 chips.Because be that despreading for the first time after descrambling is processed here, so be greater than 32 for SF, need just can obtain symbol after follow-up despreading for the second time, what obtain here is just added to 32 data; For SF, be less than or equal to 32, be added to SF, obtain is-symbol.
The descrambling and de-spreading device of the present embodiment data channel comprises following circuit:
Chip rotation and interlock circuit, for choosing from the 64 chip antenna datas that take out, participate in relevant 32 cumulative chip antenna datas, phase rotating namely, and will through postrotational antenna data and pseudo noise code for example PN code do associative operation, output 32 chips;
Chip adds up and rotation circuit, for according to SF, the correlated results of 32 chips is cumulative, in cumulative process, chip is rotated, and obtains the relevant accumulation result of 32 chips of correct sequence.
Wherein:
Chip rotation and interlock circuit as shown in Figure 1, in figure, ant_data_0, ant_data_1 ..., ant_data63 represents 64 chips in antenna data; Mix_pn represents to mix PN code, for the associative operation of chip; Select_0, select_1 ..., select_31 represents the gating signal of either-or switch; In literary composition, X[i, j] represent the i～j position of getting binary signal X, X[i] represent the i position of getting binary signal X, as the chip_offset[4:0 in figure] represent to get the 4th to the 0th of chip_offset signal, mix_pn[1:0] represent to get the 1st to the 0th of mix_pn signal.
As shown in the figure, this chip rotation and interlock circuit comprise:
Either-or switch circuit, comprise 32 either-or switch Switch_i, each either-or switch Switch_i is according to gating signal select_i output of selection from the antenna data ant_data (i) of two chips of input and ant_data (i+32).
Decoding circuit (Coding), for generate the gating signal select_i of each either-or switch according to chip offset chip_offset, make when i < chip_offset, either-or switch Switch_i exports chip ant_data (i+32), when i >=chip_offset, either-or switch Switch_i exports chip ant_data (i).
Chip interlock circuit, comprises 32 sub-interlock circuits (Chip_correlate), for the chip of 32 either-or switch outputs and the corresponding positions of PN code are carried out to associative operation, and 32 chip Chip0～Chip (31) after output is relevant.Here need PN code also according to chip_offset, to be rotated, 32 continuous values are rotated to be to the phase place identical with antenna chip, because the PN of solid size sheet only has 2bit, so the resource consuming here relatively seldom.
Wherein, i=0,1 ..., 31, chip_offset is chip offset, with 5bit, represents to be chip_offset[4:0].
32 chips that choose by above-mentioned either-or switch circuit are effective chip data, then carry out associative operation output chip0～chip31 with PN code, but are easy to find out from Fig. 1, and the sequence of chip from 0 to 31 is not the correct sequence needing.The chip offset of still take equals 7 as example, and the relevant rear corresponding Chip of ant_data (i) is designated as to Chip ' (i), is: chip ' 7 for the follow-up relevant and cumulative 32 chips correct order that for Chip0～Chip31, Chip ' (i) represents, chip ' 8, and chip ' 9, and chip ' 10, ..., chip ' 30, and chip ' 31, chip ' 32, and chip ' 33, and chip ' 34, chip ' 35, chip ' 36, and chip ' 37, and chip ' 38; And through the present embodiment rotation and relevant after 32 chips that obtain for Chip0～Chip31 Chip ' (i) represent be: chip ' 32, and chip ' 33, and chip ' 34, chip ' 35, and chip ' 36, and chip ' 37, chip ' 38, chip ' 7, and chip ' 8, and chip ' 9, chip ' 10, ..., chip ' 30, and chip ' 31.; in the situation of chip offset >=1, the chip that the chip offset of take is corresponding is separation, before be the chip that numbering is greater than 31 one group correct sequence; after be the chip that numbering is less than 31 one group correct sequence, but there is on the whole dislocation.Therefore follow-up, while adding up according to SF, also need these 32 chips to be further rotated, to obtain correct sequence.Here rotation is that the design of this rotation and interlock circuit is in order to reduce too much MUX because the phase rotating of rotation and interlock circuit has been upset the order of effective chip, reduces the area that design realizes.
The chip that Fig. 2 has described the present embodiment on the whole adds up and rotation circuit, and this circuit will be selected cumulative progression according to SF on the one hand, and adjacent several chip adds up; To chip0～chip31 be rotated to be to correct chip order according to chip offset on the other hand, add up and bypass output.As shown in the figure, the present embodiment adopts five rank circuit to realize the chip cumulative sum rotation to different SF, and the output of front single order is as the input of rear single order.Because SF minimum is 2, thus firstorder circuit only need adjacent between two chip be added according to chip offset, all the other 4 rank cumulative need to according to SF judgement be continue cumulative or by adder bypass.Acc_step0_0～Acc_step0_15 in figure represents to form 16 single order electronic circuits of firstorder circuit, and Acc_step1_0～Acc_step1_7 represents to form 8 second order electronic circuits of second-order circuit, similar according to this, and Acc_step4 represents the 5th rank circuit.Dislocation for chip rotation causes before adjusting, allows different timeticks cycle_cnt can export correct symbol, need to control rotation according to chip_offset and cycle_cnt.
It should be noted that, the granularity of phase rotating is directly related with the processing granularity of chip-level descrambling and de-spreading, in number of chips, be not strict restriction, the present embodiment is that the processing granularity based on 32 chips is discussed, therefore adopt five rank cumulative sum rotation circuits to carry out cumulative sum rotation, because only do a despreading, maximum need to be added to 32 chips (being that S equals 32), when SF is greater than 32 chip, in secondary despreading, according to SF, continue cumulative; If one time despreading maximum demand is added to 64 chips, need six rank cumulative sum rotation circuits, if a despreading is only added to 16 chips, only need quadravalence cumulative sum rotation circuit, the granularity of a despreading can freely be selected as required, is generally less than and equals 64 chips.
Firstorder circuit comprises 16 the 1st exponent arithmetic(al) unit step0_M and 16 latch units, 0 <=M < 16.Fig. 3 shows a 1st rank electronic circuit Acc_step0_M of a latch units formation of a 1st exponent arithmetic(al) unit step0_M and correspondence, as shown in the figure,
Each the 1st exponent arithmetic(al) unit step0_M comprises a cumulative rotary unit, and this cumulative rotary unit comprises:
Either-or switch, at gating signal chip_offset[0]=1 o'clock, from two input Chip (2M) and Chip (2M+2), select Chip (2M+2) output, at chip_offset[0]=0 o'clock, selection Chip (2M) exports.
Adder, for chip data and the cumulative rear output of Chip (2M+1) that either-or switch is exported.
Each latch units is exported for after the output step0_symbol (M) of the 1st exponent arithmetic(al) unit step0M of correspondence is latched to a timeticks, can realize with d type flip flop.
Second-order circuit comprises 8 the 2nd exponent arithmetic(al) unit step1_N and 8 latch units, 0 <=N < 8.Fig. 4 shows a 2nd rank electronic circuit Acc_step1_N of a latch units formation of a 2nd exponent arithmetic(al) unit step1_N and correspondence, the 2nd exponent arithmetic(al) unit step1_N comprises cumulative rotary unit, a bypass rotary unit step1_N_BR and a selected cell, this cumulative rotary unit is realized the cumulative of adjacent 4 chips, if SF=2, do not need chip cumulative, only need to carry out phase rotating according to chip_offset, export 16 symbols.16 symbols are wanted 16 bat outputs, thus cycle_cnt value 0～15, cycle_cnt[3] be front 8 flip symbols of 0 output, cycle_cnt[3] be 8 flip symbols after 1 output.
As shown in Figure 4, wherein:
This cumulative rotary unit comprises:
Either-or switch, be used at gating signal chip_offset[1]=1 o'clock, from two input step0_symbol (2N) and step0_symbol (2N+2), select step0_symbol (2N+2) output, at chip_offset[1]=0 o'clock, step0_symbol (2N) output selected.
Adder, for output after the output of same unit either-or switch and step0_symbol (2N+1) is cumulative.
This bypass rotary unit step1_N_BR comprises a gyrator unit step1_N_BR (2), and this gyrator unit step1_N_BR (2) comprises again:
The 2nd rank decoder (Step1 Coding), for exporting gating signal according to chip offset and timeticks, make <=chip_offset[4:1 at N+1] during < N+9, the either-or switch of same subelement is clapped output step0_symbol (N+8) front 8, and rear 8 clap output step0_symbol (N); At chip_offset[4:1] < N+1 or chip_offset[4:1] during >=N+9, the either-or switch of same subelement is clapped output step0_symbol (N) front 8, and rear 8 clap output step0_symbol (N+8).
Either-or switch for according to gating signal, is selected an output from two input step0_symbol (N) and step0_symbol (N+8).
This selected cell is used for according to spreading factor SF, when SF=2, output step1_symbol (N) using the output of bypass rotary unit as the 2nd exponent arithmetic(al) unit step1_N, when SF > 2, the output step1_symbol (N) using the output of this cumulative rotary unit as the 2nd exponent arithmetic(al) unit step1_N.This selected cell can be realized with either-or switch, 1 either-or switch representing with SF > 2 as gating signal in figure.(gating signal be SF > 2, SF > 4, SF > 8, SF > 16 while all representing that this condition is set up the value of gating signal be 1).
Each latch units is exported for after the output step1_symbol (N) of the 2nd exponent arithmetic(al) unit step1_N of correspondence is latched to a timeticks, 0 <=N < 8.
The 3rd rank circuit comprises 4 the 3rd exponent arithmetic(al) unit step2_P and 4 latch units, 0 <=P < 4, Fig. 5 shows a 3rd rank electronic circuit Acc_step2_P of a latch units formation of a 3rd exponent arithmetic(al) unit and correspondence, the 3rd exponent arithmetic(al) unit step2_P comprises a cumulative rotary unit, one bypass rotary unit step2_P_BR and a selected cell, wherein cumulative rotary unit is realized the cumulative of adjacent 8 chips, if SF=2 or 4, do not need chip cumulative, only need to carry out phase rotating according to chip_offset, export 16 or 8 symbols.As SF=2, need on the basis of second-order rotation, each 8 symbols of 2 groups of front and back be continued to rotation in group; As SF=4, after phase rotating, export 8 symbols.And 8 symbols are wanted 8 bat outputs, thus cycle_cnt value 0～7, cycle_cnt[2] be front 4 flip symbols of 0 output, cycle_cnt[2] be 4 flip symbols after 1 output.
As shown in Figure 5, wherein:
This cumulative rotary unit comprises:
Either-or switch, be used at gating signal chip_offset[2]=1 o'clock, from two input step1_symbol (2P) and step1_symbol (2P+2), select step1_symbol (2P+2) output, at chip_offset[2]=0 o'clock, step1_symbol (2P) output selected.
Adder, for output after the output of same unit either-or switch and step1_symbol (2P+1) is cumulative.
This bypass rotary unit comprises that step2_P_BR comprises a bypass gyrator unit step2_P_BR (2) and a bypass gyrator unit step2_P_BR (4), wherein:
Bypass gyrator unit step2_P_BR (2) comprises again:
The 3rd rank decoder (Step2 Coding 1), for exporting gating signal according to chip offset and timeticks, make <=chip_offset[3:1 at P+1] during < P+5, the either-or switch of same subelement is clapped output step1_symbol (P+4) front 4, and rear 4 clap output step1_symbol (P); At chip_offset[3:1] < P+1 or chip_offset[3:1] during >=P+5, the either-or switch of same subelement is clapped output step1_symbol (P) front 4, and rear 4 clap output step1_symbol (P+4).
Either-or switch for according to gating signal, is selected an output from two input step1_symbol (P) and step1_symbol (P+4).
The structure of bypass gyrator unit step2_P_BR (4) is identical with bypass gyrator unit step2_P_BR (2), the chip_offset[3:1 using in the time of just need to be by step2_P_BR (2) decoding] replace with chip_offset[4:2], repeat no more here.
This selected cell is used for according to spreading factor SF, in SF <=4 o'clock, output step2_symbol (P) using the output of bypass gyrator unit step2_P_BR (SF) as the 3rd exponent arithmetic(al) unit step2_P, when SF > 4, the output step2_symbol (P) using the output of cumulative rotary unit as the 3rd exponent arithmetic(al) unit step2_P.This selected cell can be realized with two either-or switch, 2 either-or switch that represent with SF > 4 and SF > 2 as gating signal in figure.
Each latch units is exported for after the output step2_symbol (P) of the 3rd exponent arithmetic(al) unit step2_P of correspondence is latched to a timeticks, 0 <=P < 4.
Quadravalence circuit comprises 2 the 4th exponent arithmetic(al) unit step3_Q and 2 latch units, 0 <=Q < 2.Fig. 6 shows a 4th rank electronic circuit Acc_step3_Q of a latch units formation of a 4th exponent arithmetic(al) unit step3_Q and correspondence.The 4th exponent arithmetic(al) unit step3_Q comprises cumulative rotary unit, a bypass rotary unit step3_Q_BR and a selected cell, wherein cumulative rotary unit is realized the cumulative of adjacent 16 chips, if SF=2 or 4 or 8, do not need chip cumulative, only need to carry out phase rotating according to chip_offset, export 16 or 8 or 4 symbols.During SF=2, need on the basis of the 3rd rank rotation, each 4 symbols of 4 groups of front and back be continued to rotation in group; During SF=4, need on the basis of the 3rd rank rotation, each 4 symbols of 2 groups of front and back be continued to rotation in group; During SF=8, after phase rotating, export 4 symbols.4 symbols are wanted 4 bat outputs, thus cycle_cnt value 0～3, cycle_cnt[1] be front 2 flip symbols of 0 output, cycle_cnt[1] be 2 flip symbols after 1 output.
As shown in Figure 6, wherein:
This cumulative rotary unit comprises:
Either-or switch, be used at gating signal chip_offset[3]=1 o'clock, from two input step2_symbol (2Q) and step2_symbol (2Q+2), select step2_symbol (2Q+2) output, at chip_offset[3]=0 o'clock, step2_symbol (2Q) output selected.
Adder, for output after the output of same unit either-or switch and step2_symbol (2Q+1) is cumulative.
This bypass rotary unit comprises a bypass gyrator unit step3_Q_BR (2), a bypass gyrator unit step3_Q_BR (4) and a bypass gyrator unit step3_Q_BR (8), wherein:
Bypass gyrator unit step3_Q_BR (2) comprises again:
The 4th rank decoder (Step3 Coding 2), for exporting gating signal according to chip offset and timeticks, make <=chip_offset[2:1 at Q+1] during < Q+3, the either-or switch of same subelement is clapped output step2_symbol (Q+2) front 2, and rear 2 clap output step2_symbol (Q); At chip_offset[2:1] < Q+1 or chip_offset[2:1] during >=Q+3, the either-or switch of same subelement is clapped output step2_symbol (Q) front 2, and rear 2 clap output step2_symbol (Q+2).
Either-or switch for according to gating signal, is selected an output from two input step2_symbol (Q) and step2_symbol (Q+2).
The structure of bypass gyrator unit step3_Q_BR (4) is identical with bypass gyrator unit step3_Q_BR (2), the chip_offset[2:1 using in the time of just need to be by step3_Q_BR (2) decoding] replace with chip_offset[3:2], repeat no more here.
The structure of bypass gyrator unit step3_Q_BR (8) is identical with bypass gyrator unit step3_Q_BR (2), the chip_offset[2:1 using in the time of just need to be by step3_Q_BR (2) decoding] replace with chip_offset[4:3], repeat no more here.
This selected cell is used for according to spreading factor SF, in SF <=8 o'clock, output step3_symbol (Q) using the output of bypass gyrator unit step3_Q_BR (SF) as the 4th exponent arithmetic(al) unit step3_Q, when SF > 8, the output step3_symbol (Q) using the output of cumulative rotary unit as the 4th exponent arithmetic(al) unit step3_Q.This selected cell can be realized with 3 either-or switch, 3 either-or switch that represent as SF > 8, SF > 4 and SF > 2 for gating signal in figure.
Each latch units is exported for after the output step3_symbol (Q) of the 4th exponent arithmetic(al) unit step3_Q of correspondence is latched to a timeticks, 0 <=Q < 2.
The 5th rank circuit Acc_step4 comprises 1 the 5th exponent arithmetic(al) unit step4_0 and 1 latch units, as shown in Figure 7, the 5th exponent arithmetic(al) unit step4_0 comprises an adder, a bypass rotary unit and a selected cell, wherein adder realizes the cumulative of adjacent 32 chips, if SF=2,4,8 or 16, do not need chip cumulative, only need to carry out phase rotating according to chip_offset, export 16,8,4 or 2 symbols.And during SF=2, need on the basis of quadravalence rotation, each 2 symbols of 8 groups of front and back be continued to rotate in group; During SF=4, need on the basis of quadravalence rotation, each 2 symbols of 4 groups of front and back be continued to rotation in group; During SF=8, need on the basis of quadravalence rotation, each 2 symbols of 2 groups of front and back be continued to rotation in group; During SF=16, after phase rotating, export 2 symbols.2 symbols are wanted 2 bat outputs, thus cycle_cnt value 0～1, cycle_cnt[0] be front 1 flip symbol of 0 output, cycle_cnt[0] be 1 flip symbol after 1 output.
As shown in Figure 7, wherein:
This adder is for inputting step3_symbol (0) and the cumulative rear output of step3_symbol (1) by two.
This bypass rotary unit comprises a bypass gyrator unit step4_0_BR (2), a bypass gyrator unit step4_0_BR (4), a bypass gyrator unit step4_0_BR (8) and a bypass gyrator unit step4_0_BR (16), wherein:
Bypass gyrator unit step4_0_BR (2) comprises again:
The 5th rank decoder, for exporting gating signal according to chip offset and timeticks, make at chip_offset[1]=1 o'clock, the either-or switch of same subelement is clapped output step3_symbol (1) front 1, and rear 1 claps output step3_symbol (0); At chip_offset[1]=0 o'clock, the either-or switch of same subelement is clapped output step3_symbol (0) front 1, and rear 1 claps output step3_symbol (1).
Either-or switch for according to gating signal, is selected an output from two input step3_symbol (0) and step3_symbol (1).
The structure of bypass gyrator unit step4_0_BR (4) is identical with bypass gyrator unit step4_0_BR (2), the chip_offset[1 using in the time of just need to be by step4_0_BR (2) decoding] replace with chip_offset[2], repeat no more here.
The structure of bypass gyrator unit step4_0_BR (8) is identical with bypass gyrator unit step4_0_BR (2), the chip_offset[1 using in the time of just need to be by step4_0_BR (2) decoding] replace with chip_offset[3], repeat no more here.
The structure of bypass gyrator unit step4_0_BR (16) is identical with bypass gyrator unit step4_0_BR (2), the chip_offset[1 using in the time of just need to be by step4_0_BR (2) decoding] replace with chip_offset[4], repeat no more here.
This selected cell is used for according to spreading factor SF, in SF <=16 o'clock, and the output step4_symbol using the output of bypass gyrator unit step4_0_BR (SF) as the 5th exponent arithmetic(al) unit step4_0; When SF > 16, the output step4_symbol using the output of cumulative rotary unit as the 5th exponent arithmetic(al) unit step4_0.This selected cell can be realized with 4 either-or switch, 4 either-or switch that represent as SF > 16, SF > 8, SF > 4 and SF > 2 for gating signal in figure.
This latch units is exported for after the output step4_symbol of the 5th exponent arithmetic(al) unit step4_0 is latched to a timeticks.
The output step4_symbol of the 5th rank circuit is exactly the output of a descrambling and de-spreading, and this result is in cumulative process, to have adjusted the correct output that chip phase obtains.
With chip_offset=7, chip_offset=00111 is example, supposes SF=32, and now five rank circuit are all the cumulative results of output rotation.
At firstorder circuit, because chip_offset[0] be 1, each cumulative rotary unit is cumulative by chip (2M+1) and chip (2M+2), and output can be expressed as:
Chip1+Chip2，
Chip3+Chip4，
...，
Chip31+Chip0。
At second-order circuit, because chip_offset[1] be 1, each cumulative rotary unit is cumulative by step0_symbol (2N+1) and step0_symbol (2N+2), and output can be expressed as:
Chip3+Chip4+Chip5+Chip6，
Chip7+Chip8+Chip9+Chip10，
...，
Chip31+Chip0+Chip1+Chip2。
At the 3rd rank circuit, because chip_offset[2] be 1 o'clock, step1_symbol (2P+1) and step1_symbol (2P+2) is cumulative, and output can be expressed as:
Chip7+Chip8+Chip9+Chip10+Chip11+Chip12+Chip13+Chip14，
Chip15+Chip16+Chip17+Chip18+Chip19+Chip20+Chip21+Chip22，
Chip23+Chip24+Chip25+Chip26+Chip27+Chip28+Chip29+Chip30，
Chip31+Chip0+Chip1+Chip2+Chip3+Chip4+Chip5+Chip6。
Output is now Chip7 by chip order, chip8 ..., Chip31, Chip0, Chip1, ..., Chip6, (i) represents to be with Chip ': Chip ' 7, chip ' 8 ..., Chip ' 31, Chip ' 32, and Chip ' 33 ..., Chip ' 38, due correct order while having reverted to chip_offset=7 as seen.
In quadravalence circuit and the 5th rank circuit, because chip_offset[3]=chip_offset[4]=0, can to said sequence, not adjust again, therefore the symbol of last output has correct chip order.
Chip_offset=7 again, chip_offset=00111 is example, supposes SF=2, the cumulative result of firstorder circuit output rotation in five rank circuit now, the result that bypass rotation all should be exported in other rank, no longer adds up.
At firstorder circuit, as previously mentioned, the output of each the 1st exponent arithmetic(al) cell S tep0_M (0 <=M < 16) can be expressed as:
Chip1+Chip2，
Chip3+Chip4，
...，
Chip31+Chip0。
Two of every a line output Step0_symbol (M) that chip accumulation result is exactly the 1st exponent arithmetic(al) cell S tep0_M above;
At second-order circuit, final output is the output of bypass gyrator unit step1_N_BR (2), because chip_offset[4:1] be 3, according to the rotation logic of this bypass gyrator unit, in N=0～2 o'clock, that the 2nd exponent arithmetic(al) unit step1_N front 8 claps output is step0_symbol (N+8), that rear 8 bats are exported is step0_symbol (N), and in N=3～7 o'clock, that the 2nd exponent arithmetic(al) unit step1_N front 8 claps output is step0_symbol (N), and that rear 8 bats are exported is step0_symbol (N+8).
Thus, the output of each the 2nd exponent arithmetic(al) cell S tep1_N (0 <=N < 8) can be expressed as:
Chip17+Chip18，Chip1+Chip2，
Chip19+Chip20，Chip3+Chip4，
Chip21+Chip22，Chip5+Chip6，
Chip7+Chip8，Chip23+Chip24，
Chip9+Chip10，Chip25+Chip26，
Chip11+Chip12，Chip27+Chip28，
Chip13+Chip14，Chip29+Chip30，
Chip15+Chip16，Chip31+Chip0，
Before every a line comma, being the output Step1_symbol (N) that the 2nd exponent arithmetic(al) cell S tep1_N the front the 8th claps, is 8 output Step1_symbol (N) that clap thereafter after comma.
At the 3rd rank circuit, final output is the output of bypass gyrator unit step2_P_BR (2), because chip_offset[3:1] be 3, according to the rotation logic of this bypass gyrator unit, in P=0～2 o'clock, that the 3rd exponent arithmetic(al) unit step2_P front 4 claps output is step1_symbol (P+4), that rear 4 bats are exported is step1_symbol (P), when P=3, that the 3rd exponent arithmetic(al) cell S tep2_P front 4 claps output is step1_symbol (P), and that rear 4 bats are exported is step1_symbol (P+4).
Thus, the output of each the 3rd exponent arithmetic(al) cell S tep2_P (0 <=P < 4) can be expressed as:
Chip9+Chip10，Chip17+Chip18，Chip25+Chip26，Chip1+Chip2，
Chip11+Chip12，Chip19+Chip20，Chip27+Chip28，Chip3+Chip4，
Chip13+Chip14，Chip21+Chip22，Chip29+Chip30，Chip5+Chip6，
Chip7+Chip8，Chip15+Chip16，Chip23+Chip24，Chip31+Chip0，
Each row is respectively the output Step2_symbol (P) during 16 of the 3rd rank computing unit Step2_P claps, and the symbol that every 2 chips form takies 4 beats.
At quadravalence circuit, final output is the output of bypass gyrator unit step3_Q_BR (2), because chip_offset[2:1] be 3, according to the rotation logic of this bypass gyrator unit, during Q=0, the 4th exponent arithmetic(al) cell S tep3_0 claps output step2_symbol (Q) front 2, rear 2 clap output step2_symbol (Q+2), during Q=1, the 4th exponent arithmetic(al) cell S tep3_1 claps output step2_symbol (Q+2) front 2, and rear 2 clap output step2_symbol (Q).
Thus, the output of each the 4th exponent arithmetic(al) cell S tep3_Q (0 <=Q < 2) can be expressed as:
Chip9+Chip10，Chip13+Chip14，Chip17+Chip18，Chip21+Chip22，Chip25+Chip26，Chip29+Chip30，Chip1+Chip2，Chip5+Chip6；
Chip7+Chip8，Chip11+Chip12，Chip15+Chip16，Chip19+Chip20，Chip23+Chip24，Chip27+Chip28，Chip31+Chip0，Chip3+Chip4，
The first group code is the output Step3_symbol (0) during 16 of the 4th rank computing unit Step3_0 claps, and the second group code is the output Step3_symbol (1) during 16 of the 4th rank computing unit Step3_1 claps.
At the 5th rank circuit, final output is the output of bypass gyrator unit step4_0_BR (2), because chip_offset[1] be 1, according to the rotation logic of this bypass gyrator unit, output step3_symbo1 (1) is clapped front 1 in the 5th exponent arithmetic(al) unit, and rear 1 claps output step3_symbol (0).
Thus, the output of the 5th exponent arithmetic(al) cell S tep4_0 can be expressed as:
Chip7+Chip8，Chip9+Chip10，Chip11+Chip12，......，Chip31+Chip0，Chip1+Chip2，Chip3+Chip4，Chip5+Chip6。
Visible, due correct order while reverting to chip_offset=7.
Pass through such scheme, in can optimal design WCDMA data channel demodulation system chip rotation with add up scheme, reduce the resource consumption of WCDMA data channel demodulation system, improve the disposal ability of WCDMA data channel demodulation system, meet the system upgrade demand that the continuous evolution of agreement brings.
The above embodiment is only preferred embodiment of the present invention, is not intended to limit protection scope of the present invention, and those skilled in the art can deliberately carry out various modifications and variations to the present invention and without departing from the spirit and scope of the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these modifications and modification interior.
Claims (8)
1. a descrambling and de-spreading device for data channel, is characterized in that, this device comprises:
Chip rotation and interlock circuit, be used for according to chip offset chip_offset, with S either-or switch, from 2S chip antenna data ant_data0ant_data (2S-1), choose and participate in relevant S cumulative chip antenna data, then this S chip antenna data and pseudo noise code are done to associative operation, S chip Chip0～Chip (S-1) after output is relevant, wherein, S=2
x, 0 <=chip_offset < S, S, X, chip_offset are positive integer;
Chip adds up and rotation circuit, for according to spreading factor SF, adjacent S F the chip of Chip0～Chip (S-1) being added up, and in cumulative process, chip is rotated, and obtains the relevant accumulation result of S chip of correct sequence, wherein, and SF=2
j, j is positive integer.
2. descrambling and de-spreading device according to claim 1, is characterized in that:
Described chip rotation and interlock circuit comprise:
Either-or switch circuit, comprise S either-or switch Switch_i, each either-or switch Switch_i according to a gating signal select_i from input two chip antenna data ant_data (i) and ant_data (i+S) selection an output, wherein, i=0,1..., (S-1);
Decoding circuit, for generate the gating signal select_i of each either-or switch according to chip offset chip_offset, make when i < chip_offset, either-or switch Switch_i exports ant_data (i+S), during i >=chip_offset, either-or switch Switch_i exports ant_data (i);
Chip interlock circuit, for chip and the pseudo noise code of the output of either-or switch circuit are carried out to associative operation, exports S the chip Chip0～Chip (S-1) after described being correlated with.
3. descrambling and de-spreading device according to claim 1 and 2, is characterized in that: described chip adds up and rotation circuit comprises X rank circuit, wherein:
Firstorder circuit comprises 2
(X-1)individual the 1st exponent arithmetic(al) unit step0_M and 2
(X-1)individual latch units, M=0,1 ... (2
(X-1)-1), wherein:
Each the 1st exponent arithmetic(al) unit step0_M comprises a cumulative rotary unit, be used at chip_offset[0]=0 o'clock, the accumulation result of output Chip (2M) and Chip (2M+1), at chip_offset[0]=1 o'clock, the accumulation result of output Chip (2M+1) and Chip (2M+2);
Each latch units is exported for after the output step0_symbol (M) of the 1st exponent arithmetic(al) unit step0_M of correspondence is latched to a timeticks;
X rank circuit comprises 2
(X-x)individual x exponent arithmetic(al) unit step (x-1) _ Z and 2
(X-x)individual latch units, x=2,3 ..., (X-1), Z=0,1 ... (2
(X-x)-1), wherein:
Each x exponent arithmetic(al) unit step (x-1) _ Z comprises a cumulative rotary unit, be used at chip_offset[x-1]=0 o'clock, the accumulation result of output step (x-2) _ symbol (2Z) and step (x-2) _ symbol (2Z+1), at chip_offset[x-1]=1 o'clock, the accumulation result of output step (x-2) _ symbol (2Z+1) and step (x-2) _ symbol (2Z+2);
Each latch units is exported for after output step (x-1) _ symbol (Z) of x exponent arithmetic(al) unit step (the x-1) _ Z of correspondence is latched to a timeticks;
X rank circuit comprises an X exponent arithmetic(al) unit and a latch units, wherein:
This X exponent arithmetic(al) unit step (X-1) _ 0 comprises an adder, for by output step (the X-2) _ symbol (0) of two X-1 exponent arithmetic(al) unit and step (X-2) _ symbol (1);
This latch units, for exporting after timeticks of the output latch of this adder, obtains the relevant accumulation result of S chip of correct sequence.
4. descrambling and de-spreading device according to claim 3, is characterized in that:
Cumulative rotary unit in described the 1st exponent arithmetic(al) unit step0_M comprises:
Either-or switch, at gating signal chip_offset[0]=1 o'clock, from two input Chip (2M) and Chip (2M+2), select Chip (2M+2) output, at chip_offset[0]=0 o'clock, selection Chip (2M) exports;
Adder, for output after the output of the either-or switch of same unit and Chip (2M+1) is cumulative;
Cumulative rotary unit in described x exponent arithmetic(al) unit step (x-1) _ Z comprises:
Either-or switch, be used at gating signal chip_offset[x-1]=1 o'clock, from two input step (x-2) _ symbol (2Z) and step (x-2) _ symbol (2Z+2), select step (x-2) _ symbol (2Z+2) output, at chip_offset[1]=0 o'clock, step (x-2) _ symbol (2Z) output selected;
Adder, for output after the output of the either-or switch of same unit and step (x-2) _ symbol (2Z+1) is cumulative.
5. descrambling and de-spreading device according to claim 3, is characterized in that:
Each x exponent arithmetic(al) unit step (x-1) _ Z also comprises an x rank bypass rotary unit step (x-1) _ Z_BR and x rank selected cell step (x-1) _ Z_SL, x=2, and 3 ..., X, Z=0,1 ... (2
(X-x)-1), wherein:
X rank bypass rotary unit step (x-1) _ Z_BR comprises (x-1) individual bypass gyrator unit step (x-1) _ Z_BR (2
j), bypass gyrator unit step (x-1) _ Z_BR (2
j) for SF=2
jtime bypass and rotation to input chip, j=1,2 ..., (x-1), at Z+1 <=chip_offset[p:q] < Z+2
(X-x)+ 1 o'clock, front 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), rear 2
(X-x)clap output step (x-2) _ symbol (Z), at chip_offset[p:q] < Z+1 or chip_offset[p:q] >=Z+2
(X-x)+ 1 o'clock, front 2
(X-x)clap output step (x-2) _ symbol (Z), rear 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), q=j, p=j+X-x;
X rank selected cell step (x-1) _ Z_SL is connected with (x-1) individual bypass gyrator unit in x exponent arithmetic(al) unit step (x-1) _ Z and the output of cumulative rotary unit, in SF <=2
(x-1)time, output step (the x-1) _ symbol (Z) using the output of bypass gyrator unit step (x-1) _ Z_BR (SF) as this x exponent arithmetic(al) unit step (x-1) _ Z, at SF > 2
(x-1)time, output step (the x-1) _ symbol (Z) using the output of this cumulative rotary unit as this x exponent arithmetic(al) unit step (x-1) _ Z.
6. descrambling and de-spreading device according to claim 5, is characterized in that:
Described bypass gyrator unit step (x-1) _ Z_BR (2
j) comprising:
X rank decoder, for according to chip offset and timeticks output gating signal, makes at Z+1 <=chip_offset[p:q] < Z+2
(X-x)+ 1 o'clock, the either-or switch of same subelement was front 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x)), rear 2
(X-x)clap output step (x-2) _ symbol (Z), at chip_offset[p:q] < Z+1 or chip_offset[p:q] >=Z+2
(X-x)+ 1 o'clock, the either-or switch of same subelement was front 2
(X-x)clap output step (x-2) _ symbol (Z), rear 2
(X-x)clap output step (x-2) _ symbol (Z+2
(X-x));
Either-or switch, for according to the gating signal of the x rank decoder output of same subelement, inputs step (x-2) _ symbol (Z) and step (x-2) _ symbol (Z+2 from two
(X-x)) output of middle selection.
7. according to the descrambling and de-spreading device described in claim 1 or 2 or 4 or 5 or 6, it is characterized in that:
Described S=2,4,8,16,32,64,128 or 256.
8. according to the descrambling and de-spreading device described in claim 5 or 6, it is characterized in that:
This descrambling and de-spreading device, for a descrambling and de-spreading of WCDMA system data channel demodulation, is supported the various SF of this system regulation, and wherein SF minimum is 2.
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| CN201310116377.9A CN104104410B (en) | 2013-04-03 | 2013-04-03 | A kind of descrambling and de-spreading device of data channel |
| PCT/CN2013/081763 WO2013189360A2 (en) | 2013-04-03 | 2013-08-19 | Descrambling and despreading device of data channel |
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| CN101064581A (en) * | 2006-04-27 | 2007-10-31 | 凯明信息科技股份有限公司 | Descrambling and despreading method and apparatus |
| EP1983656A1 (en) * | 2007-04-19 | 2008-10-22 | MediaTek Inc. | Shared filter design for pilot symbol averaging in rake fingers in WCDMA systems |
| CN102684740A (en) * | 2011-03-07 | 2012-09-19 | 清华大学 | High-speed low-complexity PAKE receiver and implementation method of high-speed low-complexity PAKE receiver |
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| CN101136652B (en) * | 2006-12-11 | 2010-05-19 | 中兴通讯股份有限公司 | WCDMA code chip processing equipment |
| WO2009074291A1 (en) * | 2007-12-10 | 2009-06-18 | Nxp B.V. | Improvements in or relating to receive diversity systems |
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| CN101064581A (en) * | 2006-04-27 | 2007-10-31 | 凯明信息科技股份有限公司 | Descrambling and despreading method and apparatus |
| EP1983656A1 (en) * | 2007-04-19 | 2008-10-22 | MediaTek Inc. | Shared filter design for pilot symbol averaging in rake fingers in WCDMA systems |
| CN102684740A (en) * | 2011-03-07 | 2012-09-19 | 清华大学 | High-speed low-complexity PAKE receiver and implementation method of high-speed low-complexity PAKE receiver |
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