CN104103540B - Graphics chip grid electrode oxide layer surface monitoring method - Google Patents
Graphics chip grid electrode oxide layer surface monitoring method Download PDFInfo
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- CN104103540B CN104103540B CN201410356924.5A CN201410356924A CN104103540B CN 104103540 B CN104103540 B CN 104103540B CN 201410356924 A CN201410356924 A CN 201410356924A CN 104103540 B CN104103540 B CN 104103540B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- Microelectronics & Electronic Packaging (AREA)
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a graphics chip grid electrode oxide layer surface monitoring method. The graphics chip grid electrode oxide layer surface monitoring method comprises providing a semiconductor substrate which is provided with a grid electrode oxide layer; detecting the surface information of a plurality of grid points on the grid electrode oxide layer to obtain the distribution, the average value and the standard deviation of the surface information; according to the average value and the standard deviation of the surface information, determining whether the growth technology of the grid electrode oxide layer is stable. The surface information is work functions and/or surface potentials. The graphics chip grid electrode oxide layer surface monitoring method detects the work functions and the surface potentials of the surface of the grid electrode oxide layer through an electrical detecting method; the detected surface information can be used for daily monitoring of the grid electrode oxide layer as well as for rapidly screening out graphics chips with excellent-quality grid electrode oxide layers, so that the deficiency of traditional detecting methods can be made up.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of side of monitoring pattern chip gate oxidation layer surface
Method.
Background technology
With developing rapidly of super large-scale integration (VLSI) and ULSI (ULSI), MOS device
Size be steadily decreasing.For increasing the reaction speed of device, improving the capacity of driving current and storage capacitance, grid in device
The thickness of oxide layer constantly reduces.Integrated circuit is hindered to develop further however, two problems of the thing followed become
Key factor:Puncture and leak electricity.
While device size scaled down, operating voltage does not but have correspondingly Scaling, so that thin grid
Electric-field intensity in oxide layer increases, and the breakdown voltage of device reduces;On the other hand, existing defects, surface in grid oxic horizon
Uneven grade, it may appear that internal field concentrates, easily produces internal discharge and forms many conductive channels, equally reduces breakdown potential
Pressure.And the generation of leakage current is often relevant with the charged impurity in grid oxic horizon.There is positive charge in grid oxic horizon
In the case of, when thickness of grid oxide layer is uneven, internal field in thinner region very strong so that the most advanced and sophisticated thickness of potential barrier
Thinning, tunnel current (electronics flows to semiconductor from polysilicon or metal gates) can be produced in negative gate voltage, thus shape
Become leakage current.
Because the requirement to grid oxic horizon quality improves, the mode of traditional monitoring grid oxic horizon can not meet
Super large-scale integration and the demand of ULSI.For example, a kind of mode of traditional monitoring grid oxic horizon
It is to measure the no surface charge of graphical wafer and diffusion length (Diffusion Length);Or using optical method detection
The surface defect of graphical wafer (Pattern Wafer).Due to the limitation of traditional detection method, the surface microscopic of pattern piece
Matter cannot monitored it is impossible to monitor the quality comparison of grid oxic horizon completely, therefore it provides a kind of monitoring pattern chip grid oxygen
The method changing layer surface is those skilled in the art's technical problem urgently to be resolved hurrily.
Content of the invention
It is an object of the invention to, a kind of method of monitoring pattern chip gate oxidation layer surface is provided, solves existing skill
The limitation of detection method in art.
In order to achieve the above object, the present invention provides a kind of method of monitoring pattern chip gate oxidation layer surface, and it is special
Levy and be, including:
Semi-conductive substrate is provided, described Semiconductor substrate is formed with a grid oxic horizon, described semiconductor substrate
Include N trap, p-well, input/output trap and fleet plough groove isolation structure, described grid oxic horizon include a first grid oxide layer and
One second grid oxide layer, described first grid oxide layer covers described input/output trap, and described second grid oxide layer covers
Described N trap and described p-well;
Detect the surface information of multiple lattice points on described grid oxic horizon, obtain distribution, the mean value of described surface information
And standard deviation;And
Mean value according to described surface information and standard deviation, judge whether the growth technique of described grid oxic horizon is steady
Fixed.
Further, detect the surface information of multiple lattice points on described grid oxic horizon, obtain dividing of described surface information
The concrete steps of cloth, mean value and standard deviation include:
Select multiple lattice points in described gate oxidation layer surface;
Measure the described surface information of each lattice point;
Obtain the distribution of the described surface information of described grid oxic horizon;
Distribution according to described surface information obtains mean value and the standard deviation of described surface information.
Further, judge whether stable the concretely comprising the following steps of growth technique of described grid oxic horizon:
Preset the first term of reference, the second term of reference;
The mean value judging described surface information, whether in the range of described first term of reference, judges described table simultaneously
Whether the standard deviation of surface information is in the range of described second term of reference;
The mean value of described surface information is in the range of described first term of reference, and the standard of described surface information
Deviation, in the range of described second term of reference, judges that described grid oxic horizon growth technique is stable, otherwise, described grid oxygen
Change layer growth technique unstable.
Further, described first term of reference, the second term of reference set according to described Gate Oxide Integrity.
Further, described surface information includes work function and/or surface potential.
Further, the thickness of described first grid oxide layer isThe thickness of described second grid oxide layer
Spend and be
Compared with prior art, the method for the monitoring pattern chip gate oxidation layer surface that the present invention provides has and has as follows
Beneficial effect:
The method of the monitoring pattern chip gate oxidation layer surface that the present invention provides, including:Semi-conductive substrate, institute are provided
State and a grid oxic horizon is formed with Semiconductor substrate;Detect the surface information of multiple lattice points on described grid oxic horizon, obtain
The distribution of described surface information, mean value and standard deviation;And the mean value according to described surface information and standard deviation, sentence
Whether the growth technique of disconnected described grid oxic horizon is stable.Described surface information is work function and/or surface potential.The present invention supervises
The method of control graphical wafer gate oxidation layer surface, using the method for electrical detection, detects the work function of gate oxidation layer surface
And surface potential, the surface information of detection both can be used for the daily monitoring of grid oxic horizon it is also possible to for express delivery screening tool
The graphical wafer of the grid oxic horizon of standby superior quality, compensate for the deficiency of traditional detection method.
Brief description
Fig. 1 is the flow chart of the method for monitoring pattern chip gate oxidation layer surface in one embodiment of the invention;
Fig. 2 is the method schematic diagram that in one embodiment of the invention, monitoring pattern chip second grid aoxidizes layer surface;
Fig. 3 is to judge the whether stable flow chart of second grid oxide layer growth technique in one embodiment of the invention.
Specific embodiment
Method below in conjunction with the monitoring pattern chip gate oxidation layer surface to the present invention for the schematic diagram is carried out in more detail
Description, which show the preferred embodiments of the present invention it should be appreciated that those skilled in the art can change described here
The present invention, and still realize the advantageous effects of the present invention.Therefore, description below is appreciated that for those skilled in the art
Widely known, and be not intended as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
It is necessary to make a large amount of implementation details to realize the specific objective of developer in sending out, such as according to relevant system or relevant business
Limit, another embodiment is changed into by an embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Seek book, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is all in the form of very simplification and all using non-
Accurately ratio, only in order to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
The core concept of the present invention is, the method for the monitoring pattern chip gate oxidation layer surface providing, including:There is provided
Semi-conductive substrate, described Semiconductor substrate is formed with a grid oxic horizon;Detect multiple lattice points on described grid oxic horizon
Surface information, obtain distribution, mean value and the standard deviation of described surface information;And it is average according to described surface information
Value and standard deviation, judge whether the growth technique of described grid oxic horizon is stable.Described surface information is work function and/or table
Face potential.The method of monitoring pattern chip gate oxidation layer surface of the present invention, using the method for electrical detection, detects gate oxidation
The work function of layer surface and surface potential, the surface information of detection both can be used for grid oxic horizon daily monitoring it is also possible to
Possess the graphical wafer of the grid oxic horizon of superior quality for express delivery screening, compensate for the deficiency of traditional detection method.
Specifically, in conjunction with above-mentioned core concept, the method for the monitoring pattern chip gate oxidation layer surface that the present invention provides,
Particular flow sheet refer to Fig. 1, its comprise the steps for:
Execution step S1, provides semi-conductive substrate, and described Semiconductor substrate is formed with a grid oxic horizon.
In described step S1, with reference to shown in Fig. 2, described Semiconductor substrate 40 includes N trap 41, p-well 42, input/output
Trap 43, fleet plough groove isolation structure 44, described grid oxic horizon includes a first grid oxide layer 31 and a second grid oxide layer
32, described first grid oxide layer 31 covers described input/output trap 43, and described second grid oxide layer covers described N trap 41
With described p-well 42.The thickness of described first grid oxide layer 31 isDescribed second grid aoxidizes 32 layers of thickness
Spend and be
In the present embodiment, to detect described second grid oxide layer 32 growth technique illustrates as a example whether stable,
Thickness with described second grid oxide layer 32 isAs a example illustrate.Detect the side of described first grid oxide layer 31
Method is essentially identical with the method detecting described second grid oxide layer 32, will not be described here..
Execution step S2, detects the surface information of multiple lattice points in described second grid oxide layer, obtains described surface letter
The distribution of breath, mean value and standard deviation.
In described step S2, the concrete steps obtaining distribution, mean value and the standard deviation of described surface information include:
With reference to shown in Fig. 2, select multiple lattice points on described second grid oxide layer 32 surface;Measure the described surface information of each lattice point
20;Obtain the distribution of the described surface information 20 of described second grid oxide layer 32;Distribution according to described surface information obtains
The mean value of described surface information 20 and standard deviation.
The present invention, in implementation process, is located on a certain lattice point on described second grid oxide layer 32 surface with a probe 1
Side, an additional bias between described probe 1 and described second grid oxide layer 32, described probe 1 can be obtained by described lattice point
Surface information 20, preferably, described surface information 20 includes work function (Work Function) 21 and/or surface potential
(Surface Potentials)22.Described work function 21 represents at lattice site described in described second grid oxide layer 32
Electronics spills into the energy required for the surface of described second grid oxide layer 32 from the inside of described second grid oxide layer 32,
Described surface potential 22 represents between current potential and described probe 1 at lattice site described in described second grid oxide layer 32
Potential difference.In the present embodiment, illustrated with described surface information 20 for described surface potential 22.
Described probe 1 chooses multiple lattice points in described second grid oxide layer 32, obtains the described surface of multiple lattice points
Letter 20, that is, obtain the distribution of the described surface information 20 of described second grid oxide layer 32.Take the distribution of described surface letter 20
Mean value and standard deviation, that is, obtain the mean value of surface information and the standard deviation of described second grid oxide layer 32.
The method that embodiments of the invention use electrical detection, detects work function 21 and the surface on described second grid oxide layer 32 surface
Potential 22, can obtain the surface information 20 of the microcosmic of described second grid oxide layer 32, have higher resolution ratio.
For example, in the present embodiment, detect 4 lattice points, the described surface potential 22 detecting be -1.0V, -1.2V, -
1.1V, -0.8V, the value of above-mentioned surface potential 22 is not limited to above range, herein only because illustrating.
Execution step S3, the mean value according to described surface information and standard deviation, judge described second grid oxide layer
Growth technique whether stable.
In described step S3, judge whether stable the concretely comprising the following steps of growth technique of described grid oxic horizon:Reference
Shown in Fig. 3, in the present embodiment, described step S3 includes sub-step S310, S321, S322, S331 and S332:
Carry out step S310:Preset the first term of reference, the second term of reference, described first reference in the present invention
Scope, the second term of reference are to set according to the Gate Oxide Integrity in semiconductor fabrication process.In the present embodiment,
Described first term of referenceDescribed second term of referenceOn
State the first term of reference and the value of the second term of reference is not limited to above range, herein only because illustrating.
Carry out step S321:By the mean value of the described surface information 20 obtaining in step S2 and described first term of reference
It is compared, whether the mean value judging described surface information 20 is in the range of described first term of reference.When described surface
The mean value of information 20 not in the range of described first term of reference, then carries out step S322, i.e. described second grid oxidation
The growth technique of layer 32 is unstable;The mean value of described surface information 20 in the range of described first term of reference, is then carried out
Step S322.For example, in the present embodiment, the mean value of described surface potential 22 is -1.0, in described first term of reference,
Then carry out step S322.
Carry out step S322:By 20 standard deviations of the described surface information obtaining in step S2 with described second with reference to model
Enclose and be compared, whether the standard deviation judging described surface information 20 is in the range of described second term of reference.When described
The standard deviation of surface information 20 not in the range of described second term of reference, then carries out step S322, i.e. described second gate
The growth technique of pole oxide layer 32 is unstable;When described surface information 20 standard deviation described second term of reference scope
Interior, then carry out step S321, that is, the growth technique of described second grid oxide layer 32 is stable.For example, in the present embodiment,
The standard deviation of described surface potential 22 is 0.17, in the range of described second term of reference, then carries out step S321, i.e. institute
The growth technique stating second grid oxide layer 32 is stable.
In the present embodiment, in step s3, the order of described sub-step S321 and described sub-step S322 is adjusted
Change and can also realize the present invention.
If the growth technique of described first grid oxide layer 31 and described second grid oxide layer 32 is all stable, described
Grid oxic horizon 30 growth technique is stable, and otherwise, the growth technique of described grid oxic horizon 30 is unstable.
In the present embodiment, described surface information 20 is described surface potential 22, but in other embodiments of the invention
In, described surface information 20 can also be work function 21, or, described surface information 20 can also include work function 21 and described
22 two kinds of information of surface potential, according to the foregoing description of the present invention, this be it will be appreciated by those skilled in the art that, here is not
Repeat.
In sum, the method for the monitoring pattern chip gate oxidation layer surface that the present invention provides, including:Half is provided to lead
Body substrate, described Semiconductor substrate is formed with a grid oxic horizon;Detect the surface of multiple lattice points on described grid oxic horizon
Information, obtains distribution, mean value and the standard deviation of described surface information;And the mean value according to described surface information and mark
Quasi- deviation, judges whether the growth technique of described grid oxic horizon is stable.Described surface information is work function and/or surface electricity
Gesture.The method of monitoring pattern chip gate oxidation layer surface of the present invention, using the method for electrical detection, detects grid oxic horizon table
The work function in face and surface potential, the surface information of detection both can be used for the daily monitoring of grid oxic horizon it is also possible to be used for
Express delivery screening possesses the graphical wafer of the grid oxic horizon of superior quality, compensate for the deficiency of traditional detection method.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (5)
1. a kind of method of monitoring pattern chip gate oxidation layer surface is it is characterised in that include:
Semi-conductive substrate is provided, described Semiconductor substrate is formed with a grid oxic horizon, described Semiconductor substrate includes N
Trap, p-well, input/output trap and fleet plough groove isolation structure, described grid oxic horizon includes a first grid oxide layer and one
Two grid oxic horizons, described first grid oxide layer covers described input/output trap, and described second grid oxide layer covers described
N trap and described p-well;
Detect the surface information of multiple lattice points on described grid oxic horizon, obtain distribution, mean value and the mark of described surface information
Quasi- deviation;And
Mean value according to described surface information and standard deviation, judge whether the growth technique of described grid oxic horizon is stable,
Judge whether stable the concretely comprising the following steps of growth technique of described grid oxic horizon:
Preset the first term of reference, the second term of reference;
The mean value judging described surface information, whether in the range of described first term of reference, judges described surface letter simultaneously
Whether the standard deviation of breath is in the range of described second term of reference;
The mean value of described surface information is in the range of described first term of reference, and the standard deviation of described surface information
In the range of described second term of reference, judge that described grid oxic horizon growth technique is stable, otherwise, described grid oxic horizon
Growth technique is unstable.
2. the method for monitoring pattern chip gate oxidation layer surface as claimed in claim 1 is it is characterised in that detect described grid
The surface information of multiple lattice points in the oxide layer of pole, obtains the concrete step of distribution, mean value and the standard deviation of described surface information
Rapid inclusion:
Select multiple lattice points in described gate oxidation layer surface;
Measure the described surface information of each lattice point;
Obtain the distribution of the described surface information of described grid oxic horizon;
Distribution according to described surface information obtains mean value and the standard deviation of described surface information.
3. the method for monitoring pattern chip gate oxidation layer surface as claimed in claim 1 is it is characterised in that described first joins
Examine scope, the second term of reference sets according to described Gate Oxide Integrity.
4. the method for monitoring pattern chip gate oxidation layer surface as claimed in claim 1 is it is characterised in that described surface is believed
Breath includes work function and/or surface potential.
5. the method for monitoring pattern chip gate oxidation layer surface as claimed in claim 1 is it is characterised in that the described first grid
The thickness of pole oxide layer isThe thickness of described second grid oxide layer is
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101069092A (en) * | 2005-03-11 | 2007-11-07 | Q概念技术公司 | Inspection system and apparatus |
CN101728293A (en) * | 2009-11-10 | 2010-06-09 | 上海宏力半导体制造有限公司 | Method for gate oxide integrity (GOI) test of MOS transistor devices |
CN101769848A (en) * | 2008-12-30 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting etching fluid filter |
CN101834114A (en) * | 2009-03-11 | 2010-09-15 | 台湾积体电路制造股份有限公司 | Advanced process control method for gate profile and system for fabricating integrated circuit |
CN103824771A (en) * | 2012-11-16 | 2014-05-28 | 中芯国际集成电路制造(上海)有限公司 | Formation method for gate oxide |
-
2014
- 2014-07-24 CN CN201410356924.5A patent/CN104103540B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101069092A (en) * | 2005-03-11 | 2007-11-07 | Q概念技术公司 | Inspection system and apparatus |
CN101769848A (en) * | 2008-12-30 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting etching fluid filter |
CN101834114A (en) * | 2009-03-11 | 2010-09-15 | 台湾积体电路制造股份有限公司 | Advanced process control method for gate profile and system for fabricating integrated circuit |
CN101728293A (en) * | 2009-11-10 | 2010-06-09 | 上海宏力半导体制造有限公司 | Method for gate oxide integrity (GOI) test of MOS transistor devices |
CN103824771A (en) * | 2012-11-16 | 2014-05-28 | 中芯国际集成电路制造(上海)有限公司 | Formation method for gate oxide |
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