CN104103309A - Operation Method Of Nand Array And Computer Readable Non-transient Storage Media - Google Patents
Operation Method Of Nand Array And Computer Readable Non-transient Storage Media Download PDFInfo
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Abstract
The present invention discloses an operation method of an NAND array and a computer readable non-transient storage media, which are technologies supporting a nonvolatile memory and reducing the programming interference. A three-dimensional or two-dimensional NAND array comprises a plurality of pagings divided into a plurality of paging sets. A storage unit is allowed to be stored in a first paging set of the plurality of paging sets in an erasing area of the three-dimensional NAND array, but the storage of the storage unit which is stored in a second paging set of the plurality of paging sets in the erasing area of the three-dimensional or two-dimensional NAND array is minimum. The pagings in the same paging set are not adjacent to each other in the three-dimensional or two-dimensional NAND array.
Description
Technical field
The invention relates to the storage arrangement and the system that comprise memory management, the nonvolatile Storage Media of especially a kind of method of operating of NAND array and embodied on computer readable.
Background technology
Flash memory is a kind of of non-volatile integrated circuit memory technology.Traditional flash memory adopts suspension joint gate memory cell.Along with the density of storage arrangement increase and suspension joint gate memory cell between become more and more tightr, the interference being stored between the electric charge of contiguous suspension joint grid becomes a problem.This has limited the ability of the flash memory increase density based on suspension joint gate memory cell.The storage unit that is used for the another kind of pattern of flash memory can be called as a charge capturing storage unit, and it catches layer by a dielectric charge and replaces suspension joint grid.
Typical flash memory cell is comprised of a field-effect transistor FET structure, it has source electrode and the drain electrode being separated by a passage, and a grid that channel spacing one charge storage is constructed therewith, charge storage structure comprises that a tunnel dielectric layer, electric charge storage layer (suspension joint grid or dielectric material) and stop dielectric layer.According to the known charge capturing memory design that is called as in early days SONOS device, source electrode, drain electrode and passage are that to be formed at one can be in the silicon body (S) of strip, tunnel dielectric layer is comprised of monox (O), electric charge storage layer is comprised of silicon nitride (N), stop that dielectric layer is comprised of monox (O), and grid comprises polysilicon (S).
Although other frameworks are known, flash memory device normally comprises that by use the NAND of AND framework or NOR framework realize.NAND framework, because of its high density and high speed, enjoys great popularity it when being applied to data storing application.NOR framework is to be suitable for other application, and for example coding stores, and random bytes access is wherein important.In a kind of NAND framework, programming process generally relies on Fu Le-Nuo Dehan tunnelling (Fowler-Nordheim (FN) tunneling), and needs for example high voltage of about 20 volts, and needs high voltage transistor to control them.Extra high voltage transistor on integrated circuit combines with the transistor for logic and other data stream, can cause the complicacy of technique.And the complicacy of this increase instead can increase the cost of device.
The nand memory element of cubical array be take have larger memory span as feature in a relatively little volume.But when a selected memory cell of programming NAND array, near storage unit is still subject to programming and disturbs.Being subject to the storage unit that programming disturbs comprises: the storage unit in same NAND string, by identical word line institute's access and the storage unit in the semiconductor bar of same tier (but different layers), by identical word line institute's access and the storage unit in the semiconductor bar of identical layer (but at contiguous lamination); And by identical word line institute access but the storage unit in the semiconductor bar of contiguous lamination (and different layers).
A kind of method that reduces programming interference is that hot carrier injects (memory technology of an applicable low voltage program operation), and hot carrier injects configurable at a NAND framework.Hot carrier in one NAND framework injects and previously at following application case number, explained: U. S. application case number 12/797,994, and the applying date is on June 10th, 2010, it is to be disclosed as U.S. Patent Application Publication No. 2011/0305088 on Dec 15th, 2011; And U. S. application case number 12/898,979, the applying date is on October 6th, 2010, and it is to be disclosed as U.S. Patent Application Publication No. 2012/0081962 on April 5th, 2012, and it is all incorporated to for referencial use herein.
No matter why hot carrier injects, and the problem that remains in high-density storage is disturbed in programming.Our expectation further improves programming and disturbs.
Summary of the invention
A kind of technology of supporting the minimizing programming interference of nonvolatile memory.
It is a kind of method of operating that comprises three-dimensional/two-dimentional NAND array of a plurality of pagings (page) that one of this technology is implemented sample state, and a plurality of pagings are divided into a plurality of paging groups.The method comprises:
Allow to be accessed in the storage unit within one first paging group of a plurality of paging groups in an erase blocks of three-dimensional/two-dimentional NAND array, but it is minimized to make to be accessed in the access of the storage unit within one second paging group of a plurality of paging groups in the erase blocks of three dimensional NAND array.
Paging in wherein paging group is not adjacent to each other on entity in three-dimensional/two-dimentional NAND array.
In an embodiment, the first paging group and the second paging group have the relative to each other checkerboard pattern of skew.By this, can not carry out programming operation for paging contiguous on entity.
Allow access and make the minimized example of access for programming and read operation.In an embodiment, the storage unit within the first paging group in the erase blocks of three dimensional NAND array allows programming operation, and the programming operation of the storage unit within the second paging group in the erase blocks of this array is minimized.In another embodiment, in the storage unit within the first paging group in the erase blocks of three dimensional NAND array, allow read operation, and the read operation of the storage unit within the second paging group in the erase blocks of this array is minimized.
By with a logical erase but not an entity wipes to respond an erase command of a paging, and in after collective wipe this kind of paging, the various embodiment of this technology have reduced the sum for the performed erase operation of erase blocks.By mode according to this, reduce the sum of erase operation, life-span that can extension fixture.In the embodiment of this technology, for the first paging group erasing instruction used, it is the paging that causes having a disarmed state, this disarmed state be the delay of indication (i) paging wipe and (ii) paging for reading and cannot the using of write store operation, until at least delay of paging is wiped.In the another kind of embodiment of this technology, when when first and second paging group, both have received erasing instruction, the erase blocks that comprises these two paging groups is to be wiped free of, and is to be removed for the disarmed state of all a plurality of paging groups.After removing disarmed state, read and programming operation is no longer stoped in real time for this reason at least.
In certain embodiments, paging is included in the storage unit of being close on the entity of the many strings in three-dimensional/two-dimentional NAND array.
Three/two following embodiment have changed the physical direction of the storage unit of the paging between three/two different spaces axles.
In an embodiment, on the entities of many strings, contiguous storage unit is to be configured to make a paging in a plurality of pagings to be included in a plurality of storage unit in a same memory cell layer of this array, by same word line institute access, and by not corresponding lines institute access, wherein any two pagings of first paging group of a plurality of paging groups are non-conterminous mutually on entity, result from following at least one:
(i) at least one intermediary wordline bits is between two pagings,
(ii) at least one intermediary's memory cell layers position is between two pagings, and
(iii) two pagings are positioned in different memory cell layers and by different word line institute accesses.
In another embodiment, on the entities of many strings, contiguous storage unit is to be configured to make a paging in a plurality of pagings to be included in a plurality of storage unit in the different layers of this array by same word line institute access,
Wherein any two pagings of first paging group of a plurality of paging groups are non-conterminous mutually on entity, result from following at least one:
(i) at least one intermediary wordline bits is between two pagings,
(ii) at least one intermediary's memory string lamination position is between two pagings, and
(iii) two pagings are shared no memory string and by the access of different word line institute.
In embodiment further, on the entities of many strings, contiguous storage unit is to be configured to make a paging in a plurality of pagings to be included in a plurality of storage unit in an identical layer of this array by the access of different word line institute.
Wherein any two pagings of first paging group of a plurality of paging groups are non-conterminous mutually on entity, result from following at least one:
(i) at least one intermediary's memory cell layers position is between two pagings,
(ii) at least one intermediary's memory string lamination position is between two pagings, and
(iii) two pagings are positioned in different memory cell layers and are positioned in different memory string laminations.
Another technology of implementing sample state is a calculation element, and it comprises a processor, a three-dimensional/two-dimentional NAND array and control circuit.This storer comprises a plurality of pagings, and it is divided into a plurality of paging groups.Be coupled to processor therewith at least one control circuit of array allow to be accessed in a plurality of storage unit within one first paging group of a plurality of paging groups in an erase blocks of three-dimensional/two-dimentional NAND array, but it is minimized to make to be accessed in the access of a plurality of storage unit within one second paging group of a plurality of paging groups in the erase blocks of three-dimensional/two-dimentional NAND array.Virtual erase blocks in a plurality of virtual erase blocks is videoed into one of them of a plurality of paging groups.A plurality of paging groups in these paging groups comprise from a plurality of pagings of non-conterminous these pagings mutually on entity in three-dimensional/two-dimentional NAND array.Paging in paging group is not adjacent to each other on entity in three-dimensional/two-dimentional NAND array.
The technology of further implementing sample state is the nonvolatile Storage Media of an embodied on computer readable, and it is implemented for a plurality of instructions that comprise a three-dimensional/two-dimentional NAND array of a plurality of pagings.Three-dimensional/two-dimentional NAND array is divided into a plurality of paging groups.Instruction completes when being performed:
Allow to be accessed in a plurality of storage unit within one first paging group of a plurality of paging groups in an erase blocks of three-dimensional/two-dimentional NAND array, but the access that makes to be accessed in a plurality of storage unit within one second paging group of a plurality of paging groups in the erase blocks of three-dimensional/two-dimentional NAND array is minimized
Paging in wherein paging group is not adjacent to each other on entity in three-dimensional/two-dimentional NAND array.Graphic, the detailed description that other implement that sample states and advantage can enclose in inspection of the present invention and claim scope and recognize.
Accompanying drawing explanation
Fig. 1 is the calcspar of an example of storage management system.
Fig. 2 shows an erase blocks of a plurality of pagings, and it is mapped to an erase blocks that is divided into a plurality of paging groups.
Fig. 3 is presented at the configuration of the storage page in the 3 D memory array with a word line parallel.
Fig. 4 is presented at the configuration of the storage page in a 3 D memory array of the multilayer that extends through NAND string.
Fig. 5 is presented at the configuration of the storage page in the 3 D memory array moving along a NAND string.
Fig. 6 shows idle NAND erase blocks, so that all sub-block of erase blocks are all idle.
Fig. 7-Fig. 8 shows the NAND erase blocks of half free time, so that at least one sub-block becomes is invalid, and remaining sub-block is idle.
Fig. 9-Figure 12 shows NAND erase blocks in use, so that at least one of sub-block is in use, and other sub-block are idle and/or invalid.
Figure 13-Figure 16 shows NAND erase blocks in use, so that at least one of sub-block is in use, and other sub-block are idle and/or invalid; But unlike Fig. 9-Figure 12, a different sub-block is in use.
Figure 17 shows the life cycle of the simplification of an erase blocks.
Figure 18 shows the life cycle of the simplification of an erase blocks; Unlike Figure 17, the different order of the sub-block in use is as follows.
Figure 19 is the calcspar of an example of computer system.
[symbol description]
100: system
110: application program
120: disk file system
125: flash translation layer
130: original file system
140: memory technology device archives
150: storer/high power capacity 3D NAND flash array
210: erase blocks
212,612,712,812,912: sub-block 1
214,614,714,814,914: sub-block 2
300,400,500: 3 D memory array/NAND array
610:NAND erase blocks
710:NAND erase blocks
810:NAND erase blocks
910:NAND erase blocks
1010:NAND erase blocks
1012,1112,1212,1312,1412,1512,1612,1712,1722,1732,1742: sub-block 1
1014,1114,1214,1314,1414,1514,1614,1714,1724,1734,1744: sub-block 2
1110,1210,1310,1410,1510,1610,1710:NAND erase blocks
1720,1740,1840: the erase blocks in use
1730,1830: half idle erase blocks
1750: distribute sub-block 1
1760: the virtual sub-block 1 of wiping
1770: distribute sub-block 2
1780: entity is wiped sub-block 1 and 2
1810: idle erase blocks
1820: erase blocks
1850: distribute sub-block 2
1860: the virtual sub-block 2 of wiping
1870: distribute sub-block 1
1880: entity is wiped sub-block 1 and 2
1910: computer system
1912: bus subsystem
1914: processor subsystem
1916: network interface subsystem
1918: communication network/computer network
1920: user interface output unit
1922: user interface input equipment
1924: storage subsystem
1926: memory sub-system
1928: archives storage subsystem
1930: main random access memory (RAM)
1931: flash memory
1932: ROM (read-only memory) (ROM)
Embodiment
The detailed description of embodiment is provided with reference to accompanying drawing.
Fig. 1 is the functional layer calcspar of the data handling system 100 of a combined memory (for example 3D NAND flash array 150 of high power capacity).Storer is various nand flash memory, NOR flash memory or any suitable storage arrangement with erase blocks also.In this memory entities, can be divided into a plurality of sections, so that the minimum dimension unit of the block erase operation that each entity section is storer to be supported.One erase blocks of storer can correspond to one or more entity sections.For example, the capacity of each entity section of storer can be 16KB.In some example, one erase blocks of storer 150 can comprise an entity section, and has and entity section, or the capacity of the identical 16KB of a plurality of entity section, for example 4 entity sections have the total volume of 64KB, or 8 entity sections have the total volume of 128KB.
In order to carry out in the storer of paging mode operation, each erase blocks of storer can comprise a plurality of pagings (page), and each paging can be programmed or read by being stored paging programming and the paging read operation that device supports.For example, the nand flash memory device of one 1-Gbit single-layer type storage memory cells (Single-Level-Cell, SLC) framework can comprise 1K erase blocks, and each erase blocks size is 128KB, and each erase blocks can comprise 64 pagings, each paging size is 2KB.Each paging for example can comprise, for the additional storage space of error-correcting code (ECC) or other functions (64 bytes).Each erase blocks can comprise that additional storage space (for example 4KB) records corrupted paging, erasing times or other data.
By providing an address of a paging program command or paging reading order and confirmation paging to storer, flash memory can be planned and a paging of storer can be programmed or read.Again, by the address that a block erase order is provided and confirms this block to storer, flash memory can be planned and make storer each block can and be wiped free of.For example, each specific paging of the 1-Gbit SLC nand flash memory device of an example can utilize the address of 16 to carry out addressing, and 10 highest significant positions in 16 bit address are the address that comprises the block of specific paging.In this 1-Gbit SLC NAND example, by 16 bit address that a paging reading order or paging program command are provided and confirm this paging, to 1-Gbit SLC nand flash memory device, a paging can be programmed or read.In this 1-GbitSLC NAND example, by providing 10 highest significant positions (in 16 bit address forms) of a block erase order and this erase blocks of confirmation to 1-Gbit SLC nand flash memory device, an erase blocks can be wiped free of.
System 100 comprises one or more file system, and its a plurality of requests based on from an application program 110 store, capture and upgrade the data that are stored in storer 150.File system in this embodiment comprises disk file system 120, it is for example file allocation table (File Allocation Table, FAT) file system, the 3rd is extended file system (Third Extended File System, EXT3) or New Technology File System (New Technology File System, NTFS).File system in this embodiment also comprises a kind of original (native) file system 130 designing for flash memory, Journaled flash file system version 2 (Journaling Flash File System Version2 for example, JFFS2), without sequence tile images file system (Unsorted Block Image File System, UBIFS) or again another kind of flash file system (Yet Another Flash File System, YAFFS).File system 120 or 130 is via for example one reading driver (in order to paging read operation), a driven by program device (in order to paging programming operation) and a device driver of wiping driver (for block erase operation) and carry out access memory 150.One software layer, memory technology device archives (Memory Technology Device file) 140 for example, can be provided as file system 120 or 130 and storer 150 between, there is the interface of device driver.Memory technology device archives 140 comprise an erase blocks and sub-block administration module and relevant status data.Erase blocks and sub-block administration module are regarded erase blocks to be divided into a plurality of sub-block as, and before one of execution erase blocks entity is wiped, the ineffectivity (invalidation) of this little block of management in erase blocks.As discussed below, invalid is a software erase or virtual wiping, and it postpones entity wipes, until a plurality of sub-block can be wiped free of on entity together.Memory technology device archives 140 comprise an operational processes machine and free space (free space) manager.The all operations that the interception of operational processes machine is asked by flash translation layer 125, and by the original function being provided by the memory technology device archives 140 of both having deposited is provided, re-establish the operation for the physical blocks under it.When not having enough free spaces when completing the new programming operation from flash translation layer 125, free-space administration management, distribute and allocation of free space again.
Shown system 100 also comprises the flash translation layer (Flash Translation Layer) 125 of the interface of a conduct between disk file system 120 and device driver (or memory technology device archives 140).Flash translation layer 125 can be carried out the address translation between the logical address of disk file system 120 and the physical address of storer 150.
In certain embodiments, flash translation layer 125 and memory technology device archives 140 are to be for example placed in, in a stocking system (a movable memory card) as firmware.This firmware is removable to the modification demand of the file system of high-order more, has used the stocking system with old system compatible, and has enjoyed the improvement in the present invention simultaneously.In other embodiments, memory technology device archives 140 are to be merged in flash translation layer 125 and/or original file system 130.
Fig. 2 shows an erase blocks of a plurality of pagings, and it is mapped to an erase blocks that is divided into a plurality of paging groups.
An erase blocks 210 in three-dimensional/two dimensional memory arrays comprise storage page (paging 0, paging 1, paging 2, paging 3 ..., paging N).The storage page of erase blocks is a plurality of sub-block of logically being videoed into different paging groups.Shown in figure, be the sub-block 1212 with the paging group 1 of non-conterminous paging on entity, and the sub-block 2214 with the paging group 2 of non-conterminous paging on entity.The paging of paging group 1 (such as paging 1, paging 3, paging 4, paging 6 etc.) is not adjacent to each other on entity in 3 D memory array.The paging of paging group 2 (such as paging 0, paging 2, paging 5, paging 7 etc.) is not adjacent to each other on entity in 3 D memory array.Non-conterminous meaning on entity, the paging being configured in 3 D memory array along x axle, y axle and z axle is not directly adjacent to each other along the arbitrary of x axle or y axle or z axle.Non-conterminous on entity not get rid of the paging being configured in 3 D memory array along x axle, y axle and z axle be to approach cornerwise configuration, so that the position of any two pagings in same paging group differs 1 between the two in appointing of x axle, y axle and z axle.Because the paging in same group is relative to each other non-conterminous on entity, thus the programming operation cause in any paging in a paging group for the programming of any other paging in identical paging group, disturb as minimum or nothing.
Although this figure only shows two sub-block, other embodiment can be divided into plural sub-block by an erase blocks, and each sub-block comprises the paging of a paging group, and it is not adjacent to each other on entity in 3 D memory array.
Fig. 3 is presented at the configuration of the storage page in a kind of 3 D memory array 300 with a word line parallel.
Shown in NAND array 300 in, in a paging, on the entities of many strings, contiguous storage unit is to be configured to: make a paging be included in storage unit in a same memory cell layer of this array by same word line and not corresponding lines institute access.Each of different sub-block (example sub-block as shown in Figure 2) is the checkerboard pattern being configured in Fig. 3.
For example, the storage unit in paging 0 is by 0 access of word line, and by different bit line (do not show, extend into and stretch out this figure) institute's access in identical memory cell layers.
Due to following reason at least one, any two pagings of a paging group are non-conterminous mutually on entity:
(i) at least one intermediary (intervening) wordline bits is for example, between two pagings (paging 1 being separated by word line 1 and paging 9),
(ii) at least one intermediary's memory cell layers position is for example, between two pagings (being included paging 1 and paging 3 that the memory cell layers of paging 2 separates), and
(iii) these two pagings are positioned in different memory cell layers and for example, by different word line institute access (paging 1 and pagings 4, wherein 1 of paging is in than the higher memory cell layers of paging 4 next ones, and paging 1 and paging 4 are respectively by word line 0 and 1 access of word line).
Fig. 4 shows the configuration of storage page in 3 D memory array 400, and it extends through the multilayer of NAND string.
Shown in NAND array 400 in, in a paging, on the entities of many strings, contiguous storage unit is to be configured to: make a paging be included in storage unit in the different layers of this array by same word line institute access.Each of different sub-block (example sub-block as shown in Figure 2) is the checkerboard pattern being configured in Fig. 4.
For example, the storage unit in paging 0 is by 0 access of word line in the different layers of this array.
Due to following reason at least one, any two pagings of a paging group are non-conterminous mutually on entity:
(i) at least one intermediary wordline bits is for example, between two pagings (paging 1 being separated by word line 1 and paging 9),
(ii) at least one intermediary's memory string lamination position is for example, between two pagings (being included paging 1 and paging 3 that the memory string lamination of paging 2, paging 6, paging 10, paging M-1 separates), and
(iii) these two pagings not shared storage string and by different word line institute accesses (for example paging 1 and paging 4, wherein 4 of paging 1 and pagings are in the memory string lamination of different vicinities; And paging 1 and paging 4 are respectively by word line 0 and 1 access of word line).The identical memory string lamination with paging 5, paging 9 and paging M-2 is shared in paging 1.The identical memory string lamination with paging 0, paging 8 and paging M-3 is shared in paging 4.
Fig. 5 is presented at the configuration of the storage page in a kind of 3 D memory array 500 moving along a NAND string.
Shown in NAND array 500 in, in a paging, on the entities of many strings, contiguous storage unit is to be configured to: make a paging be included in storage unit in an identical layer of this array by different word line institute accesses.Each of different sub-block (example sub-block as shown in Figure 2) is configured in the checkerboard pattern in Fig. 5.
For example, the storage unit in paging 0 is that position is in an identical layer of this array, by 0 access of word line.
Due at least one of following reason, it is non-conterminous mutually on entity that the appointing of a paging group watched two pagings:
(i) at least one intermediary's memory cell layers position is for example, between two pagings (being included paging 1 and paging 9 that intermediary's memory cell layers of paging 5 separates),
(ii) at least one intermediary's memory string lamination position is for example, between two pagings (being included paging 1 and paging 3 that the memory string lamination of paging 2, paging 6, paging 10 and paging 14 separates), and
(iii) these two pagings, be positioned in different memory cell layers and be positioned in (for example paging 1 and paging 4 in different memory string laminations, wherein 1 of paging is in than the lower memory cell layers of paging 4 next ones, and 4 of paging 1 and pagings are in the memory string lamination of different vicinities).The identical memory string lamination with paging 5, paging 9 and paging 13 is shared in paging 1.The identical memory string lamination with paging 0, paging 8 and paging 12 is shared in paging 4.
Fig. 6 shows the NAND erase blocks 610 of a free time (free), and all sub-block that make erase blocks are all idle.
NAND erase blocks 610 comprises sub-block 1612 and sub-block 2614.Sub-block 1612 has the paging group 1 of non-conterminous paging on entity.Sub-block 2614 has the paging group 2 of non-conterminous paging on entity.NAND erase blocks 610 is idle, because sub-block 1612 has the paging group 1 of only having free page, and sub-block 2614 has the paging group 2 of only having free page.
Fig. 7-Fig. 8 shows the NAND erase blocks of one and half free time (semi-free), and it is invalid making at least one sub-block, and remaining sub-block is idle.
In Fig. 7, NAND erase blocks 710 comprises sub-block 1712 and sub-block 2714.Sub-block 1712 has the paging group 1 of non-conterminous paging on entity.Sub-block 2714 has the paging group 2 of non-conterminous paging on entity.NAND erase blocks 710 was half free time, because at least one sub-block only includes free page, and at least one sub-block only includes invalid page.Sub-block 1712 has the paging group 1 of only having invalid page, and sub-block 2714 has the paging group 2 of only having free page.
In Fig. 8, NAND erase blocks 810 comprises sub-block 1812 and sub-block 2814.Except having the sub-block of invalid page exchanged with the sub-block with free page, Fig. 8 is similar to Fig. 7.
Fig. 9-Figure 12 shows a NAND erase blocks in use, at least one that makes these sub-block is in use (being sub-block 1 in these cases), and other sub-block are idle and/or invalid (being sub-block 2 in these cases).
In Fig. 9, NAND erase blocks 910 comprises sub-block 1912 and sub-block 2914.Sub-block 1912 has the paging group 1 of non-conterminous paging on entity.Sub-block 2914 has the paging group 2 of non-conterminous paging on entity.NAND erase blocks 910 is in use, because at least one sub-block comprises an active page.Sub-block 1912 has the paging group 1 of effective and invalid page, and sub-block 2914 has the paging group 2 of only having free page.
In Figure 10, NAND erase blocks 1010 comprises sub-block 11012 and sub-block 21014.Except the effective and invalid page of each number of sub-block 1 is in use different, Figure 10 is similar to Fig. 9.
Fig. 9 and Figure 10 and Figure 11 and Figure 12 difference are at least: in Fig. 9 and Figure 10, non-sub-block (in the case, being sub-block 2) is in use idle, and is invalid in Figure 11 and Figure 12.
In Figure 11, NAND erase blocks 1110 comprises sub-block 11112 and sub-block 21114.Sub-block 11112 has the paging group 1 of non-conterminous paging on entity.Sub-block 21114 has the paging group 2 of non-conterminous paging on entity.NAND erase blocks 1110 is in use, and this is because at least one sub-block comprises an active page.Sub-block 11112 has effectively and the paging group 1 of free page, and sub-block 21114 has the paging group 2 of only having invalid page.
In Figure 12, NAND erase blocks 1210 comprises sub-block 11212 and sub-block 21214.Figure 12 is similar to Figure 10, and except the position effective and invalid page of sub-block 1 is in use different, and sub-block in use (in the case, sub-block 2) is not idle in Figure 10, and in Figure 12, is invalid.
Figure 13-Figure 16 shows a NAND erase blocks in use, so that at least one of these sub-block is in use (being sub-block 2 in these cases), and other sub-block are idle and/or invalid (being sub-block 1 in these cases).Unlike Fig. 9-Figure 12, a different sub-block is in use.
In Figure 13, NAND erase blocks 1310 comprises sub-block 11312 and sub-block 21314.In Figure 14, NAND erase blocks 1410 comprises sub-block 11412 and sub-block 21414.In Figure 15, NAND erase blocks 1510 comprises sub-block 11512 and sub-block 21514.In figure l6, NAND erase blocks 1610 comprises sub-block 11612 and sub-block 21614.Except sub-block in use and the sub-block in non-use are exchanged, Figure 13-Figure 16 is similar to respectively Fig. 9-Figure 12.
Figure 17 shows the life cycle of the simplification of an erase blocks.
About the summary of Figure 17, life cycle is carried out according to following order: idle erase blocks (sub-block 1 and 2 free time) 1710; Erase blocks in use (sub-block 1 in use, 2 free time of sub-block) 1720; Half idle erase blocks (sub-block 1 is invalid, 2 free time of sub-block) 1730; Erase blocks in use (sub-block 1 is invalid, sub-block 2 in use) 1740; And get back to idle erase blocks (sub-block 1 and 2 free time) 1710.
Figure 17 is discussed below in more detail.
Idle NAND erase blocks 1710 comprises sub-block 11712 and sub-block 21714.Sub-block 11712 has the paging group 1 of non-conterminous paging on entity.Sub-block 21714 has the paging group 2 of non-conterminous paging on entity.NAND erase blocks 1710 is idle, and this is because all sub-block only include free page.Sub-block 11712 has the paging group 1 of only having free page, and sub-block 21714 has the paging group 2 of only having free page.
In 1750, distribute sub-block 1.Idle NAND erase blocks 1710 becomes the NAND erase blocks 1720 in use.
NAND erase blocks 1720 in use comprises sub-block 11722 and sub-block 21724.NAND erase blocks 1720 is in use, and this is because at least one sub-block comprises an active page.Sub-block 11722 has been assigned with and has comprised at least 1 active page.Sub-block 21724 still has the paging group 2 of only having free page.
In 1760, sub-block 1 is wiped free of virtually.Erase blocks 1720 in use becomes the erase blocks 1730 of half free time.Due to virtual, wipe, sub-block 1 has a disarmed state, this disarmed state be the delay of the paging of indication in (i) sub-block 1 wipe and (ii) paging in sub-block 1 for reading and cannot the using of write store operation, until at least the delay of the paging in sub-block 1 is wiped.
Half idle NAND erase blocks 1730 comprises sub-block 11732 and sub-block 21734.NAND erase blocks 1730 was half free time, and this is invalid because of at least one sub-block, and remaining sub-block is idle.Sub-block 11732 has the paging group 1 of only having invalid page, and sub-block 21734 has the paging group 2 of only having free page.
In 1770, distribute sub-block 2.Half idle NAND erase blocks 1730 becomes the NAND erase blocks 1740 in use.
NAND erase blocks 1740 in use comprises sub-block 11742 and sub-block 21744.NAND erase blocks 1740 is in use, and this is because at least one sub-block comprises an active page.Sub-block 11742 is invalid.Sub-block 21744 has been assigned with and has comprised at least 1 active page.
In 1780, on sub-block 1 and 2 entities, be wiped free of, comprise that the delay of always invalid sub-block 1 is wiped.NAND erase blocks 1740 in use returns back to idle NAND erase blocks 1710.
Figure 18 shows the life cycle of the simplification of an erase blocks; Unlike Figure 17, the different order of the sub-block in use is as follows: before sub-block 1 is allocated to and has active page, first sub-block 2 is distributed into and has active page.After sub-block 2 be distributed into there is active page, sub-block 2 be erased into virtually for invalid page and sub-block 1 be to be allocated to there is active page.
About the summary of Figure 18, life cycle is carried out according to following order: idle erase blocks (sub-block 1 and 2 free time) 1810; Distribute sub-block 21850; Erase blocks in use (1 free time of sub-block, sub-block 2 are in use) 1820; The virtual sub-block 21860 of wiping; Half idle erase blocks (1 free time of sub-block, sub-block 2 invalid) 1830; Distribute sub-block 11870; Erase blocks in use (sub-block 1 in use, sub-block 2 invalid) 1840; Entity is wiped sub-block 1 and 21880; And get back to idle erase blocks (sub-block 1 and 2 free time) 1810.
In the cycle shown in Figure 17 and Figure 18, conventionally, two sub-block in same block can't be in use simultaneously.Yet in Figure 17, if use all sub-block 1, in response to the requirement of a distribution new block, sub-block 2 can be selected and distribute as this new block.Similarly, in Figure 18, if use all sub-block 2, be the requirement in response to a distribution new block, sub-block 1 can be selected and distribute as this new block.
Figure 19 is the calcspar of computer system 1910, and it can comprise the erase blocks shown in Fig. 1 and sub-block administration module.
Computer system 1910 generally comprises a processor subsystem 1914, and it is linked up with some peripheral devices via bus subsystem 1912.These peripheral devices can comprise a storage subsystem 1924 (it comprises a memory sub-system 1926 and an archives storage subsystem 1928), user interface input equipment 1922, user interface output unit 1920 and a network interface subsystem 1916.Input and output unit allow user and computer system 1910 to carry out interaction.Network interface subsystem 1916 provides one to be interfaced to external network (comprising that is interfaced to communication network 1918), and is coupled to the corresponding interface arrangement in other computer systems via communication network 1918.Communication network 1918 can comprise computer system and the communication linkage (1ink) of many interconnection.These communication linkages may be wired link, optical link, wireless link, or any other is about the communication mechanism of information, but generally it is the communication network of a kind of IP address corresponding (IP-based).Although in one embodiment, communication network 1918 is the Internet (Internet), and in other embodiments, communication network 1918 can be any suitable computer network.
The entity hardware element of network interface is called as network adapter (Network Interface Cards sometimes, NIC), for example, although they need not exist with the pattern of card:, they can be the forms of integrated circuit (IC) and connector, directly be installed on mainboard, or huge born of the same parents' (macrocell) pattern, be produced on the single IC for both chip of other elements with computer system.
User interface input equipment 1922 can comprise that a keyboard, indicator device (for example a mouse, trace ball, touch pad or plotting sheet), one scan instrument, are incorporated to the input equipment of the Touch Screen of display, audio input device (for example speech recognition system, microphone) and other patterns.Generally speaking, the use of term " input equipment " be intention comprise input information to computer system 1910 or on computer network 1918 the device and method of pattern likely.
User interface output unit 1920 can comprise a display subsystem, a printer, a facsimile recorder or non-visual displays (for example audio output device).Display subsystem can comprise a cathode-ray tube (CRT) (CRT), for example be the board device, a projection arrangement of a liquid crystal display (LCD) or in order to produce some other mechanism of a visible image.Display subsystem also can provide non-visual displays, for example, via audio output device.Generally speaking, the use of term " output unit " be intention comprise by information from computer system 1910 export to user or to another machine or computer system the device and method of pattern likely.
Storage subsystem 1924 stores base program and data form, and it provides the function of some embodiment of the present invention.For example, the various modules of implementing the function of some embodiment of the present invention can be stored in storage subsystem 1924.For example, erase blocks and the sub-block administration module of implementing above-mentioned technology can be stored in storage subsystem 1924.These software modules are normally carried out by processor subsystem 1914.
Memory sub-system 1926 generally comprises some storeies, comprises the main random access memory (RAM) 1930 for save command the program term of execution and data, and stores fixed instruction in ROM (read-only memory) (ROM) 1932 wherein.Memory sub-system 1926 also can comprise a flash memory 1931.Archives storage subsystem 1928 provides lasting storage for program and data file, and can comprise a hard drives, follows floppy drive, a CD ROM CD-ROM drive, a CD-ROM drive or the movable media box (media cartridge) of relevant movable media.Implement database and the module of the function of some embodiment of the present invention, can be arranged at a computer fetch medium (for example one or more CD-ROM) upper, and can be stored by archives storage subsystem 1928.In addition, mainframe memory subsystem 1926 comprises computer instruction, when it is carried out by processor subsystem 1914, is to make computer system operation or carry out described function.As used herein, be discussed as in " main frame " or " computing machine " or program and the software carried out thereon, to carry out on processor subsystem 1914, with computer instruction and the data in response in mainframe memory subsystem 1926 (the Local or Remote storage area that comprises any other this instruction and data).
It is a kind of for allowing the various elements of computer system 1910 and the subsystem mechanism of communication each other as expected that bus subsystem 1912 provides.Although bus subsystem 1912 is to be summarily shown as unified bus, the alternate embodiment of bus subsystem can be used a plurality of buses.
Computer system 1910 itself can be various types, comprises a personal computer, a pocket computer, a workstation, a computer terminal, a network computer, a televisor, a mainframe computer (mainframe), a server zone (server farm) or any other data handling system or user's set.Due to the characteristic of the continuous variation of computing machine and network, the explanation of the computer system 1910 illustrating in Figure 19 is just for the object of preferred embodiment of the present invention is described, and as a specific examples.A lot of other configurations of computer system 1910 may have the element more more or less than the computer system illustrating in Figure 19.
Although the present invention discloses with reference to above-mentioned preferred embodiment and example, we it will be appreciated that these examples are that intention presents a kind of explanation and unrestriced meaning.We consider that haveing the knack of this skill person will expect multiple modification and combination easily, these modifications and combination by drop on spirit of the present invention and the category of the claim scope of enclosing within.
Claims (21)
1. a method of operating for NAND array, this NAND array comprises a plurality of pagings, wherein these pagings of this NAND array are divided into a plurality of paging groups, comprise the following steps:
Permission is done access to a plurality of storage unit in one first paging group of a plurality of paging groups in an erase blocks of this NAND array, but makes the access minimized (minimizing) of a plurality of storage unit within one second paging group of these paging groups in this erase blocks of this NAND array;
Wherein a plurality of pagings in this paging group are not adjacent to each other in this NAND array.
2. method according to claim 1,
Wherein the step of this permission access comprises: allow the programming operation for a plurality of storage unit within this first paging group of these paging groups in this erase blocks of this NAND array, and
Wherein the minimized step of this access comprises: make for the programming operation of a plurality of storage unit within this second paging group of these paging groups in this erase blocks of this NAND array minimized.
3. method according to claim 1,
Wherein the step of this permission access comprises: allow the read operation for a plurality of storage unit within this first paging group of these paging groups in this erase blocks of this NAND array, and
Wherein the minimized step of this access comprises, makes the read operation of a plurality of storage unit within this second paging groups of these paging groups in this erase blocks of this NAND array minimized.
4. method according to claim 1, wherein: the erasing instruction for a paging group is this paging group that causes having a disarmed state, this disarmed state be the delay of indication (i) this paging group wipe and (ii) these pagings of this paging group for reading and cannot the using of write store operation, until at least this delay of this paging is wiped.
5. method according to claim 4, wherein when this first paging group and this second paging group have received this erasing instruction, this erase blocks that comprises this first paging group and this second paging group is to be wiped free of, and is to be removed for this disarmed state of all these paging groups.
6. method according to claim 1, wherein this first paging group and this second paging group have the relative to each other checkerboard pattern of skew.
7. method according to claim 1, wherein the paging in these pagings is included in the storage unit of the vicinities of many strings in this NAND array.
8. method according to claim 7,
Wherein the storage unit of the vicinity of these many strings is to be configured to: make a paging in these pagings be included in a plurality of storage unit in a same memory cell layer of this NAND array, and by same word line institute access, and by different bit line institute accesses,
Wherein any two pagings of this first paging group of these paging groups are non-conterminous mutually, result from
(i) at least one intermediary wordline bits is between these two pagings,
(ii) at least one intermediary's memory cell layers position is between these two pagings, and
(iii) these two pagings be positioned in different memory cell layers and by different word line institute accesses at least one of them.
9. method according to claim 7,
Wherein the storage unit of the vicinity of these many strings is to be configured to: make a paging in these pagings be included in the storage unit of the many strings in the different layers of this NAND array, and by same word line institute access,
Wherein any two pagings of this first paging group of these paging groups are non-conterminous mutually, result from
(i) at least one intermediary wordline bits is between these two pagings,
(ii) at least one intermediary's memory string lamination position is between these two pagings, and
(iii) these two pagings share no memory string and by the access of different word line institute at least one of them.
10. method according to claim 7,
Wherein the storage unit of the vicinity of these many strings is to be configured to: make a paging in these pagings be included in a plurality of storage unit in an identical layer of this NAND array, and by the access of different word line institute,
Wherein any two pagings of this first paging group of these paging groups are non-conterminous mutually, result from
(i) at least one intermediary's memory cell layers position is between these two pagings,
(ii) at least one intermediary's memory string lamination position is between these two pagings, and
(iii) these two pagings are positioned in different memory cell layers and are positioned in different memory string laminations at least one of them.
The nonvolatile of 11. 1 kinds of embodied on computer readable (non-transitory) Storage Media, it is implemented for a plurality of instructions that comprise a NAND array of a plurality of pagings, and wherein this NAND array is divided into a plurality of paging groups, and these instructions are carried out when being performed:
Allow to be accessed in a plurality of storage unit within one first paging group of a plurality of paging groups in an erase blocks of this NAND array, but make the access of a plurality of storage unit within one second paging group of these paging groups in this erase blocks of this NAND array minimized
Wherein a plurality of pagings in this paging group are not adjacent to each other in this NAND array.
The nonvolatile Storage Media of 12. embodied on computer readable according to claim 11,
Wherein the step of this permission access comprises: allow the programming operation for a plurality of storage unit within this first paging group of these paging groups in this erase blocks of this three dimensional NAND array, and
Wherein the minimized step of this access comprises: do not allow the programming operation for a plurality of storage unit within this second paging group of these paging groups in this erase blocks of this three dimensional NAND array.
The nonvolatile Storage Media of 13. embodied on computer readable according to claim 11,
Wherein the step of this permission access comprises: allow the read operation for a plurality of storage unit within this first paging group of these paging groups in this erase blocks of this three dimensional NAND array, and
Wherein the minimized step of this access comprises: do not allow the read operation for a plurality of storage unit within this second paging group of these paging groups in this erase blocks of this three dimensional NAND array.
The nonvolatile Storage Media of 14. embodied on computer readable according to claim 11,
Wherein the erasing instruction for a paging group is this paging group that causes having a disarmed state, this disarmed state be the delay of indication (i) this paging group wipe and (ii) these pagings of this paging group for reading and cannot the using of write store operation, until at least this delay of this paging is wiped.
The nonvolatile Storage Media of 15. embodied on computer readable according to claim 14,
Wherein, when this first paging group and this second paging group have received this erasing instruction, comprise that this erase blocks of this first paging group and this second paging group is wiped free of, and be to be removed for this disarmed state of all these paging groups.
The nonvolatile Storage Media of 16. embodied on computer readable according to claim 11, wherein this first paging group and this second paging group have the relative to each other checkerboard pattern of skew.
The nonvolatile Storage Media of 17. embodied on computer readable according to claim 11, wherein the paging in these pagings is included in the storage unit of the vicinity of many strings in this NAND array.
The nonvolatile Storage Media of 18. embodied on computer readable according to claim 17,
Wherein the storage unit of the vicinity of these many strings is to be configured to: make a paging in these pagings be included in a plurality of storage unit in a same memory cell layer of this NAND array, and by same word line institute access, and by different bit line institute accesses,
Wherein any two pagings of this first paging group of these paging groups are non-conterminous mutually, result from
(i) at least one intermediary wordline bits is between these two pagings,
(ii) at least one intermediary's memory cell layers position is between these two pagings, and
(iii) these two pagings be positioned in different memory cell layers and by different word line institute accesses at least one of them.
The nonvolatile Storage Media of 19. embodied on computer readable according to claim 17,
Wherein the storage unit of the vicinities of many strings is to be configured to: make a paging in these pagings be included in a plurality of storage unit in the different layers of this NAND array, and by same word line institute access,
Wherein any two pagings of this first paging group of these paging groups are non-conterminous mutually, result from
(i) at least one intermediary wordline bits is between these two pagings,
(ii) at least one intermediary's memory string lamination position is between these two pagings, and
(iii) these two pagings share no memory string and by the access of different word line institute at least one of them.
The nonvolatile Storage Media of 20. embodied on computer readable according to claim 17,
Wherein the storage unit of the vicinities of many strings is to be configured to: make a paging in these pagings be included in a plurality of storage unit in an identical layer of this NAND array, and by the access of different word line institute,
Wherein this first paging group of these paging groups appoint that to watch two pagings non-conterminous mutually, result from:
(i) at least one intermediary's memory cell layers position is between these two pagings,
(ii) at least one intermediary's memory string lamination position is between these two pagings, and
(iii) these two pagings are positioned in different memory cell layers and are positioned in different memory string laminations at least one of them.
21. 1 kinds of calculation elements, comprising:
One processor;
One NAND array, comprises a plurality of pagings, and wherein these pagings of this NAND array are divided into a plurality of paging groups; And
Control circuit, be coupled at least one of this processor and this NAND array, this control circuit allows to be accessed in a plurality of storage unit within one first paging group of a plurality of paging groups in an erase blocks of this NAND array, but the access that makes to be accessed in a plurality of storage unit within one second paging group of these paging groups in this erase blocks of this NAND array is minimized
Wherein the virtual erase blocks in a plurality of virtual erase blocks is videoed into one of them of these paging groups, and the paging group in these paging groups comprises coming the paging in these pagings mutual not adjacent to each other in comfortable this NAND array, and
Wherein the paging in these paging groups is not adjacent to each other in this NAND array.
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| US14/060,296 | 2013-10-22 | ||
| US14/060,296 US9025375B2 (en) | 2013-04-15 | 2013-10-22 | Memory disturb reduction for nonvolatile memory |
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| US20020099904A1 (en) * | 2001-01-19 | 2002-07-25 | Conley Kevin M. | Partial block data programming and reading operations in a non-volatile memory |
| CN102763166A (en) * | 2009-08-19 | 2012-10-31 | 桑迪士克技术有限公司 | Selective memory cell program and erase |
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